Move includes to where they are needed. This allows to simplify

romstage.c files in mainboards.

Signed-off-by: Patrick Georgi <patrick.georgi@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5539 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

diff --git a/src/arch/i386/include/stddef.h b/src/arch/i386/include/stddef.h
index e4fc019c87ac6e38c3d01de9bbe9060caafa1d00..6583cc62efa457a0f6cf7470a343c3934bacfde5 100644 (file)
--- a/src/arch/i386/include/stddef.h
+++ b/src/arch/i386/include/stddef.h
@@ -8,7 +8,9 @@ typedef long ssize_t;
 typedef int wchar_t;
 typedef unsigned int wint_t;
 
+#ifndef NULL
 #define NULL ((void *)0)
+#endif
 
 #define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER)
 

diff --git a/src/cpu/amd/car/post_cache_as_ram.c b/src/cpu/amd/car/post_cache_as_ram.c
index 24ea8da5e6ff26f4196ea2ae80f924a910005a2b..58d38cd60315077e853e60fe69c381c65753f91a 100644 (file)
--- a/src/cpu/amd/car/post_cache_as_ram.c
+++ b/src/cpu/amd/car/post_cache_as_ram.c
@@ -1,6 +1,7 @@
 /* 2005.6 by yhlu
  * 2006.3 yhlu add copy data from CAR to ram
  */
+#include <string.h>
 #include <arch/stages.h>
 #include "cpu/amd/car/disable_cache_as_ram.c"
 

diff --git a/src/cpu/amd/model_10xxx/defaults.h b/src/cpu/amd/model_10xxx/defaults.h
index 98918ec312e204c6894e5fb414f37d13e6a78295..78c46d4eaf21ffce73e3411cdb8179ed7a23e25b 100644 (file)
--- a/src/cpu/amd/model_10xxx/defaults.h
+++ b/src/cpu/amd/model_10xxx/defaults.h
@@ -17,6 +17,8 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
+#include <northbridge/amd/amdmct/amddefs.h>
+#include <cpu/amd/mtrr.h>
 
 /*
  * Default MSR and errata settings.

diff --git a/src/cpu/amd/model_10xxx/init_cpus.c b/src/cpu/amd/model_10xxx/init_cpus.c
index 3a86be296f177f34a4b743e48676bd0275995bc5..a64cdd887492087cb880c714b800715b45adb6fa 100644 (file)
--- a/src/cpu/amd/model_10xxx/init_cpus.c
+++ b/src/cpu/amd/model_10xxx/init_cpus.c
@@ -18,6 +18,12 @@
  */
 
 #include "defaults.h"
+#include <stdlib.h>
+#include <cpu/x86/lapic.h>
+#include <cpu/x86/mtrr.h>
+#include <northbridge/amd/amdfam10/amdfam10.h>
+#include <northbridge/amd/amdht/AsPsDefs.h>
+#include <northbridge/amd/amdht/porting.h>
 
 //it takes the CONFIG_ENABLE_APIC_EXT_ID and CONFIG_APIC_ID_OFFSET and CONFIG_LIFT_BSP_APIC_ID
 #ifndef SET_FIDVID

diff --git a/src/cpu/amd/quadcore/quadcore.c b/src/cpu/amd/quadcore/quadcore.c
index d66f56c881af1bb19d753b4a4e57f956660b84b1..142a270125cc03e731ed2d19e78ac17045ae0543 100644 (file)
--- a/src/cpu/amd/quadcore/quadcore.c
+++ b/src/cpu/amd/quadcore/quadcore.c
@@ -17,6 +17,7 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
+#include <console/console.h>
 
 #ifndef SET_NB_CFG_54
        #define SET_NB_CFG_54 1

diff --git a/src/include/cpu/amd/model_10xxx_msr.h b/src/include/cpu/amd/model_10xxx_msr.h
index a774125cb040aec8a4f447a957456027f007cd69..f497eb3a8271c8a5df83af888be8a8a8365ae55b 100644 (file)
--- a/src/include/cpu/amd/model_10xxx_msr.h
+++ b/src/include/cpu/amd/model_10xxx_msr.h
@@ -20,6 +20,8 @@
 #ifndef CPU_AMD_MODEL_10XXX_MSR_H
 #define CPU_AMD_MODEL_10XXX_MSR_H
 
+#include <cpu/x86/msr.h>
+
 #define HWCR_MSR                       0xC0010015
 #define NB_CFG_MSR                     0xC001001f
 #define LS_CFG_MSR                     0xC0011020

diff --git a/src/northbridge/amd/amdht/ht_wrapper.c b/src/northbridge/amd/amdht/ht_wrapper.c
index f02ce44f80b9ac8ca8c27e562f36261474cf237e..38733c9863584575bd4739c5789f53746cb7e8ba 100644 (file)
--- a/src/northbridge/amd/amdht/ht_wrapper.c
+++ b/src/northbridge/amd/amdht/ht_wrapper.c
@@ -17,6 +17,9 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
  */
 
+#include <cpu/x86/msr.h>
+#include <console/console.h>
+#include <northbridge/amd/amdfam10/amdfam10.h>
 
 /*----------------------------------------------------------------------------
  *                     TYPEDEFS, DEFINITIONS AND MACROS

diff --git a/src/northbridge/amd/amdmct/mct/mctmtr_d.c b/src/northbridge/amd/amdmct/mct/mctmtr_d.c
index 76cf9806afb5036ebf57db536105df01e6df8a56..64500f0d58d5030cd66eacb1c033fc8fd7994b4f 100644 (file)
--- a/src/northbridge/amd/amdmct/mct/mctmtr_d.c
+++ b/src/northbridge/amd/amdmct/mct/mctmtr_d.c
@@ -19,6 +19,7 @@
 
 
 #include "mct_d.h"
+#include <cpu/amd/mtrr.h>
 
 static void SetMTRRrangeWB_D(u32 Base, u32 *pLimit, u32 *pMtrrAddr);
 static void SetMTRRrange_D(u32 Base, u32 *pLimit, u32 *pMtrrAddr, u16 MtrrType);

diff --git a/src/superio/smsc/smscsuperio/smscsuperio_early_serial.c b/src/superio/smsc/smscsuperio/smscsuperio_early_serial.c
index 28022b649e3ef427224f8eab28d47ba55d8cd96d..de2e8917428195b56268b66531cc8477f051ce2a 100644 (file)
--- a/src/superio/smsc/smscsuperio/smscsuperio_early_serial.c
+++ b/src/superio/smsc/smscsuperio/smscsuperio_early_serial.c
@@ -19,6 +19,7 @@
  */
 
 #include <arch/romcc_io.h>
+#include <device/pnp_def.h>
 
 /* All known/supported SMSC Super I/Os have the same logical device IDs
  * for the serial ports (COM1, COM2).