memory must be clear with 0s because otherwise the resources of K8 will be
totally messed up.
res = probe_resource(dev, 0x100 + (reg | link));
This is called with dev = NULL and this is no good for probe_resource at all.
The attached patch fixes the potential problems and of course the problem
itself. On one particular place was missing test if the device really exists.
This was copied to fam10 and perhaps the same issue is in v3 (DID NOT check).
The rest of the patch is just very paranoid and do all checkings.
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Myles Watson <mylesgw@gmail.com>
--This line, and those below, will be igno
red--
M src/devices/pci_ops.c
M src/northbridge/amd/amdk8/northbridge.c
M src/northbridge/amd/amdfam10/northbridge.c
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4030
2b7e53f0-3cfb-0310-b3e9-
8179ed1497e1
static struct bus *get_pbus(device_t dev)
{
static struct bus *get_pbus(device_t dev)
{
- struct bus *pbus = dev->bus;
+ struct bus *pbus;
+
+ if (!dev)
+ printk_alert("get_pbus: dev is NULL!\n");
+
+ pbus = dev->bus;
+
while(pbus && pbus->dev && !ops_pci_bus(pbus)) {
if (pbus == pbus->dev->bus) {
printk_alert("%s in endless loop looking for a parent "
while(pbus && pbus->dev && !ops_pci_bus(pbus)) {
if (pbus == pbus->dev->bus) {
printk_alert("%s in endless loop looking for a parent "
for(nodeid = 0; !res && (nodeid < NODE_NUMS); nodeid++) {
device_t dev;
dev = __f0_dev[nodeid];
for(nodeid = 0; !res && (nodeid < NODE_NUMS); nodeid++) {
device_t dev;
dev = __f0_dev[nodeid];
for(link = 0; !res && (link < 8); link++) {
res = probe_resource(dev, 0x1000 + reg + (link<<16)); // 8 links, 0x1000 man f1,
}
for(link = 0; !res && (link < 8); link++) {
res = probe_resource(dev, 0x1000 + reg + (link<<16)); // 8 links, 0x1000 man f1,
}
unsigned nodeid, link;
int result;
res = 0;
unsigned nodeid, link;
int result;
res = 0;
- for(nodeid = 0; !res && (nodeid < 8); nodeid++) {
+ for(nodeid = 0; !res && (nodeid < FX_DEVS); nodeid++) {
device_t dev;
dev = __f0_dev[nodeid];
device_t dev;
dev = __f0_dev[nodeid];
for(link = 0; !res && (link < 3); link++) {
res = probe_resource(dev, 0x100 + (reg | link));
}
for(link = 0; !res && (link < 3); link++) {
res = probe_resource(dev, 0x100 + (reg | link));
}
mem_hole.hole_startk = HW_MEM_HOLE_SIZEK;
mem_hole.node_id = -1;
mem_hole.hole_startk = HW_MEM_HOLE_SIZEK;
mem_hole.node_id = -1;
- for (i = 0; i < 8; i++) {
+ for (i = 0; i < FX_DEVS; i++) {
uint32_t base;
uint32_t hole;
base = f1_read_config32(0x40 + (i << 3));
if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
continue;
}
uint32_t base;
uint32_t hole;
base = f1_read_config32(0x40 + (i << 3));
if ((base & ((1<<1)|(1<<0))) != ((1<<1)|(1<<0))) {
continue;
}
+ if (!__f1_dev[i])
+ continue;
hole = pci_read_config32(__f1_dev[i], 0xf0);
if(hole & 1) { // we find the hole
mem_hole.hole_startk = (hole & (0xff<<24)) >> 10;
hole = pci_read_config32(__f1_dev[i], 0xf0);
if(hole & 1) { // we find the hole
mem_hole.hole_startk = (hole & (0xff<<24)) >> 10;
limit = f1_read_config32(0x44 + (i << 3));
f1_write_config32(0x44 + (i << 3),limit - (hole_sizek << 2));
dev = __f1_dev[i];
limit = f1_read_config32(0x44 + (i << 3));
f1_write_config32(0x44 + (i << 3),limit - (hole_sizek << 2));
dev = __f1_dev[i];
- hoist = pci_read_config32(dev, 0xf0);
- if(hoist & 1) {
- pci_write_config32(dev, 0xf0, 0);
- }
- else {
- base = pci_read_config32(dev, 0x40 + (i << 3));
- f1_write_config32(0x40 + (i << 3),base - (hole_sizek << 2));
+ if (dev) {
+ hoist = pci_read_config32(dev, 0xf0);
+ if(hoist & 1) {
+ pci_write_config32(dev, 0xf0, 0);
+ } else {
+ base = pci_read_config32(dev, 0x40 + (i << 3));
+ f1_write_config32(0x40 + (i << 3),base - (hole_sizek << 2));
+ }
}
static uint32_t hoist_memory(unsigned long hole_startk, int i)
}
static uint32_t hoist_memory(unsigned long hole_startk, int i)
base |= (4*1024*1024)<<2;
f1_write_config32(0x40 + (i<<3), base);
}
base |= (4*1024*1024)<<2;
f1_write_config32(0x40 + (i<<3), base);
}
{
hoist = /* hole start address */
((hole_startk << 10) & 0xff000000) +
{
hoist = /* hole start address */
((hole_startk << 10) & 0xff000000) +
#if HW_MEM_HOLE_SIZE_AUTO_INC == 1
//We need to double check if the mmio_basek is valid for hole setting, if it is equal to basek, we need to decrease it some
uint32_t basek_pri;
#if HW_MEM_HOLE_SIZE_AUTO_INC == 1
//We need to double check if the mmio_basek is valid for hole setting, if it is equal to basek, we need to decrease it some
uint32_t basek_pri;
- for (i = 0; i < 8; i++) {
+ for (i = 0; i < FX_DEVS; i++) {
uint32_t base;
uint32_t basek;
base = f1_read_config32(0x40 + (i << 3));
uint32_t base;
uint32_t basek;
base = f1_read_config32(0x40 + (i << 3));
- for(i = 0; i < 8; i++) {
+ for(i = 0; i < FX_DEVS; i++) {
uint32_t base, limit;
unsigned basek, limitk, sizek;
base = f1_read_config32(0x40 + (i << 3));
uint32_t base, limit;
unsigned basek, limitk, sizek;
base = f1_read_config32(0x40 + (i << 3));