Make Asus A8V-E SE better ACPI citizen.

Use the SSDT autogen infrastructure to support the automatic reserved resources,
automatic P-state generation and automatic _CRS PCI0 method.

Change-Id: Ic56a92eeb70a0a2a2d6de2507009ec3a832c83b3
Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Reviewed-on: http://review.coreboot.org/251
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

diff --git a/src/mainboard/asus/a8v-e_se/acpi_tables.c b/src/mainboard/asus/a8v-e_se/acpi_tables.c
index fe8d4757eeb21a815efd0af5d9e0ae33aa8155d1..e08b3053d7343833881a0e56ec28f006aa3f9407 100644 (file)
--- a/src/mainboard/asus/a8v-e_se/acpi_tables.c
+++ b/src/mainboard/asus/a8v-e_se/acpi_tables.c
@@ -31,6 +31,8 @@
 #include <device/pci_ids.h>
 #include "southbridge/via/vt8237r/vt8237r.h"
 #include "southbridge/via/k8t890/k8t890.h"
+#include "northbridge/amd/amdk8/acpi.h"
+#include <cpu/amd/model_fxx_powernow.h>
 
 extern const unsigned char AmlCode[];
 
@@ -81,6 +83,14 @@ unsigned long acpi_fill_madt(unsigned long current)
        return current;
 }
 
+unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id)
+{
+       k8acpi_write_vars();
+       amd_model_fxx_generate_powernow(0, 0, 0);
+       acpigen_write_mainboard_resources("\\_SB.PCI0.MBRS", "_CRS");
+       return (unsigned long) (acpigen_get_current());
+}
+
 unsigned long write_acpi_tables(unsigned long start)
 {
        unsigned long current;
@@ -91,6 +101,7 @@ unsigned long write_acpi_tables(unsigned long start)
        acpi_mcfg_t *mcfg;
        acpi_fadt_t *fadt;
        acpi_facs_t *facs;
+       acpi_header_t *ssdt;
        acpi_header_t *dsdt;
 
        /* Align ACPI tables to 16 byte. */
@@ -151,6 +162,14 @@ unsigned long write_acpi_tables(unsigned long start)
        current += srat->header.length;
        acpi_add_table(rsdp, srat);
 
+       /* SSDT */
+       printk(BIOS_DEBUG, "ACPI:    * SSDT\n");
+       ssdt = (acpi_header_t *)current;
+
+       acpi_create_ssdt_generator(ssdt, "DYNADATA");
+       current += ssdt->length;
+       acpi_add_table(rsdp, ssdt);
+
        printk(BIOS_INFO, "ACPI: done.\n");
        return current;
 }

diff --git a/src/mainboard/asus/a8v-e_se/dsdt.asl b/src/mainboard/asus/a8v-e_se/dsdt.asl
index 6a46102b5a7e2aa9e408ead73a6d87a47c199fd1..16ad92c077db413a1a92ff477142cac502b38b10 100644 (file)
--- a/src/mainboard/asus/a8v-e_se/dsdt.asl
+++ b/src/mainboard/asus/a8v-e_se/dsdt.asl
@@ -24,12 +24,7 @@
 
 DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE  ", "COREBOOT", 1)
 {
-       /* Define the main processor.*/
-       Scope (\_PR)
-       {
-               Processor (\_PR.CPU0, 0x00, 0x000000, 0x00) {}
-               Processor (\_PR.CPU1, 0x01, 0x000000, 0x00) {}
-       }
+        #include "northbridge/amd/amdk8/util.asl"
 
        /* For now only define 2 power states:
         *  - S0 which is fully on
@@ -50,8 +45,44 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE  ", "COREBOOT", 1)
                        Name (_UID, 0x00)
                        Name (_BBN, 0x00)
 
+                   External (BUSN)
+                   External (MMIO)
+                   External (PCIO)
+                   External (SBLK)
+                   External (TOM1)
+                   External (HCLK)
+                   External (SBDN)
+                   External (HCDN)
+
+                   Method (_CRS, 0, NotSerialized)
+                       {
+                           Name (BUF0, ResourceTemplate ()
+                           {
+                               IO (Decode16,
+                               0x0CF8,             // Address Range Minimum
+                               0x0CF8,             // Address Range Maximum
+                               0x01,               // Address Alignment
+                               0x08,               // Address Length
+                               )
+                               WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+                               0x0000,             // Address Space Granularity
+                               0x0000,             // Address Range Minimum
+                               0x0CF7,             // Address Range Maximum
+                               0x0000,             // Address Translation Offset
+                               0x0CF8,             // Address Length
+                               ,, , TypeStatic)
+                           })
+                               /* Methods bellow use SSDT to get actual MMIO regs
+                                  The IO ports are from 0xd00, optionally an VGA,
+                                  otherwise the info from MMIO is used.
+                                */
+                               Concatenate (\_SB.GMEM (0x00, \_SB.PCI0.SBLK), BUF0, Local1)
+                               Concatenate (\_SB.GIOR (0x00, \_SB.PCI0.SBLK), Local1, Local2)
+                               Concatenate (\_SB.GWBN (0x00, \_SB.PCI0.SBLK), Local2, Local3)
+                               Return (Local3)
+                       }
+
                        /* PCI Routing Table */
-                       /* aaa */
                        Name (_PRT, Package () {
                                Package (0x04) { 0x000BFFFF, 0x00, 0x00, 0x10 }, /* Slot 0xB */
                                Package (0x04) { 0x000BFFFF, 0x01, 0x00, 0x11 },
@@ -206,6 +237,13 @@ DefinitionBlock ("DSDT.aml", "DSDT", 1, "CORE  ", "COREBOOT", 1)
                                        }
                                }
                        }
+                       /* Dummy device to hold auto generated reserved resources */
+                       Device(MBRS) {
+                               Name (_HID, EisaId ("PNP0C02"))
+                               Name (_UID, 0x01)
+                               External(_CRS) /* Resource Template in SSDT */
+                       }
+
                }
        }
 }