Add AMD Fam10 B3 default settings to match AMD example code.

Includes setting for most recent errata.

Signed-off-by: Marc Jones <marc.jones@amd.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3435 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

diff --git a/src/cpu/amd/model_10xxx/defaults.h b/src/cpu/amd/model_10xxx/defaults.h
index 2741cce2b181bede29b594dc44e8929f2e2197da..2497c5ba8ec948e6a03f6d2d8b43864ec6048de3 100644 (file)
--- a/src/cpu/amd/model_10xxx/defaults.h
+++ b/src/cpu/amd/model_10xxx/defaults.h
@@ -46,10 +46,6 @@ static const struct {
          0xF << 19, 0x00000000,
          0xF << 19, 0x00000000 },      /* [RtryHt[0..3]]=1 */
 
-       { MC4_CTL_MASK, AMD_DR_ALL, AMD_PTYPE_ALL,
-         0x1 << 10, 0x00000000,
-         0x1 << 10, 0x00000000 },      /* [GartTblWkEn]=1 */
-
        { DC_CFG, AMD_DR_ALL, AMD_PTYPE_SVR,
          0x00000000, 0x00000004,
          0x00000000, 0x0000000C },     /* [REQ_CTR] = 1 for Server */
@@ -68,7 +64,7 @@ static const struct {
 
        { DC_CFG, AMD_DR_ALL, AMD_PTYPE_ALL,
          1 << 24, 0x00000000,
-         1 << 24, 0x00000000 },        /* Erratum #202 [DIS_PIGGY_BACK_SCRUB]=1 */
+         1 << 24, 0x00000000 },        /* Erratum #261 [DIS_PIGGY_BACK_SCRUB]=1 */
 
        { LS_CFG, AMD_DR_GT_B0, AMD_PTYPE_ALL,
          0 << 1, 0x00000000,
@@ -160,12 +156,15 @@ static const struct {
          0x00000100, 0x00000100 },     /* [8] MstrAbrtEn */
 
        { 3, 0x44, AMD_DR_ALL, AMD_PTYPE_ALL,
-         0x0A100044, 0x0A300044 },     /* [27] NB MCA to CPU0 Enable,
-                                          [25] DisPciCfgCpuErrRsp,
-                                          [21] SyncOnErr=0,
-                                          [20] SyncOnWDTEn=1,
-                                          [6] CpuErrDis,
-                                          [2] SyncOnUcEccEn=1 */
+         0x4A30005C, 0x4A30005C },     /* [30] SyncOnDramAdrParErrEn = 1,
+                                          [27] NbMcaToMstCpuEn = 1,
+                                          [25] DisPciCfgCpuErrRsp = 1,
+                                          [21] SyncOnAnyErrEn = 1,
+                                          [20] SyncOnWDTEn = 1,
+                                          [6] CpuErrDis = 1,
+                                          [4] SyncPktPropDis = 1,
+                                          [3] SyncPktGenDis = 1,
+                                          [2] SyncOnUcEccEn = 1 */
 
        /* XBAR buffer settings */
        { 3, 0x6C, AMD_DR_ALL, AMD_PTYPE_ALL,
@@ -222,7 +221,7 @@ static const struct {
        { 3, 0x84, AMD_DR_ALL, AMD_PTYPE_ALL,
          0xA0E641E6, 0xFFFFFFFF },
 
-       { 3, 0xA0, AMD_DR_ALL, AMD_PTYPE_MOB,
+       { 3, 0xA0, AMD_DR_ALL, AMD_PTYPE_MOB | AMD_PTYPE_DSK,
          0x00000080, 0x00000080 },     /* [7] PSIVidEnable */
 
        { 3, 0xA0, AMD_DR_ALL, AMD_PTYPE_ALL,
@@ -250,9 +249,13 @@ static const struct {
 
        /* Extended NB MCA Config Register */
        { 3, 0x180, AMD_DR_ALL, AMD_PTYPE_ALL,
-         0x00700022, 0x00700022 },     /* [5]     = DisPciCfgCpuMstAbtRsp
-                                          [22:20] = SyncFloodOn_Err = 7,
-                                          [1] = SyncFloodOnUsPwDataErr = 1 */
+         0x007003E2, 0x007003E2 },     /* [22:20] = SyncFloodOn_Err = 7,
+                                          [9] SyncOnUncNbAryEn = 1 ,
+                                          [8] SyncOnProtEn = 1,
+                                          [7] SyncFloodOnTgtAbtErr = 1,
+                                          [6] SyncFloodOnDatErr = 1,
+                                          [5] DisPciCfgCpuMstAbtRsp = 1,
+                                          [1] SyncFloodOnUsPwDataErr = 1 */
 
        /* L3 Control Register */
        { 3, 0x1B8, AMD_DR_ALL, AMD_PTYPE_ALL,

diff --git a/src/cpu/amd/model_10xxx/init_cpus.c b/src/cpu/amd/model_10xxx/init_cpus.c
index c67ef6ce81d0a912a8fb56a2bfcfe11863067267..63859b004b7824d39081ddc0c3696cf036299efb 100644 (file)
--- a/src/cpu/amd/model_10xxx/init_cpus.c
+++ b/src/cpu/amd/model_10xxx/init_cpus.c
@@ -669,6 +669,35 @@ u32 get_platform_type(void)
 }
 
 
+void AMD_SetupPSIVID_d (u32 platform_type, u8 node)
+{
+       u32 dword;
+       int i;
+       msr_t msr;
+
+       if (platform_type & (AMD_PTYPE_MOB | AMD_PTYPE_DSK)) {
+
+       /* The following code sets the PSIVID to the lowest support P state
+        * assuming that the VID for the lowest power state is below
+        * the VDD voltage regulator threshold. (This also assumes that there
+        * is a Pstate lower than P0)
+        */
+
+               for( i = 4; i >= 0; i--) {
+                       msr = rdmsr(PS_REG_BASE + i);
+                       /*  Pstate valid? */
+                       if (msr.hi & PS_EN_MASK) {
+                               dword = pci_read_config32(NODE_PCI(i,3), 0xA0);
+                               dword &= ~0x7F;
+                               dword |= (msr.lo >> 9) & 0x7F;
+                               pci_write_config32(NODE_PCI(i,3), 0xA0, dword);
+                               break;
+                       }
+               }
+       }
+}
+
+
 /**
  * AMD_CpuFindCapability - Traverse PCI capability list to find host HT links.
  *  HT Phy operations are not valid on links that aren't present, so this
@@ -854,9 +883,12 @@ void cpuSetAMDPCI(u8 node)
 
        printk_debug("cpuSetAMDPCI %02d", node);
 
+
        revision = mctGetLogicalCPUID(node);
        platform = get_platform_type();
 
+       AMD_SetupPSIVID_d(platform, node);      /* Set PSIVID offset which is not table driven */
+
        for(i = 0; i < sizeof(fam10_pci_default)/sizeof(fam10_pci_default[0]); i++) {
                if ((fam10_pci_default[i].revision & revision) &&
                    (fam10_pci_default[i].platform & platform)) {