Intel cpus: cache actual size of the Flash ROM device

Cache was enabled for the last 4 MB below 4 GB when ramstage is
loaded. This does not cover the case of a 8 MB Flash and could
overlap with some system device placed at high memory.

Use the actual device size for the cache region. Mainboard
may override this with Kconfig CACHE_ROM_SIZE if necessary.

Change-Id: I622223b1e2af0b3c1831f3570b74eacfde7189dc
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/641
Tested-by: build bot (Jenkins)
Reviewed-by: Idwer Vollering <vidwer@gmail.com>
Reviewed-by: Patrick Georgi <patrick@georgi-clan.de>

diff --git a/src/cpu/intel/car/cache_as_ram_ht.inc b/src/cpu/intel/car/cache_as_ram_ht.inc
index 08f5b1138dec5055efbb20c470b5501048c3d3d6..ed207db7b17dfeaf20dd2a126fcaff7dd8061bfa 100644 (file)
--- a/src/cpu/intel/car/cache_as_ram_ht.inc
+++ b/src/cpu/intel/car/cache_as_ram_ht.inc
@@ -25,6 +25,9 @@
 #define CPU_MAXPHYADDR 36
 #define CPU_PHYSMASK_HI  (1 << (CPU_MAXPHYADDR - 32) - 1)
 
 #define CPU_MAXPHYADDR 36
 #define CPU_PHYSMASK_HI  (1 << (CPU_MAXPHYADDR - 32) - 1)
 

+/* Base address to cache all of Flash ROM, just below 4GB. */
+#define CACHE_ROM_BASE ((1<<22 - CONFIG_CACHE_ROM_SIZE>>10)<<10)
+

 #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
 #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
 
 #define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
 #define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
 


@@ -203,13 +206,13 @@ clear_mtrrs:
        movl    $CPU_PHYSMASK_HI, %edx
        wrmsr
 
        movl    $CPU_PHYSMASK_HI, %edx
        wrmsr
 

-       /* Enable caching and Speculative Reads for the last 4MB. */
+       /* Enable caching and Speculative Reads for Flash ROM device. */

        movl    $MTRRphysBase_MSR(1), %ecx
        movl    $MTRRphysBase_MSR(1), %ecx

-       movl    $(0xffc00000 | MTRR_TYPE_WRPROT), %eax
+       movl    $(CACHE_ROM_BASE | MTRR_TYPE_WRPROT), %eax

        xorl    %edx, %edx
        wrmsr
        movl    $MTRRphysMask_MSR(1), %ecx
        xorl    %edx, %edx
        wrmsr
        movl    $MTRRphysMask_MSR(1), %ecx

-       movl    $(~(4 * 1024 * 1024 - 1) | MTRRphysMaskValid), %eax
+       movl    $(~(CONFIG_CACHE_ROM_SIZE - 1) | MTRRphysMaskValid), %eax

        movl    $CPU_PHYSMASK_HI, %edx
        wrmsr
 
        movl    $CPU_PHYSMASK_HI, %edx
        wrmsr
 

diff --git a/src/mainboard/Kconfig b/src/mainboard/Kconfig
index a968b51563be44eb699489c91e13334092796b55..051ae45dff364e654305de0e583900e2232d1e6c 100644 (file)
--- a/src/mainboard/Kconfig
+++ b/src/mainboard/Kconfig
@@ -301,6 +301,10 @@ config ROM_SIZE
        default 0x800000 if COREBOOT_ROMSIZE_KB_8192
        default 0x1000000 if COREBOOT_ROMSIZE_KB_16384
 
        default 0x800000 if COREBOOT_ROMSIZE_KB_8192
        default 0x1000000 if COREBOOT_ROMSIZE_KB_16384
 

+config CACHE_ROM_SIZE
+       hex
+       default ROM_SIZE
+

 config ENABLE_POWER_BUTTON
        bool "Enable the power button" if POWER_BUTTON_IS_OPTIONAL
        default y if POWER_BUTTON_DEFAULT_ENABLE
 config ENABLE_POWER_BUTTON
        bool "Enable the power button" if POWER_BUTTON_IS_OPTIONAL
        default y if POWER_BUTTON_DEFAULT_ENABLE