Add GNB internal graphic interrupt,
correct southbridge hd audio device interrupt. and remove the
dead code already commented out.
south_station, union_station, inagua, persimmon and e350m1 mainboard
are included herein.
Change-Id: Ic7618d80e0432ed0e22d1c16e1adb8ba6cea2e59
Signed-off-by: Kerry Sheh <shekairui@gmail.com>
Signed-off-by: Kerry Sheh <kerry.she@amd.com>
Reviewed-on: http://review.coreboot.org/451
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
#define PCI_INT(bus, dev, int_sign, pin) \
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), apicid_sb800, (pin))
#define PCI_INT(bus, dev, int_sign, pin) \
smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, (bus), (((dev)<<2)|(int_sign)), apicid_sb800, (pin))
+ /* APU Internal Graphic Device*/
+ PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
+ PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]);
+
/* SMBUS */
PCI_INT(0x0, 0x14, 0x0, 0x10);
/* SMBUS */
PCI_INT(0x0, 0x14, 0x0, 0x10);
- /* HD Audio */
- PCI_INT(0x0, 0x14, 0x0, intr_data[0x13]);
+ /* Southbridge HD Audio */
+ PCI_INT(0x0, 0x14, 0x2, intr_data[0x13]);
/* USB */
PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]);
/* USB */
PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]);
PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]);
PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]);
PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]);
PCI_INT(0x0, 0x13, 0x1, intr_data[0x33]);
PCI_INT(0x0, 0x16, 0x0, intr_data[0x34]);
PCI_INT(0x0, 0x16, 0x1, intr_data[0x35]);
- PCI_INT(0x0, 0x14, 0x2, intr_data[0x36]);
+ PCI_INT(0x0, 0x14, 0x5, intr_data[0x36]);
/* sata */
PCI_INT(0x0, 0x11, 0x0, intr_data[0x40]);
/* sata */
PCI_INT(0x0, 0x11, 0x0, intr_data[0x40]);
#define PCI_INT(bus, dev, fn, pin)
#endif
#define PCI_INT(bus, dev, fn, pin)
#endif
+ /* APU Internal Graphic Device*/
+ PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
+ PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]);
+
//PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */
PCI_INT(0x0, 0x14, 0x0, 0x10);
//PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */
PCI_INT(0x0, 0x14, 0x0, 0x10);
+ /* Southbridge HD Audio: */
PCI_INT(0x0, 0x14, 0x2, 0x12);
PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); /* USB */
PCI_INT(0x0, 0x14, 0x2, 0x12);
PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); /* USB */
/* sata */
PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]);
/* sata */
PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]);
- /* PCI_INT(0x0, 0x14, 0x2, 0x12); */
-
/* on board NIC & Slot PCIE. */
/* PCI slots */
/* on board NIC & Slot PCIE. */
/* PCI slots */
#define PCI_INT(bus, dev, fn, pin)
#endif
#define PCI_INT(bus, dev, fn, pin)
#endif
+ /* APU Internal Graphic Device*/
+ PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
+ PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]);
+
//PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */
PCI_INT(0x0, 0x14, 0x0, 0x10);
//PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */
PCI_INT(0x0, 0x14, 0x0, 0x10);
+ /* Southbridge HD Audio: */
PCI_INT(0x0, 0x14, 0x2, 0x12);
PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); /* USB */
PCI_INT(0x0, 0x14, 0x2, 0x12);
PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); /* USB */
/* sata */
PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]);
/* sata */
PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]);
- /* PCI_INT(0x0, 0x14, 0x2, 0x12); */
-
/* on board NIC & Slot PCIE. */
/* PCI slots */
/* on board NIC & Slot PCIE. */
/* PCI slots */
#define PCI_INT(bus, dev, fn, pin)
#endif
#define PCI_INT(bus, dev, fn, pin)
#endif
+ /* APU Internal Graphic Device*/
+ PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
+ PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]);
+
//PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */
PCI_INT(0x0, 0x14, 0x0, 0x10);
//PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */
PCI_INT(0x0, 0x14, 0x0, 0x10);
+ /* Southbridge HD Audio: */
PCI_INT(0x0, 0x14, 0x2, 0x12);
PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); /* USB */
PCI_INT(0x0, 0x14, 0x2, 0x12);
PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); /* USB */
/* sata */
PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]);
/* sata */
PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]);
- /* PCI_INT(0x0, 0x14, 0x2, 0x12); */
-
/* on board NIC & Slot PCIE. */
/* PCI slots */
/* on board NIC & Slot PCIE. */
/* PCI slots */
#define PCI_INT(bus, dev, fn, pin)
#endif
#define PCI_INT(bus, dev, fn, pin)
#endif
+ /* APU Internal Graphic Device*/
+ PCI_INT(0x0, 0x01, 0x0, intr_data[0x02]);
+ PCI_INT(0x0, 0x01, 0x1, intr_data[0x03]);
+
//PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */
PCI_INT(0x0, 0x14, 0x0, 0x10);
//PCI_INT(0x0, 0x14, 0x1, 0x11); /* IDE. */
PCI_INT(0x0, 0x14, 0x0, 0x10);
+ /* Southbridge HD Audio: */
PCI_INT(0x0, 0x14, 0x2, 0x12);
PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); /* USB */
PCI_INT(0x0, 0x14, 0x2, 0x12);
PCI_INT(0x0, 0x12, 0x0, intr_data[0x30]); /* USB */
/* sata */
PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]);
/* sata */
PCI_INT(0x0, 0x11, 0x0, intr_data[0x41]);
- /* PCI_INT(0x0, 0x14, 0x2, 0x12); */
-
/* on board NIC & Slot PCIE. */
/* PCI slots */
/* on board NIC & Slot PCIE. */
/* PCI slots */