+++ /dev/null
-##
-## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
-##
-if USE_FALLBACK_IMAGE
- default ROM_SECTION_SIZE = FALLBACK_SIZE
- default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
-else
- default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
- default ROM_SECTION_OFFSET = 0
-end
-
-##
-## Compute the start location and size size of
-## The linuxBIOS bootloader.
-##
-default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
-default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
-
-##
-## Compute where this copy of linuxBIOS will start in the boot rom
-##
-default _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
-
-##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
-## execution speed.
-##
-## XIP_ROM_SIZE must be a power of 2.
-## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
-##
-default XIP_ROM_SIZE=65536
-default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
-
-##
-## Set all of the defaults for an x86 architecture
-##
-
-arch i386 end
-
-##
-## Build the objects we have code for in this directory.
-##
-
-driver mainboard.o
-if HAVE_MP_TABLE object mptable.o end
-if HAVE_PIRQ_TABLE object irq_tables.o end
-#object reset.o
-
-## ATI Rage XL framebuffering graphics driver
-dir /drivers/ati/ragexl
-
-##
-## Romcc output
-##
-makerule ./failover.E
- depends "$(MAINBOARD)/failover.c ./romcc"
- action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
-end
-
-makerule ./failover.inc
- depends "$(MAINBOARD)/failover.c ./romcc"
- action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
-end
-
-makerule ./auto.E
- depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
- action "./romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc
- depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
- action "./romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
-end
-
-##
-## Build our 16 bit and 32 bit linuxBIOS entry code
-##
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
-
-##
-## Build our reset vector (This is where linuxBIOS is entered)
-##
-if USE_FALLBACK_IMAGE
- mainboardinit cpu/x86/16bit/reset16.inc
- ldscript /cpu/x86/16bit/reset16.lds
-else
- mainboardinit cpu/x86/32bit/reset32.inc
- ldscript /cpu/x86/32bit/reset32.lds
-end
-
-### Should this be in the northbridge code?
-mainboardinit arch/i386/lib/cpu_reset.inc
-
-##
-## Include an id string (For safe flashing)
-##
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-
-###
-### This is the early phase of linuxBIOS startup
-### Things are delicate and we test to see if we should
-### failover to another image.
-###
-if USE_FALLBACK_IMAGE
- ldscript /arch/i386/lib/failover.lds
- mainboardinit ./failover.inc
-end
-
-###
-### O.k. We aren't just an intermediary anymore!
-###
-
-##
-## Setup RAM
-##
-mainboardinit cpu/x86/fpu/enable_fpu.inc
-mainboardinit cpu/x86/mmx/enable_mmx.inc
-mainboardinit cpu/x86/sse/enable_sse.inc
-mainboardinit ./auto.inc
-mainboardinit cpu/x86/sse/disable_sse.inc
-mainboardinit cpu/x86/mmx/disable_mmx.inc
-
-##
-## Include the secondary Configuration files
-##
-dir /pc80
-config chip.h
-
-# config for Iwill/DK8S2
-chip northbridge/amd/amdk8/root_complex
- device pci_domain 0 on
- chip northbridge/amd/amdk8
- device pci 18.0 on # LDT 0
- chip southbridge/amd/amd8131
- device pci 0.0 on end
- device pci 0.1 on end
- device pci 1.0 on end
- device pci 1.1 on end
- end
- chip southbridge/amd/amd8111
- # this "device pci 0.0" is the parent the next one
- # PCI bridge
- device pci 0.0 on
- device pci 0.0 on end
- device pci 0.1 on end
- device pci 0.2 on end
- device pci 1.0 off end
- end
- device pci 1.0 on
- chip superio/winbond/w83627hf
- device pnp 2e.0 on # Floppy
- io 0x60 = 0x3f0
- irq 0x70 = 6
- drq 0x74 = 2
- end
- device pnp 2e.1 off # Parallel Port
- io 0x60 = 0x378
- irq 0x70 = 7
- end
- device pnp 2e.2 on # Com1
- io 0x60 = 0x3f8
- irq 0x70 = 4
- end
- device pnp 2e.3 off # Com2
- io 0x60 = 0x2f8
- irq 0x70 = 3
- end
- device pnp 2e.5 on # Keyboard
- io 0x60 = 0x60
- io 0x62 = 0x64
- irq 0x70 = 1
- irq 0x72 = 12
- end
- device pnp 2e.6 off end # CIR
- device pnp 2e.7 off end # GAME_MIDI_GIPO1
- device pnp 2e.8 off end # GPIO2
- device pnp 2e.9 off end # GPIO3
- device pnp 2e.a off end # ACPI
- device pnp 2e.b on # HW Monitor
- io 0x60 = 0x290
- end
- register "com1" = "{1}"
- # register "com1" = "{1, 0, 0x3f8, 4}"
- # register "lpt" = "{1}"
- end
- end
- device pci 1.1 on end
- device pci 1.2 on end
- device pci 1.3 on end
- device pci 1.5 off end
- device pci 1.6 off end
- end
- end # LDT0
- device pci 18.0 on end # LDT1
- device pci 18.0 on end # LDT2
- device pci 18.1 on end
- device pci 18.2 on end
- device pci 18.3 on end
- end
- chip northbridge/amd/amdk8
- device pci 19.0 on end
- device pci 19.0 on end
- device pci 19.0 on end
- device pci 19.1 on end
- device pci 19.2 on end
- device pci 19.3 on end
- end
- end
- device apic_cluster 0 on
- chip cpu/amd/socket_940
- device apic 0 on end
- end
- chip cpu/amd/socket_940
- device apic 1 on end
- end
- end
-end
-
+++ /dev/null
-uses HAVE_MP_TABLE
-uses HAVE_PIRQ_TABLE
-uses USE_FALLBACK_IMAGE
-uses HAVE_FALLBACK_BOOT
-uses HAVE_HARD_RESET
-uses IRQ_SLOT_COUNT
-uses HAVE_OPTION_TABLE
-uses CONFIG_MAX_CPUS
-uses CONFIG_MAX_PHYSICAL_CPUS
-uses CONFIG_IOAPIC
-uses CONFIG_SMP
-uses FALLBACK_SIZE
-uses ROM_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_IMAGE_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_SECTION_OFFSET
-uses CONFIG_ROM_STREAM
-uses CONFIG_ROM_STREAM_START
-uses PAYLOAD_SIZE
-uses _ROMBASE
-uses XIP_ROM_SIZE
-uses XIP_ROM_BASE
-uses STACK_SIZE
-uses HEAP_SIZE
-uses USE_OPTION_TABLE
-uses LB_CKS_RANGE_START
-uses LB_CKS_RANGE_END
-uses LB_CKS_LOC
-uses MAINBOARD
-uses MAINBOARD_PART_NUMBER
-uses MAINBOARD_VENDOR
-uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses LINUXBIOS_EXTRA_VERSION
-uses _RAMBASE
-uses TTYS0_BAUD
-uses TTYS0_BASE
-uses TTYS0_LCS
-uses DEFAULT_CONSOLE_LOGLEVEL
-uses MAXIMUM_CONSOLE_LOGLEVEL
-uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-uses CONFIG_CONSOLE_SERIAL8250
-uses HAVE_INIT_TIMER
-uses CONFIG_GDB_STUB
-uses CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses OBJCOPY
-
-uses CONFIG_USE_INIT
-
-## ROM_SIZE is the size of boot ROM that this board will use.
-default ROM_SIZE=524288
-
-###
-### Build options
-###
-
-##
-## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
-##
-default FALLBACK_SIZE=0x40000
-
-##
-## Build code for the fallback boot
-##
-default HAVE_FALLBACK_BOOT=1
-
-##
-## Build code to reset the motherboard from linuxBIOS
-##
-default HAVE_HARD_RESET=1
-
-##
-## Build code to export a programmable irq routing table
-##
-default HAVE_PIRQ_TABLE=1
-default IRQ_SLOT_COUNT=9
-
-##
-## Build code to export an x86 MP table
-## Useful for specifying IRQ routing values
-##
-default HAVE_MP_TABLE=1
-
-##
-## Build code to export a CMOS option table
-##
-default HAVE_OPTION_TABLE=1
-
-##
-## Move the default LinuxBIOS cmos range off of AMD RTC registers
-##
-default LB_CKS_RANGE_START=49
-default LB_CKS_RANGE_END=122
-default LB_CKS_LOC=123
-
-##
-## Build code for SMP support
-## Only worry about 2 micro processors
-##
-default CONFIG_SMP=1
-default CONFIG_MAX_CPUS=2
-default CONFIG_MAX_PHYSICAL_CPUS=2
-
-##
-## Build code to setup a generic IOAPIC
-##
-default CONFIG_IOAPIC=1
-
-##
-## Clean up the motherboard id strings
-##
-default MAINBOARD_PART_NUMBER="HDAMA"
-default MAINBOARD_VENDOR="ARIMA"
-default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x161f
-default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3016
-
-
-###
-### LinuxBIOS layout values
-###
-
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
-default ROM_IMAGE_SIZE = 65536
-
-##
-## Use a small 8K stack
-##
-default STACK_SIZE=0x2000
-
-##
-## Use a small 16K heap
-##
-default HEAP_SIZE=0x4000
-
-##
-## Only use the option table in a normal image
-##
-default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
-
-##
-## LinuxBIOS C code runs at this location in RAM
-##
-default _RAMBASE=0x00004000
-
-##
-## Load the payload from the ROM
-##
-default CONFIG_ROM_STREAM = 1
-
-###
-### Defaults of options that you may want to override in the target config file
-###
-
-##
-## The default compiler
-##
-#default CC="$(CROSS_COMPILE)gcc -m32"
-#default HOSTCC="gcc"
-
-##
-## Disable the gdb stub by default
-##
-default CONFIG_GDB_STUB=0
-
-##
-## The Serial Console
-##
-
-# To Enable the Serial Console
-default CONFIG_CONSOLE_SERIAL8250=1
-
-## Select the serial console baud rate
-default TTYS0_BAUD=115200
-#default TTYS0_BAUD=57600
-#default TTYS0_BAUD=38400
-#default TTYS0_BAUD=19200
-#default TTYS0_BAUD=9600
-#default TTYS0_BAUD=4800
-#default TTYS0_BAUD=2400
-#default TTYS0_BAUD=1200
-
-# Select the serial console base port
-default TTYS0_BASE=0x3f8
-
-# Select the serial protocol
-# This defaults to 8 data bits, 1 stop bit, and no parity
-default TTYS0_LCS=0x3
-
-##
-### Select the linuxBIOS loglevel
-##
-## EMERG 1 system is unusable
-## ALERT 2 action must be taken immediately
-## CRIT 3 critical conditions
-## ERR 4 error conditions
-## WARNING 5 warning conditions
-## NOTICE 6 normal but significant condition
-## INFO 7 informational
-## DEBUG 8 debug-level messages
-## SPEW 9 Way too many details
-
-## Request this level of debugging output
-default DEFAULT_CONSOLE_LOGLEVEL=8
-## At a maximum only compile in this level of debugging
-default MAXIMUM_CONSOLE_LOGLEVEL=8
-
-##
-## Select power on after power fail setting
-default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
-
-### End Options.lb
-end
+++ /dev/null
-#define ASSEMBLY 1
-#include <stdint.h>
-#include <device/pci_def.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <arch/romcc_io.h>
-#include <cpu/x86/lapic.h>
-#include <arch/cpu.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
-#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
-#include "ram/ramtest.c"
-#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
-#include "northbridge/amd/amdk8/raminit.h"
-#include "cpu/amd/model_fxx/apic_timer.c"
-#include "lib/delay.c"
-#include "cpu/x86/lapic/boot_cpu.c"
-#include "northbridge/amd/amdk8/reset_test.c"
-#include "northbridge/amd/amdk8/debug.c"
-#include <cpu/amd/model_fxx_rev.h>
-#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
-#include "cpu/amd/mtrr/amd_earlymtrr.c"
-#include "cpu/x86/bist.h"
-
-
-#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-
-static void hard_reset(void)
-{
- set_bios_reset();
-
- /* enable cf9 */
- pci_write_config8(PCI_DEV(0, 0x04, 3), 0x41, 0xf1);
- /* reset */
- outb(0x0e, 0x0cf9);
-}
-
-static void soft_reset(void)
-{
- set_bios_reset();
- pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1);
-}
-
-/*
- * GPIO28 of 8111 will control H0_MEMRESET_L
- * GPIO29 of 8111 will control H1_MEMRESET_L
- */
-static void memreset_setup(void)
-{
- if (is_cpu_pre_c0()) {
- /* Set the memreset low */
- outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
- /* Ensure the BIOS has control of the memory lines */
- outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
- } else {
- /* Ensure the CPU has controll of the memory lines */
- outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29);
- }
-}
-
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
- if (is_cpu_pre_c0()) {
- udelay(800);
- /* Set memreset_high */
- outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
- udelay(90);
- }
-}
-
-static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes)
-{
- /* Routing Table Node i
- *
- * F0: 0x40, 0x44, 0x48, 0x4c, 0x50, 0x54, 0x58, 0x5c
- * i: 0, 1, 2, 3, 4, 5, 6, 7
- *
- * [ 0: 3] Request Route
- * [0] Route to this node
- * [1] Route to Link 0
- * [2] Route to Link 1
- * [3] Route to Link 2
- * [11: 8] Response Route
- * [0] Route to this node
- * [1] Route to Link 0
- * [2] Route to Link 1
- * [3] Route to Link 2
- * [19:16] Broadcast route
- * [0] Route to this node
- * [1] Route to Link 0
- * [2] Route to Link 1
- * [3] Route to Link 2
- */
-
- uint32_t ret=0x00010101; /* default row entry */
-
- static const unsigned int rows_2p[2][2] = {
- { 0x00050101, 0x00010404 },
- { 0x00010404, 0x00050101 }
- };
-
- if(maxnodes>2) {
- print_debug("this mainboard is only designed for 2 cpus\r\n");
- maxnodes=2;
- }
-
- if (!(node>=maxnodes || row>=maxnodes)) {
- ret=rows_2p[node][row];
- }
-
- return ret;
-}
-
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
- /* nothing to do */
-}
-
-static inline int spd_read_byte(unsigned device, unsigned address)
-{
- return smbus_read_byte(device, address);
-}
-
-#include "northbridge/amd/amdk8/raminit.c"
-#include "northbridge/amd/amdk8/coherent_ht.c"
-#include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "sdram/generic_sdram.c"
-#include "northbridge/amd/amdk8/resourcemap.c"
-#include "cpu/amd/dualcore/dualcore.c"
-
-#define FIRST_CPU 1
-#define SECOND_CPU 1
-#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
-static void main(unsigned long bist)
-{
- static const struct mem_controller cpu[] = {
-#if FIRST_CPU
- {
- .node_id = 0,
- .f0 = PCI_DEV(0, 0x18, 0),
- .f1 = PCI_DEV(0, 0x18, 1),
- .f2 = PCI_DEV(0, 0x18, 2),
- .f3 = PCI_DEV(0, 0x18, 3),
- .channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
- .channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
- },
-#endif
-#if SECOND_CPU
- {
- .node_id = 1,
- .f0 = PCI_DEV(0, 0x19, 0),
- .f1 = PCI_DEV(0, 0x19, 1),
- .f2 = PCI_DEV(0, 0x19, 2),
- .f3 = PCI_DEV(0, 0x19, 3),
- .channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
- .channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
- },
-#endif
- };
-
- int needs_reset;
- unsigned nodeid;
-
- if (bist == 0) {
- k8_init_and_stop_secondaries();
- }
- /* Setup the console */
- w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
- uart_init();
- console_init();
-
- /* Halt if there was a built in self test failure */
- report_bist_failure(bist);
-
- setup_default_resource_map();
- needs_reset = setup_coherent_ht_domain();
- needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80);
- if (needs_reset) {
- print_info("ht reset -\r\n");
- soft_reset();
- }
-
-#if 0
- print_pci_devices();
-#endif
-
- enable_smbus();
-
-#if 0
- dump_spd_registers(&cpu[0]);
-#endif
-
- memreset_setup();
- sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
-
-#if 0
- dump_pci_devices();
- dump_pci_device(PCI_DEV(0, 0x18, 2));
-#endif
-}
+++ /dev/null
-extern struct chip_operations mainboard_Iwill_DK8S2_ops;
-
-struct mainboard_Iwill_DK8S2_config {
- int nothing;
-};
+++ /dev/null
-entries
-
-#start-bit length config config-ID name
-#0 8 r 0 seconds
-#8 8 r 0 alarm_seconds
-#16 8 r 0 minutes
-#24 8 r 0 alarm_minutes
-#32 8 r 0 hours
-#40 8 r 0 alarm_hours
-#48 8 r 0 day_of_week
-#56 8 r 0 day_of_month
-#64 8 r 0 month
-#72 8 r 0 year
-#80 4 r 0 rate_select
-#84 3 r 0 REF_Clock
-#87 1 r 0 UIP
-#88 1 r 0 auto_switch_DST
-#89 1 r 0 24_hour_mode
-#90 1 r 0 binary_values_enable
-#91 1 r 0 square-wave_out_enable
-#92 1 r 0 update_finished_enable
-#93 1 r 0 alarm_interrupt_enable
-#94 1 r 0 periodic_interrupt_enable
-#95 1 r 0 disable_clock_updates
-#96 288 r 0 temporary_filler
-0 384 r 0 reserved_memory
-384 1 e 4 boot_option
-385 1 e 4 last_boot
-386 1 e 1 ECC_memory
-388 4 r 0 reboot_bits
-392 3 e 5 baud_rate
-395 1 e 1 hw_scrubber
-396 1 e 1 interleave_chip_selects
-397 2 e 8 max_mem_clock
-399 1 e 2 dual_core
-400 1 e 1 power_on_after_fail
-412 4 e 6 debug_level
-416 4 e 7 boot_first
-420 4 e 7 boot_second
-424 4 e 7 boot_third
-428 4 h 0 boot_index
-432 8 h 0 boot_countdown
-440 4 e 9 slow_cpu
-444 1 e 1 nmi
-445 1 e 1 iommu
-728 256 h 0 user_data
-984 16 h 0 check_sum
-# Reserve the extended AMD configuration registers
-1000 24 r 0 reserved_memory
-
-
-
-enumerations
-
-#ID value text
-1 0 Disable
-1 1 Enable
-2 0 Enable
-2 1 Disable
-4 0 Fallback
-4 1 Normal
-5 0 115200
-5 1 57600
-5 2 38400
-5 3 19200
-5 4 9600
-5 5 4800
-5 6 2400
-5 7 1200
-6 6 Notice
-6 7 Info
-6 8 Debug
-6 9 Spew
-7 0 Network
-7 1 HDD
-7 2 Floppy
-7 8 Fallback_Network
-7 9 Fallback_HDD
-7 10 Fallback_Floppy
-#7 3 ROM
-8 0 DDR400
-8 1 DDR333
-8 2 DDR266
-8 3 DDR200
-9 0 off
-9 1 87.5%
-9 2 75.0%
-9 3 62.5%
-9 4 50.0%
-9 5 37.5%
-9 6 25.0%
-9 7 12.5%
-
-checksums
-
-checksum 392 983 984
-
-
+++ /dev/null
-#define ASSEMBLY 1
-#include <stdint.h>
-#include <device/pci_def.h>
-#include <device/pci_ids.h>
-#include <arch/io.h>
-#include <arch/romcc_io.h>
-#include <cpu/x86/lapic.h>
-#include "pc80/mc146818rtc_early.c"
-#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
-#include "northbridge/amd/amdk8/early_ht.c"
-#include "cpu/x86/lapic/boot_cpu.c"
-#include "cpu/x86/mtrr/earlymtrr.c"
-#include "northbridge/amd/amdk8/reset_test.c"
-
-static unsigned long main(unsigned long bist)
-{
- unsigned nodeid;
-
- /* Make cerain my local apic is useable */
- enable_lapic();
-
- /* Is this a cpu only reset? */
- if (early_mtrr_init_detected()) {
- if (last_boot_normal()) {
- goto normal_image;
- } else {
- goto fallback_image;
- }
- }
- /* Is this a secondary cpu? */
- if (!boot_cpu()) {
- if (last_boot_normal()) {
- goto normal_image;
- } else {
- goto fallback_image;
- }
- }
-
-
- /* Nothing special needs to be done to find bus 0 */
- /* Allow the HT devices to be found */
- enumerate_ht_chain();
-
- /* Setup the 8111 */
- amd8111_enable_rom();
-
- /* Is this a deliberate reset by the bios */
- if (bios_reset_detected() && last_boot_normal()) {
- goto normal_image;
- }
- /* This is the primary cpu how should I boot? */
- else if (do_normal_boot()) {
- goto normal_image;
- }
- else {
- goto fallback_image;
- }
- normal_image:
- asm volatile ("jmp __normal_image"
- : /* outputs */
- : "a" (bist) /* inputs */
- : /* clobbers */
- );
- fallback_image:
- return bist;
-}
+++ /dev/null
-/* This file was generated by getpir.c, do not modify!
- (but if you do, please run checkpir on it to verify)
- * Contains the IRQ Routing Table dumped directly from your memory, which BIOS sets up
- *
- * Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM
-*/
-
-#include <arch/pirq_routing.h>
-
-const struct irq_routing_table intel_irq_routing_table = {
- PIRQ_SIGNATURE, /* u32 signature */
- PIRQ_VERSION, /* u16 version */
- 32+16*12, /* there can be total 12 devices on the bus */
- 0x00, /* Where the interrupt router lies (bus) */
- (0x07<<3)|0x3, /* Where the interrupt router lies (dev) */
- 0, /* IRQs devoted exclusively to PCI usage */
- 0x1022, /* Vendor */
- 0x746b, /* Device */
- 0, /* Crap (miniport) */
- { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
- 0x6d, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
- {
- /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
- {0x00,(0x07<<3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x04, 0x0def8}}, 0x0, 0x0},
- {0x03,(0x00<<3)|0x0, {{0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}, {0x04, 0x0def8}}, 0x0, 0x0},
- {0x02,(0x01<<3)|0x0, {{0x02, 0xdef8}, {0x03, 0xdef8}, {0x04, 0xdef8}, {0x01, 0x0def8}}, 0x1, 0x0},
- {0x02,(0x02<<3)|0x0, {{0x03, 0xdef8}, {0x04, 0xdef8}, {0x01, 0xdef8}, {0x02, 0x0def8}}, 0x2, 0x0},
- {0x01,(0x01<<3)|0x0, {{0x02, 0xdef8}, {0x03, 0xdef8}, {0x04, 0xdef8}, {0x01, 0x0def8}}, 0x3, 0x0},
- {0x01,(0x02<<3)|0x0, {{0x03, 0xdef8}, {0x04, 0xdef8}, {0x01, 0xdef8}, {0x02, 0x0def8}}, 0x4, 0x0},
- {0x03,(0x04<<3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x04, 0x0def8}}, 0x5, 0x0},
- {0x03,(0x05<<3)|0x0, {{0x02, 0xdef8}, {0x03, 0xdef8}, {0x04, 0xdef8}, {0x01, 0x0def8}}, 0x6, 0x0},
- {0x03,(0x06<<3)|0x0, {{0x03, 0xdef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
- {0x02,(0x03<<3)|0x0, {{0x04, 0xdef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
- {0x02,(0x04<<3)|0x0, {{0x01, 0xdef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
- {0x02,(0x05<<3)|0x0, {{0x02, 0xdef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
- }
-};
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
- return copy_pirq_routing_table(addr);
-}
+++ /dev/null
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <device/pci_ops.h>
-#include "chip.h"
-
-struct chip_operations mainboard_Iwill_DK8S2_ops = {
- CHIP_NAME("Iwill DK8S2 mainboard")
-};
-
+++ /dev/null
-#include <console/console.h>
-#include <arch/smp/mpspec.h>
-#include <device/pci.h>
-#include <string.h>
-#include <stdint.h>
-
-void *smp_write_config_table(void *v)
-{
- static const char sig[4] = "PCMP";
- static const char oem[8] = "IWILL ";
- static const char productid[12] = "DK8X ";
- struct mp_config_table *mc;
- unsigned char bus_num;
- unsigned char bus_isa;
- unsigned char bus_8131_1;
- unsigned char bus_8131_2;
- unsigned char bus_8111_1;
-
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
- memset(mc, 0, sizeof(*mc));
-
- memcpy(mc->mpc_signature, sig, sizeof(sig));
- mc->mpc_length = sizeof(*mc); /* initially just the header */
- mc->mpc_spec = 0x04;
- mc->mpc_checksum = 0; /* not yet computed */
- memcpy(mc->mpc_oem, oem, sizeof(oem));
- memcpy(mc->mpc_productid, productid, sizeof(productid));
- mc->mpc_oemptr = 0;
- mc->mpc_oemsize = 0;
- mc->mpc_entry_count = 0; /* No entries yet... */
- mc->mpc_lapic = LAPIC_ADDR;
- mc->mpe_length = 0;
- mc->mpe_checksum = 0;
- mc->reserved = 0;
-
- smp_write_processors(mc);
-
- {
- device_t dev;
-
- /* 8111 */
- dev = dev_find_slot(1, PCI_DEVFN(0x03,0));
- if (dev) {
- bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
- bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
- bus_isa++;
- }
- else {
- printk_debug("ERROR - could not find PCI 1:03.0, using defaults\n");
-
- bus_8111_1 = 4;
- bus_isa = 5;
- }
- /* 8131-1 */
- dev = dev_find_slot(1, PCI_DEVFN(0x01,0));
- if (dev) {
- bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
-
- }
- else {
- printk_debug("ERROR - could not find PCI 1:01.0, using defaults\n");
-
- bus_8131_1 = 2;
- }
- /* 8131-2 */
- dev = dev_find_slot(1, PCI_DEVFN(0x02,0));
- if (dev) {
- bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
-
- }
- else {
- printk_debug("ERROR - could not find PCI 1:02.0, using defaults\n");
-
- bus_8131_2 = 3;
- }
- }
-
- /* define bus and isa numbers */
- for(bus_num = 0; bus_num < bus_isa; bus_num++) {
- smp_write_bus(mc, bus_num, "PCI ");
- }
- smp_write_bus(mc, bus_isa, "ISA ");
-
- /* IOAPIC handling */
- smp_write_ioapic(mc, 2, 0x11, 0xfec00000);
- {
- device_t dev;
- struct resource *res;
- /* 8131 apic 3 */
- dev = dev_find_slot(1, PCI_DEVFN(0x01,1));
- if (dev) {
- res = find_resource(dev, PCI_BASE_ADDRESS_0);
- if (res) {
- smp_write_ioapic(mc, 0x03, 0x11, res->base);
- }
- }
- /* 8131 apic 4 */
- dev = dev_find_slot(1, PCI_DEVFN(0x02,1));
- if (dev) {
- res = find_resource(dev, PCI_BASE_ADDRESS_0);
- if (res) {
- smp_write_ioapic(mc, 0x04, 0x11, res->base);
- }
- }
- }
-
- /* ISA backward compatibility interrupts */
- smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_isa, 0x00, 0x02, 0x00);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_isa, 0x01, 0x02, 0x01);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_isa, 0x00, 0x02, 0x02);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_isa, 0x03, 0x02, 0x03);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_isa, 0x04, 0x02, 0x04);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_isa, 0x05, 0x02, 0x05);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_isa, 0x06, 0x02, 0x06);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_isa, 0x07, 0x02, 0x07);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_isa, 0x08, 0x02, 0x08);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_isa, 0x09, 0x02, 0x09);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_isa, 0x0a, 0x02, 0x0a);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_isa, 0x0b, 0x02, 0x0b);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_isa, 0x0c, 0x02, 0x0c);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_isa, 0x0d, 0x02, 0x0d);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_isa, 0x0e, 0x02, 0x0e);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_isa, 0x0f, 0x02, 0x0f);
-
- /* Standard local interrupt assignments */
- smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_isa, 0x00, MP_APIC_ALL, 0x00);
- smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_isa, 0x00, MP_APIC_ALL, 0x01);
-
-
- /* PCI Slot 1 */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8131_2, (1<<2)|0, 0x02, 0x11);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8131_2, (1<<2)|1, 0x02, 0x12);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8131_2, (1<<2)|2, 0x02, 0x13);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8131_2, (1<<2)|3, 0x02, 0x10);
-
- /* PCI Slot 2 */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8131_2, (2<<2)|0, 0x02, 0x12);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8131_2, (2<<2)|1, 0x02, 0x13);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8131_2, (2<<2)|2, 0x02, 0x10);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8131_2, (2<<2)|3, 0x02, 0x11);
-
- /* PCI Slot 3 */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8131_1, (1<<2)|0, 0x02, 0x11);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8131_1, (1<<2)|1, 0x02, 0x12);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8131_1, (1<<2)|2, 0x02, 0x13);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8131_1, (1<<2)|3, 0x02, 0x10);
-
- /* PCI Slot 4 */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8131_1, (2<<2)|0, 0x02, 0x12);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8131_1, (2<<2)|1, 0x02, 0x13);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8131_1, (2<<2)|2, 0x02, 0x10);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8131_1, (2<<2)|3, 0x02, 0x11);
-
- /* PCI Slot 5 */
-#warning "FIXME get the irqs right, it's just hacked to work for now"
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8111_1, (5<<2)|0, 0x02, 0x11);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8111_1, (5<<2)|1, 0x02, 0x12);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8111_1, (5<<2)|2, 0x02, 0x13);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8111_1, (5<<2)|3, 0x02, 0x10);
-
- /* PCI Slot 6 */
-#warning "FIXME get the irqs right, it's just hacked to work for now"
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8111_1, (4<<2)|0, 0x02, 0x10);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8111_1, (4<<2)|1, 0x02, 0x11);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8111_1, (4<<2)|2, 0x02, 0x12);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8111_1, (4<<2)|3, 0x02, 0x13);
-
- /* On board nics */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8131_1, (3<<2)|0, 0x02, 0x13);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8131_1, (4<<2)|0, 0x02, 0x13);
-
- /* There is no extension information... */
-
- /* Compute the checksums */
- mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
- mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
- printk_debug("Wrote the mp table end at: %p - %p\n",
- mc, smp_next_mpe_entry(mc));
- return smp_next_mpe_entry(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr);
- return (unsigned long)smp_write_config_table(v);
-}
-
+++ /dev/null
-#include "../../../southbridge/amd/amd8111/amd8111_reset.c"
-
-void hard_reset(void)
-{
- amd8111_hard_reset(0, 0);
-}
+++ /dev/null
-##
-## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
-##
-if USE_FALLBACK_IMAGE
- default ROM_SECTION_SIZE = FALLBACK_SIZE
- default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
-else
- default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
- default ROM_SECTION_OFFSET = 0
-end
-
-##
-## Compute the start location and size size of
-## The linuxBIOS bootloader.
-##
-default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
-default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
-
-##
-## Compute where this copy of linuxBIOS will start in the boot rom
-##
-default _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
-
-##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
-## execution speed.
-##
-## XIP_ROM_SIZE must be a power of 2.
-## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
-##
-default XIP_ROM_SIZE=65536
-default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
-
-##
-## Set all of the defaults for an x86 architecture
-##
-
-arch i386 end
-
-##
-## Build the objects we have code for in this directory.
-##
-
-driver mainboard.o
-if HAVE_MP_TABLE object mptable.o end
-if HAVE_PIRQ_TABLE object irq_tables.o end
-#object reset.o
-
-##
-## Romcc output
-##
-makerule ./failover.E
- depends "$(MAINBOARD)/failover.c ./romcc"
- action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
-end
-
-makerule ./failover.inc
- depends "$(MAINBOARD)/failover.c ./romcc"
- action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
-end
-
-makerule ./auto.E
- depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
- action "./romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
-end
-makerule ./auto.inc
- depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
- action "./romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
-end
-
-##
-## Build our 16 bit and 32 bit linuxBIOS entry code
-##
-mainboardinit cpu/x86/16bit/entry16.inc
-mainboardinit cpu/x86/32bit/entry32.inc
-ldscript /cpu/x86/16bit/entry16.lds
-ldscript /cpu/x86/32bit/entry32.lds
-
-##
-## Build our reset vector (This is where linuxBIOS is entered)
-##
-if USE_FALLBACK_IMAGE
- mainboardinit cpu/x86/16bit/reset16.inc
- ldscript /cpu/x86/16bit/reset16.lds
-else
- mainboardinit cpu/x86/32bit/reset32.inc
- ldscript /cpu/x86/32bit/reset32.lds
-end
-
-### Should this be in the northbridge code?
-mainboardinit arch/i386/lib/cpu_reset.inc
-
-##
-## Include an id string (For safe flashing)
-##
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-
-###
-### This is the early phase of linuxBIOS startup
-### Things are delicate and we test to see if we should
-### failover to another image.
-###
-if USE_FALLBACK_IMAGE
- ldscript /arch/i386/lib/failover.lds
- mainboardinit ./failover.inc
-end
-
-###
-### O.k. We aren't just an intermediary anymore!
-###
-
-##
-## Setup RAM
-##
-mainboardinit cpu/x86/fpu/enable_fpu.inc
-mainboardinit cpu/x86/mmx/enable_mmx.inc
-mainboardinit cpu/x86/sse/enable_sse.inc
-mainboardinit ./auto.inc
-mainboardinit cpu/x86/sse/disable_sse.inc
-mainboardinit cpu/x86/mmx/disable_mmx.inc
-
-##
-## Include the secondary Configuration files
-##
-dir /pc80
-config chip.h
-
-chip northbridge/amd/amdk8/root_complex
- device pci_domain 0 on
- chip northbridge/amd/amdk8
- device pci 18.0 on # northbridge
- # devices on link 0, link 0 == LDT 0
- chip southbridge/amd/amd8131
- # the on/off keyword is mandatory
- device pci 0.0 on end
- device pci 0.1 on end
- device pci 1.0 on end
- device pci 1.1 on end
- end
- chip southbridge/amd/amd8111
- # this "device pci 0.0" is the parent the next one
- # PCI bridge
- device pci 0.0 on
- device pci 0.0 on end
- device pci 0.1 on end
- device pci 0.2 on end
- device pci 1.0 off end
- end
- device pci 1.0 on
- chip superio/winbond/w83627thf
- device pnp 2e.0 on end
- device pnp 2e.1 on end
- device pnp 2e.2 on end
- device pnp 2e.3 on end
- device pnp 2e.4 on end
- device pnp 2e.5 on end
- device pnp 2e.6 on end
- device pnp 2e.7 on end
- device pnp 2e.8 on end
- device pnp 2e.9 on end
- device pnp 2e.a on end
- end
- end
- device pci 1.1 on end
- device pci 1.2 on end
- device pci 1.3 on end
- device pci 1.5 off end
- device pci 1.6 off end
- end
- end # LDT0
- device pci 18.0 on end # LDT1
- device pci 18.0 on end # LDT2
- device pci 18.1 on end
- device pci 18.2 on end
- device pci 18.3 on end
- end
- chip northbridge/amd/amdk8
- device pci 19.0 on end
- device pci 19.0 on end
- device pci 19.0 on end
- device pci 19.1 on end
- device pci 19.2 on end
- device pci 19.3 on end
- end
- end
- device apic_cluster 0 on
- chip cpu/amd/socket_940
- device apic 0 on end
- end
- chip cpu/amd/socket_940
- device apic 1 on end
- end
- end
-end
-
+++ /dev/null
-uses HAVE_MP_TABLE
-uses HAVE_PIRQ_TABLE
-uses USE_FALLBACK_IMAGE
-uses HAVE_FALLBACK_BOOT
-uses HAVE_HARD_RESET
-uses IRQ_SLOT_COUNT
-uses HAVE_OPTION_TABLE
-uses CONFIG_MAX_CPUS
-uses CONFIG_MAX_PHYSICAL_CPUS
-uses CONFIG_IOAPIC
-uses CONFIG_SMP
-uses FALLBACK_SIZE
-uses ROM_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_IMAGE_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_SECTION_OFFSET
-uses CONFIG_ROM_STREAM
-uses CONFIG_ROM_STREAM_START
-uses PAYLOAD_SIZE
-uses _ROMBASE
-uses XIP_ROM_SIZE
-uses XIP_ROM_BASE
-uses STACK_SIZE
-uses HEAP_SIZE
-uses USE_OPTION_TABLE
-uses LB_CKS_RANGE_START
-uses LB_CKS_RANGE_END
-uses LB_CKS_LOC
-uses MAINBOARD
-uses MAINBOARD_PART_NUMBER
-uses MAINBOARD_VENDOR
-uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses LINUXBIOS_EXTRA_VERSION
-uses _RAMBASE
-uses TTYS0_BAUD
-uses TTYS0_BASE
-uses TTYS0_LCS
-uses DEFAULT_CONSOLE_LOGLEVEL
-uses MAXIMUM_CONSOLE_LOGLEVEL
-uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-uses CONFIG_CONSOLE_SERIAL8250
-uses HAVE_INIT_TIMER
-uses CONFIG_GDB_STUB
-uses CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses OBJCOPY
-
-uses CONFIG_USE_INIT
-
-## ROM_SIZE is the size of boot ROM that this board will use.
-default ROM_SIZE=524288
-
-###
-### Build options
-###
-
-##
-## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
-##
-default FALLBACK_SIZE=131072
-
-##
-## Build code for the fallback boot
-##
-default HAVE_FALLBACK_BOOT=1
-
-##
-## Build code to reset the motherboard from linuxBIOS
-##
-default HAVE_HARD_RESET=1
-
-##
-## Build code to export a programmable irq routing table
-##
-default HAVE_PIRQ_TABLE=1
-default IRQ_SLOT_COUNT=9
-
-##
-## Build code to export an x86 MP table
-## Useful for specifying IRQ routing values
-##
-default HAVE_MP_TABLE=1
-
-##
-## Build code to export a CMOS option table
-##
-default HAVE_OPTION_TABLE=1
-
-##
-## Move the default LinuxBIOS cmos range off of AMD RTC registers
-##
-default LB_CKS_RANGE_START=49
-default LB_CKS_RANGE_END=122
-default LB_CKS_LOC=123
-
-##
-## Build code for SMP support
-## Only worry about 2 micro processors
-##
-default CONFIG_SMP=1
-default CONFIG_MAX_CPUS=2
-default CONFIG_MAX_PHYSICAL_CPUS=2
-
-##
-## Build code to setup a generic IOAPIC
-##
-default CONFIG_IOAPIC=1
-
-##
-## Clean up the motherboard id strings
-##
-#default MAINBOARD_PART_NUMBER="HDAMA"
-#default MAINBOARD_VENDOR="ARIMA"
-#default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x161f
-#default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3016
-
-###
-### LinuxBIOS layout values
-###
-
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
-default ROM_IMAGE_SIZE = 65536
-
-##
-## Use a small 8K stack
-##
-default STACK_SIZE=0x2000
-
-##
-## Use a small 16K heap
-##
-default HEAP_SIZE=0x4000
-
-##
-## Only use the option table in a normal image
-##
-default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
-
-##
-## LinuxBIOS C code runs at this location in RAM
-##
-default _RAMBASE=0x00004000
-
-##
-## Load the payload from the ROM
-##
-default CONFIG_ROM_STREAM = 1
-
-###
-### Defaults of options that you may want to override in the target config file
-###
-
-##
-## The default compiler
-##
-#default CC="$(CROSS_COMPILE)gcc -m32"
-#default HOSTCC="gcc"
-
-##
-## Disable the gdb stub by default
-##
-default CONFIG_GDB_STUB=0
-
-##
-## The Serial Console
-##
-
-# To Enable the Serial Console
-default CONFIG_CONSOLE_SERIAL8250=1
-
-## Select the serial console baud rate
-default TTYS0_BAUD=115200
-#default TTYS0_BAUD=57600
-#default TTYS0_BAUD=38400
-#default TTYS0_BAUD=19200
-#default TTYS0_BAUD=9600
-#default TTYS0_BAUD=4800
-#default TTYS0_BAUD=2400
-#default TTYS0_BAUD=1200
-
-# Select the serial console base port
-default TTYS0_BASE=0x3f8
-
-# Select the serial protocol
-# This defaults to 8 data bits, 1 stop bit, and no parity
-default TTYS0_LCS=0x3
-
-##
-### Select the linuxBIOS loglevel
-##
-## EMERG 1 system is unusable
-## ALERT 2 action must be taken immediately
-## CRIT 3 critical conditions
-## ERR 4 error conditions
-## WARNING 5 warning conditions
-## NOTICE 6 normal but significant condition
-## INFO 7 informational
-## DEBUG 8 debug-level messages
-## SPEW 9 Way too many details
-
-## Request this level of debugging output
-default DEFAULT_CONSOLE_LOGLEVEL=8
-## At a maximum only compile in this level of debugging
-default MAXIMUM_CONSOLE_LOGLEVEL=8
-
-##
-## Select power on after power fail setting
-default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
-
-### End Options.lb
-end
+++ /dev/null
-#define ASSEMBLY 1
-#include <stdint.h>
-#include <device/pci_def.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <arch/romcc_io.h>
-#include <cpu/x86/lapic.h>
-#include <arch/cpu.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
-#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
-#include "ram/ramtest.c"
-#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
-#include "northbridge/amd/amdk8/raminit.h"
-#include "cpu/amd/model_fxx/apic_timer.c"
-#include "lib/delay.c"
-#include "cpu/x86/lapic/boot_cpu.c"
-#include "northbridge/amd/amdk8/reset_test.c"
-#include "northbridge/amd/amdk8/debug.c"
-#include <cpu/amd/model_fxx_rev.h>
-
-#include "superio/NSC/pc87360/pc87360_early_serial.c"
-#include "cpu/amd/mtrr/amd_earlymtrr.c"
-#include "cpu/x86/bist.h"
-
-#define SERIAL_DEV PNP_DEV(0x2e, PC87360_SP1)
-
-static void hard_reset(void)
-{
- set_bios_reset();
-
- /* enable cf9 */
- pci_write_config8(PCI_DEV(0, 0x04, 3), 0x41, 0xf1);
- /* reset */
- outb(0x0e, 0x0cf9);
-}
-
-static void soft_reset(void)
-{
- set_bios_reset();
- pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1);
-}
-
-/*
- * GPIO28 of 8111 will control H0_MEMRESET_L
- * GPIO29 of 8111 will control H1_MEMRESET_L
- */
-static void memreset_setup(void)
-{
- if (is_cpu_pre_c0()) {
- /* Set the memreset low */
- outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
- /* Ensure the BIOS has control of the memory lines */
- outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
- }
- else {
- /* Ensure the CPU has controll of the memory lines */
- outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29);
- }
-}
-
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
- if (is_cpu_pre_c0()) {
- udelay(800);
- /* Set memreset_high */
- outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
- udelay(90);
- }
-}
-
-static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes)
-{
- /* Routing Table Node i
- *
- * F0: 0x40, 0x44, 0x48, 0x4c, 0x50, 0x54, 0x58, 0x5c
- * i: 0, 1, 2, 3, 4, 5, 6, 7
- *
- * [ 0: 3] Request Route
- * [0] Route to this node
- * [1] Route to Link 0
- * [2] Route to Link 1
- * [3] Route to Link 2
- * [11: 8] Response Route
- * [0] Route to this node
- * [1] Route to Link 0
- * [2] Route to Link 1
- * [3] Route to Link 2
- * [19:16] Broadcast route
- * [0] Route to this node
- * [1] Route to Link 0
- * [2] Route to Link 1
- * [3] Route to Link 2
- */
-
- uint32_t ret=0x00010101; /* default row entry */
-
- static const unsigned int rows_2p[2][2] = {
- { 0x00050101, 0x00010404 },
- { 0x00010404, 0x00050101 }
- };
-
- if(maxnodes>2) {
- print_debug("this mainboard is only designed for 2 cpus\r\n");
- maxnodes=2;
- }
-
-
- if (!(node>=maxnodes || row>=maxnodes)) {
- ret=rows_2p[node][row];
- }
-
- return ret;
-}
-
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
- /* nothing to do */
-}
-
-static inline int spd_read_byte(unsigned device, unsigned address)
-{
- return smbus_read_byte(device, address);
-}
-
-#include "northbridge/amd/amdk8/raminit.c"
-#include "northbridge/amd/amdk8/coherent_ht.c"
-#include "northbridge/amd/amdk8/incoherent_ht.c"
-#include "sdram/generic_sdram.c"
-#include "northbridge/amd/amdk8/resourcemap.c"
-#include "cpu/amd/dualcore/dualcore.c"
-
-#define FIRST_CPU 1
-#define SECOND_CPU 1
-#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
-static void main(unsigned long bist)
-{
- static const struct mem_controller cpu[] = {
-#if FIRST_CPU
- {
- .node_id = 0,
- .f0 = PCI_DEV(0, 0x18, 0),
- .f1 = PCI_DEV(0, 0x18, 1),
- .f2 = PCI_DEV(0, 0x18, 2),
- .f3 = PCI_DEV(0, 0x18, 3),
- .channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
- .channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
- },
-#endif
-#if SECOND_CPU
- {
- .node_id = 1,
- .f0 = PCI_DEV(0, 0x19, 0),
- .f1 = PCI_DEV(0, 0x19, 1),
- .f2 = PCI_DEV(0, 0x19, 2),
- .f3 = PCI_DEV(0, 0x19, 3),
- .channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
- .channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
- },
-#endif
- };
-
- int needs_reset;
- unsigned nodeid;
-
- if (bist == 0) {
- k8_init_and_stop_secondaries();
- }
- /* Setup the console */
- pc87360_enable_serial(SERIAL_DEV, TTYS0_BASE);
- uart_init();
- console_init();
-
- /* Halt if there was a built in self test failure */
- report_bist_failure(bist);
-
- setup_default_resource_map();
- needs_reset = setup_coherent_ht_domain();
- needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80);
- if (needs_reset) {
- print_info("ht reset -\r\n");
- soft_reset();
- }
-
-#if 0
- print_pci_devices();
-#endif
- enable_smbus();
-#if 0
- dump_spd_registers(&cpu[0]);
-#endif
-
- memreset_setup();
- sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
-
-#if 1
- dump_pci_devices();
-#endif
-#if 0
- dump_pci_device(PCI_DEV(0, 0x18, 2));
-#endif
-
- /* Check all of memory */
-#if 0
- msr_t msr;
- msr = rdmsr(TOP_MEM);
- print_debug("TOP_MEM: ");
- print_debug_hex32(msr.hi);
- print_debug_hex32(msr.lo);
- print_debug("\r\n");
-#endif
-#if 0
- ram_check(0x00000000, msr.lo);
-#endif
-#if 0
- static const struct {
- unsigned long lo, hi;
- } check_addrs[] = {
- /* Check 16MB of memory @ 0*/
- { 0x00000000, 0x01000000 },
-#if TOTAL_CPUS > 1
- /* Check 16MB of memory @ 2GB */
- { 0x80000000, 0x81000000 },
-#endif
- };
- int i;
- for(i = 0; i < sizeof(check_addrs)/sizeof(check_addrs[0]); i++) {
- ram_check(check_addrs[i].lo, check_addrs[i].hi);
- }
-#endif
-}
+++ /dev/null
-extern struct chip_operations mainboard_Iwill_DK8X_ops;
-
-struct mainboard_Iwill_DK8X_config {
- int nothing;
-};
+++ /dev/null
-entries
-
-#start-bit length config config-ID name
-#0 8 r 0 seconds
-#8 8 r 0 alarm_seconds
-#16 8 r 0 minutes
-#24 8 r 0 alarm_minutes
-#32 8 r 0 hours
-#40 8 r 0 alarm_hours
-#48 8 r 0 day_of_week
-#56 8 r 0 day_of_month
-#64 8 r 0 month
-#72 8 r 0 year
-#80 4 r 0 rate_select
-#84 3 r 0 REF_Clock
-#87 1 r 0 UIP
-#88 1 r 0 auto_switch_DST
-#89 1 r 0 24_hour_mode
-#90 1 r 0 binary_values_enable
-#91 1 r 0 square-wave_out_enable
-#92 1 r 0 update_finished_enable
-#93 1 r 0 alarm_interrupt_enable
-#94 1 r 0 periodic_interrupt_enable
-#95 1 r 0 disable_clock_updates
-#96 288 r 0 temporary_filler
-0 384 r 0 reserved_memory
-384 1 e 4 boot_option
-385 1 e 4 last_boot
-386 1 e 1 ECC_memory
-388 4 r 0 reboot_bits
-392 3 e 5 baud_rate
-395 1 e 1 hw_scrubber
-396 1 e 1 interleave_chip_selects
-397 2 e 8 max_mem_clock
-399 1 e 2 dual_core
-400 1 e 1 power_on_after_fail
-412 4 e 6 debug_level
-416 4 e 7 boot_first
-420 4 e 7 boot_second
-424 4 e 7 boot_third
-428 4 h 0 boot_index
-432 8 h 0 boot_countdown
-440 4 e 9 slow_cpu
-444 1 e 1 nmi
-445 1 e 1 iommu
-728 256 h 0 user_data
-984 16 h 0 check_sum
-# Reserve the extended AMD configuration registers
-1000 24 r 0 reserved_memory
-
-
-
-enumerations
-
-#ID value text
-1 0 Disable
-1 1 Enable
-2 0 Enable
-2 1 Disable
-4 0 Fallback
-4 1 Normal
-5 0 115200
-5 1 57600
-5 2 38400
-5 3 19200
-5 4 9600
-5 5 4800
-5 6 2400
-5 7 1200
-6 6 Notice
-6 7 Info
-6 8 Debug
-6 9 Spew
-7 0 Network
-7 1 HDD
-7 2 Floppy
-7 8 Fallback_Network
-7 9 Fallback_HDD
-7 10 Fallback_Floppy
-#7 3 ROM
-8 0 DDR400
-8 1 DDR333
-8 2 DDR266
-8 3 DDR200
-9 0 off
-9 1 87.5%
-9 2 75.0%
-9 3 62.5%
-9 4 50.0%
-9 5 37.5%
-9 6 25.0%
-9 7 12.5%
-
-checksums
-
-checksum 392 983 984
-
-
+++ /dev/null
-#define ASSEMBLY 1
-#include <stdint.h>
-#include <device/pci_def.h>
-#include <device/pci_ids.h>
-#include <arch/io.h>
-#include <arch/romcc_io.h>
-#include <cpu/x86/lapic.h>
-#include "pc80/mc146818rtc_early.c"
-#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
-#include "northbridge/amd/amdk8/early_ht.c"
-#include "cpu/x86/lapic/boot_cpu.c"
-#include "cpu/x86/mtrr/earlymtrr.c"
-#include "northbridge/amd/amdk8/reset_test.c"
-
-static unsigned long main(unsigned long bist)
-{
- unsigned nodeid;
-
- /* Make cerain my local apic is useable */
- enable_lapic();
-
- /* Is this a cpu only reset? */
- if (early_mtrr_init_detected()) {
- if (last_boot_normal()) {
- goto normal_image;
- } else {
- goto fallback_image;
- }
- }
- /* Is this a secondary cpu? */
- if (!boot_cpu()) {
- if (last_boot_normal()) {
- goto normal_image;
- } else {
- goto fallback_image;
- }
- }
-
-
- /* Nothing special needs to be done to find bus 0 */
- /* Allow the HT devices to be found */
- enumerate_ht_chain();
-
- /* Setup the 8111 */
- amd8111_enable_rom();
-
- /* Is this a deliberate reset by the bios */
- if (bios_reset_detected() && last_boot_normal()) {
- goto normal_image;
- }
- /* This is the primary cpu how should I boot? */
- else if (do_normal_boot()) {
- goto normal_image;
- }
- else {
- goto fallback_image;
- }
- normal_image:
- asm volatile ("jmp __normal_image"
- : /* outputs */
- : "a" (bist) /* inputs */
- : /* clobbers */
- );
- fallback_image:
- return bist;
-}
+++ /dev/null
-#include <arch/pirq_routing.h>
-#include <device/pci.h>
-
-#define IRQ_ROUTER_BUS 1
-#define IRQ_ROUTER_DEVFN PCI_DEVFN(4,3)
-#define IRQ_ROUTER_VENDOR 0x1022
-#define IRQ_ROUTER_DEVICE 0x746b
-
-#define AVAILABLE_IRQS 0xdef8
-#define IRQ_SLOT(slot, bus, dev, fn, linka, linkb, linkc, linkd) \
- { bus, (dev<<3)|fn, {{ linka, AVAILABLE_IRQS}, { linkb, AVAILABLE_IRQS}, \
- {linkc, AVAILABLE_IRQS}, {linkd, AVAILABLE_IRQS}}, slot, 0}
-
-/* Each IRQ_SLOT entry consists of:
- * bus, devfn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu
- */
-
-const struct irq_routing_table intel_irq_routing_table = {
- PIRQ_SIGNATURE, /* u32 signature */
- PIRQ_VERSION, /* u16 version */
- 32+16*IRQ_SLOT_COUNT, /* there can be total IRQ_SLOT_COUNT
- * devices on the bus */
- IRQ_ROUTER_BUS, /* Where the interrupt router lies (bus) */
- IRQ_ROUTER_DEVFN, /* Where the interrupt router lies (dev) */
- 0x00, /* IRQs devoted exclusively to PCI usage */
- IRQ_ROUTER_VENDOR, /* Vendor */
- IRQ_ROUTER_DEVICE, /* Device */
- 0x00, /* Crap (miniport) */
- { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
- 0x00, /* u8 checksum , mod 256 checksum must give
- * zero, will be corrected later
- */
- {
-
- /* slot(0=onboard), devfn, irqlinks (line id, 0=not routed) */
-
- /* PCI Slot 1-6 */
- IRQ_SLOT (1, 3,1,0, 2,3,4,1 ),
- IRQ_SLOT (2, 3,2,0, 3,4,1,2 ),
- IRQ_SLOT (3, 2,1,0, 2,3,4,1 ),
- IRQ_SLOT (4, 2,2,0, 3,4,1,2 ),
- IRQ_SLOT (5, 4,5,0, 2,3,4,1 ),
- IRQ_SLOT (6, 4,4,0, 1,2,3,4 ),
-
- /* Onboard NICs */
- IRQ_SLOT (0, 2,3,0, 4,0,0,0 ),
- IRQ_SLOT (0, 2,4,0, 4,0,0,0 ),
-
- /* Let Linux know about bus 1 */
- IRQ_SLOT (0, 1,4,3, 0,0,0,0 ),
- }
-};
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
- return copy_pirq_routing_table(addr);
-}
+++ /dev/null
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <device/pci_ops.h>
-#include "chip.h"
-
-struct chip_operations mainboard_Iwill_DK8X_ops = {
- CHIP_NAME("Iwill DK8X mainboard")
-};
-
+++ /dev/null
-#include <console/console.h>
-#include <arch/smp/mpspec.h>
-#include <device/pci.h>
-#include <string.h>
-#include <stdint.h>
-
-void *smp_write_config_table(void *v)
-{
- static const char sig[4] = "PCMP";
- static const char oem[8] = "IWILL ";
- static const char productid[12] = "DK8X ";
- struct mp_config_table *mc;
- unsigned char bus_num;
- unsigned char bus_isa;
- unsigned char bus_8131_1;
- unsigned char bus_8131_2;
- unsigned char bus_8111_1;
-
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
- memset(mc, 0, sizeof(*mc));
-
- memcpy(mc->mpc_signature, sig, sizeof(sig));
- mc->mpc_length = sizeof(*mc); /* initially just the header */
- mc->mpc_spec = 0x04;
- mc->mpc_checksum = 0; /* not yet computed */
- memcpy(mc->mpc_oem, oem, sizeof(oem));
- memcpy(mc->mpc_productid, productid, sizeof(productid));
- mc->mpc_oemptr = 0;
- mc->mpc_oemsize = 0;
- mc->mpc_entry_count = 0; /* No entries yet... */
- mc->mpc_lapic = LAPIC_ADDR;
- mc->mpe_length = 0;
- mc->mpe_checksum = 0;
- mc->reserved = 0;
-
- smp_write_processors(mc);
-
- {
- device_t dev;
-
- /* 8111 */
- dev = dev_find_slot(1, PCI_DEVFN(0x03,0));
- if (dev) {
- bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
- bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
- bus_isa++;
- }
- else {
- printk_debug("ERROR - could not find PCI 1:03.0, using defaults\n");
-
- bus_8111_1 = 4;
- bus_isa = 5;
- }
- /* 8131-1 */
- dev = dev_find_slot(1, PCI_DEVFN(0x01,0));
- if (dev) {
- bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
-
- }
- else {
- printk_debug("ERROR - could not find PCI 1:01.0, using defaults\n");
-
- bus_8131_1 = 2;
- }
- /* 8131-2 */
- dev = dev_find_slot(1, PCI_DEVFN(0x02,0));
- if (dev) {
- bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
-
- }
- else {
- printk_debug("ERROR - could not find PCI 1:02.0, using defaults\n");
-
- bus_8131_2 = 3;
- }
- }
-
- /* define bus and isa numbers */
- for(bus_num = 0; bus_num < bus_isa; bus_num++) {
- smp_write_bus(mc, bus_num, "PCI ");
- }
- smp_write_bus(mc, bus_isa, "ISA ");
-
- /* IOAPIC handling */
- smp_write_ioapic(mc, 2, 0x11, 0xfec00000);
- {
- device_t dev;
- struct resource *res;
- /* 8131 apic 3 */
- dev = dev_find_slot(1, PCI_DEVFN(0x01,1));
- if (dev) {
- res = find_resource(dev, PCI_BASE_ADDRESS_0);
- if (res) {
- smp_write_ioapic(mc, 0x03, 0x11, res->base);
- }
- }
- /* 8131 apic 4 */
- dev = dev_find_slot(1, PCI_DEVFN(0x02,1));
- if (dev) {
- res = find_resource(dev, PCI_BASE_ADDRESS_0);
- if (res) {
- smp_write_ioapic(mc, 0x04, 0x11, res->base);
- }
- }
- }
-
- /* ISA backward compatibility interrupts */
- smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_isa, 0x00, 0x02, 0x00);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_isa, 0x01, 0x02, 0x01);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_isa, 0x00, 0x02, 0x02);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_isa, 0x03, 0x02, 0x03);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_isa, 0x04, 0x02, 0x04);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_isa, 0x05, 0x02, 0x05);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_isa, 0x06, 0x02, 0x06);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_isa, 0x07, 0x02, 0x07);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_isa, 0x08, 0x02, 0x08);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_isa, 0x09, 0x02, 0x09);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_isa, 0x0a, 0x02, 0x0a);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_isa, 0x0b, 0x02, 0x0b);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_isa, 0x0c, 0x02, 0x0c);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_isa, 0x0d, 0x02, 0x0d);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_isa, 0x0e, 0x02, 0x0e);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_isa, 0x0f, 0x02, 0x0f);
-
- /* Standard local interrupt assignments */
- smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_isa, 0x00, MP_APIC_ALL, 0x00);
- smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_isa, 0x00, MP_APIC_ALL, 0x01);
-
-
- /* PCI Slot 1 */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8131_2, (1<<2)|0, 0x02, 0x11);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8131_2, (1<<2)|1, 0x02, 0x12);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8131_2, (1<<2)|2, 0x02, 0x13);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8131_2, (1<<2)|3, 0x02, 0x10);
-
- /* PCI Slot 2 */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8131_2, (2<<2)|0, 0x02, 0x12);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8131_2, (2<<2)|1, 0x02, 0x13);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8131_2, (2<<2)|2, 0x02, 0x10);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8131_2, (2<<2)|3, 0x02, 0x11);
-
- /* PCI Slot 3 */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8131_1, (1<<2)|0, 0x02, 0x11);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8131_1, (1<<2)|1, 0x02, 0x12);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8131_1, (1<<2)|2, 0x02, 0x13);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8131_1, (1<<2)|3, 0x02, 0x10);
-
- /* PCI Slot 4 */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8131_1, (2<<2)|0, 0x02, 0x12);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8131_1, (2<<2)|1, 0x02, 0x13);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8131_1, (2<<2)|2, 0x02, 0x10);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8131_1, (2<<2)|3, 0x02, 0x11);
-
- /* PCI Slot 5 */
-#warning "FIXME get the irqs right, it's just hacked to work for now"
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8111_1, (5<<2)|0, 0x02, 0x11);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8111_1, (5<<2)|1, 0x02, 0x12);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8111_1, (5<<2)|2, 0x02, 0x13);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8111_1, (5<<2)|3, 0x02, 0x10);
-
- /* PCI Slot 6 */
-#warning "FIXME get the irqs right, it's just hacked to work for now"
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8111_1, (4<<2)|0, 0x02, 0x10);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8111_1, (4<<2)|1, 0x02, 0x11);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8111_1, (4<<2)|2, 0x02, 0x12);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8111_1, (4<<2)|3, 0x02, 0x13);
-
- /* On board nics */
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8131_1, (3<<2)|0, 0x02, 0x13);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
- bus_8131_1, (4<<2)|0, 0x02, 0x13);
-
- /* There is no extension information... */
-
- /* Compute the checksums */
- mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
- mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
- printk_debug("Wrote the mp table end at: %p - %p\n",
- mc, smp_next_mpe_entry(mc));
- return smp_next_mpe_entry(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr);
- return (unsigned long)smp_write_config_table(v);
-}
-
+++ /dev/null
-#include "../../../southbridge/amd/amd8111/amd8111_reset.c"
-
-void hard_reset(void)
-{
- amd8111_hard_reset(0, 0);
-}
+++ /dev/null
-##
-## Compute the location and size of where this firmware image
-## (linuxBIOS plus bootloader) will live in the boot rom chip.
-##
-if USE_FAILOVER_IMAGE
- default ROM_SECTION_SIZE = FAILOVER_SIZE
- default ROM_SECTION_OFFSET = ( ROM_SIZE - FAILOVER_SIZE )
-else
- if USE_FALLBACK_IMAGE
- default ROM_SECTION_SIZE = FALLBACK_SIZE
- default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE )
- else
- default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE )
- default ROM_SECTION_OFFSET = 0
- end
-end
-
-##
-## Compute the start location and size size of
-## The linuxBIOS bootloader.
-##
-default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
-default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
-
-##
-## Compute where this copy of linuxBIOS will start in the boot rom
-##
-default _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
-
-##
-## Compute a range of ROM that can cached to speed up linuxBIOS,
-## execution speed.
-##
-## XIP_ROM_SIZE must be a power of 2.
-## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
-##
-default XIP_ROM_SIZE=65536
-
-if USE_FAILOVER_IMAGE
- default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE)
-else
- if USE_FALLBACK_IMAGE
- default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE + FAILOVER_SIZE)
- else
- default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE)
- end
-end
-
-arch i386 end
-
-##
-## Build the objects we have code for in this directory.
-##
-
-driver mainboard.o
-
-#dir /drivers/si/3114
-
-#needed by irq_tables and mptable and acpi_tables
-object get_bus_conf.o
-
-if HAVE_MP_TABLE
- object mptable.o
-end
-
-if HAVE_PIRQ_TABLE
- object irq_tables.o
-end
-
-#if HAVE_ACPI_TABLES
-# object acpi_tables.o
-# object fadt.o
-# if SB_HT_CHAIN_ON_BUS0
-# object dsdt_bus0.o
-# else
-# object dsdt.o
-# end
-# object ssdt.o
-# if ACPI_SSDTX_NUM
-# if SB_HT_CHAIN_ON_BUS0
-# object ssdt2_bus0.o
-# else
-# object ssdt2.o
-# end
-# end
-#end
-
-if HAVE_ACPI_TABLES
- object acpi_tables.o
- object fadt.o
- makerule dsdt.c
- depends "$(MAINBOARD)/dx/dsdt_lb.dsl"
- action "/usr/sbin/iasl -tc $(MAINBOARD)/dx/dsdt_lb.dsl"
- action "mv dsdt_lb.hex dsdt.c"
- end
- object ./dsdt.o
-
- #./ssdt.o is moved to northbridge/amd/amdk8/Config.lb
-
- if ACPI_SSDTX_NUM
- makerule ssdt2.c
- depends "$(MAINBOARD)/dx/pci2.asl"
- action "/usr/sbin/iasl -tc $(MAINBOARD)/dx/pci2.asl"
- action "perl -pi -e 's/AmlCode/AmlCode_ssdt2/g' pci2.hex"
- action "mv pci2.hex ssdt2.c"
- end
- object ./ssdt2.o
- makerule ssdt3.c
- depends "$(MAINBOARD)/dx/pci3.asl"
- action "/usr/sbin/iasl -tc $(MAINBOARD)/dx/pci3.asl"
- action "perl -pi -e 's/AmlCode/AmlCode_ssdt3/g' pci3.hex"
- action "mv pci3.hex ssdt3.c"
- end
- object ./ssdt3.o
- makerule ssdt4.c
- depends "$(MAINBOARD)/dx/pci4.asl"
- action "/usr/sbin/iasl -tc $(MAINBOARD)/dx/pci4.asl"
- action "perl -pi -e 's/AmlCode/AmlCode_ssdt4/g' pci4.hex"
- action "mv pci4.hex ssdt4.c"
- end
- object ./ssdt4.o
- end
-end
-
-if USE_DCACHE_RAM
-
- if CONFIG_USE_INIT
- # compile cache_as_ram.c to auto.o
- makerule ./cache_as_ram_auto.o
- depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
- action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@"
- end
-
- else
- #compile cache_as_ram.c to auto.inc
- makerule ./cache_as_ram_auto.inc
- depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
- action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
- action "perl -e 's/.rodata/.rom.data/g' -pi $@"
- action "perl -e 's/.text/.section .rom.text/g' -pi $@"
- end
-
- end
-end
-
-if USE_FAILOVER_IMAGE
-else
- if CONFIG_AP_CODE_IN_CAR
- makerule ./apc_auto.o
- depends "$(MAINBOARD)/apc_auto.c option_table.h"
- action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/apc_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@"
- end
- ldscript /arch/i386/init/ldscript_apc.lb
- end
-end
-
-##
-## Build our 16 bit and 32 bit linuxBIOS entry code
-##
-
-if HAVE_FAILOVER_BOOT
- if USE_FAILOVER_IMAGE
- mainboardinit cpu/x86/16bit/entry16.inc
- ldscript /cpu/x86/16bit/entry16.lds
- end
-else
- if USE_FALLBACK_IMAGE
- mainboardinit cpu/x86/16bit/entry16.inc
- ldscript /cpu/x86/16bit/entry16.lds
- end
-end
-
-mainboardinit cpu/x86/32bit/entry32.inc
-if USE_DCACHE_RAM
- if CONFIG_USE_INIT
- ldscript /cpu/x86/32bit/entry32.lds
- end
-
- if CONFIG_USE_INIT
- ldscript /cpu/amd/car/cache_as_ram.lds
- end
-end
-
-##
-## Build our reset vector (This is where linuxBIOS is entered)
-##
-if HAVE_FAILOVER_BOOT
- if USE_FAILOVER_IMAGE
- mainboardinit cpu/x86/16bit/reset16.inc
- ldscript /cpu/x86/16bit/reset16.lds
- else
- mainboardinit cpu/x86/32bit/reset32.inc
- ldscript /cpu/x86/32bit/reset32.lds
- end
-else
- if USE_FALLBACK_IMAGE
- mainboardinit cpu/x86/16bit/reset16.inc
- ldscript /cpu/x86/16bit/reset16.lds
- else
- mainboardinit cpu/x86/32bit/reset32.inc
- ldscript /cpu/x86/32bit/reset32.lds
- end
-end
-
-##
-## Include an id string (For safe flashing)
-##
-mainboardinit arch/i386/lib/id.inc
-ldscript /arch/i386/lib/id.lds
-
-if USE_DCACHE_RAM
- ##
- ## Setup Cache-As-Ram
- ##
- mainboardinit cpu/amd/car/cache_as_ram.inc
-end
-
-###
-### This is the early phase of linuxBIOS startup
-### Things are delicate and we test to see if we should
-### failover to another image.
-###
-if HAVE_FAILOVER_BOOT
- if USE_FAILOVER_IMAGE
- if USE_DCACHE_RAM
- ldscript /arch/i386/lib/failover_failover.lds
- end
- end
-else
- if USE_FALLBACK_IMAGE
- if USE_DCACHE_RAM
- ldscript /arch/i386/lib/failover.lds
- end
- end
-end
-
-###
-### O.k. We aren't just an intermediary anymore!
-###
-
-##
-## Setup RAM
-##
-if USE_DCACHE_RAM
-
- if CONFIG_USE_INIT
- initobject cache_as_ram_auto.o
- else
- mainboardinit ./cache_as_ram_auto.inc
- end
-
-end
-
-##
-## Include the secondary Configuration files
-##
-if CONFIG_CHIP_NAME
- config chip.h
-end
-
-dir /southbridge/amd/amd8132
-
-chip northbridge/amd/amdk8/root_complex
- device apic_cluster 0 on
- chip cpu/amd/socket_940
- device apic 0 on end
- end
- end
- device pci_domain 0 on
- chip northbridge/amd/amdk8
- device pci 18.0 on end
- device pci 18.0 on end
- device pci 18.0 on # northbridge
- chip southbridge/amd/amd8131
- # the on/off keyword is mandatory
- device pci 0.0 on end
- device pci 0.1 on end
- device pci 1.0 on end
- device pci 1.1 on end
- end
- chip southbridge/amd/amd8111
- # this "device pci 0.0" is the parent the next one
- # PCI bridge
- device pci 0.0 on
- device pci 0.0 on end
- device pci 0.1 on end
- device pci 0.2 off end
- device pci 1.0 off end
- #chip drivers/pci/onboard
- # device pci 6.0 on end
- # register "rom_address" = "0xfff80000"
- #end
- end
- device pci 1.0 on
- chip superio/winbond/w83627hf
- device pnp 2e.0 off # Floppy
- io 0x60 = 0x3f0
- irq 0x70 = 6
- drq 0x74 = 2
- end
- device pnp 2e.1 off # Parallel Port
- io 0x60 = 0x378
- irq 0x70 = 7
- end
- device pnp 2e.2 on # Com1
- io 0x60 = 0x3f8
- irq 0x70 = 4
- end
- device pnp 2e.3 off # Com2
- io 0x60 = 0x2f8
- irq 0x70 = 3
- end
- device pnp 2e.5 on # Keyboard
- io 0x60 = 0x60
- io 0x62 = 0x64
- irq 0x70 = 1
- irq 0x72 = 12
- end
- device pnp 2e.6 off # CIR
- io 0x60 = 0x100
- end
- device pnp 2e.7 off # GAME_MIDI_GIPO1
- io 0x60 = 0x220
- io 0x62 = 0x300
- irq 0x70 = 9
- end
- device pnp 2e.8 off end # GPIO2
- device pnp 2e.9 off end # GPIO3
- device pnp 2e.a off end # ACPI
- device pnp 2e.b on # HW Monitor
- io 0x60 = 0x290
- irq 0x70 = 5
- end
- end
- end
- device pci 1.1 on end
- device pci 1.2 on end
- device pci 1.3 on
- chip drivers/generic/generic #dimm 0-0-0
- device i2c 50 on end
- end
- chip drivers/generic/generic #dimm 0-0-1
- device i2c 51 on end
- end
- chip drivers/generic/generic #dimm 0-1-0
- device i2c 52 on end
- end
- chip drivers/generic/generic #dimm 0-1-1
- device i2c 53 on end
- end
- chip drivers/generic/generic #dimm 1-0-0
- device i2c 54 on end
- end
- chip drivers/generic/generic #dimm 1-0-1
- device i2c 55 on end
- end
- chip drivers/generic/generic #dimm 1-1-0
- device i2c 56 on end
- end
- chip drivers/generic/generic #dimm 1-1-1
- device i2c 57 on end
- end
- end # acpi
- device pci 1.5 off end
- device pci 1.6 off end
- register "ide0_enable" = "1"
- register "ide1_enable" = "1"
- end
- end # device pci 18.0
-
- device pci 18.1 on end
- device pci 18.2 on end
- device pci 18.3 on end
- end
-
- end #pci_domain
-# chip drivers/generic/debug
-# device pnp 0.0 off end # chip name
-# device pnp 0.1 on end # pci_regs_all
-# device pnp 0.2 off end # mem
-# device pnp 0.3 off end # cpuid
-# device pnp 0.4 off end # smbus_regs_all
-# device pnp 0.5 off end # dual core msr
-# device pnp 0.6 off end # cache size
-# device pnp 0.7 off end # tsc
-# end
-
-end
-
-
+++ /dev/null
-uses HAVE_MP_TABLE
-uses HAVE_PIRQ_TABLE
-uses HAVE_ACPI_TABLES
-uses ACPI_SSDTX_NUM
-uses USE_FALLBACK_IMAGE
-uses USE_FAILOVER_IMAGE
-uses HAVE_FALLBACK_BOOT
-uses HAVE_FAILOVER_BOOT
-uses HAVE_HARD_RESET
-uses IRQ_SLOT_COUNT
-uses HAVE_OPTION_TABLE
-uses CONFIG_MAX_CPUS
-uses CONFIG_MAX_PHYSICAL_CPUS
-uses CONFIG_LOGICAL_CPUS
-uses CONFIG_IOAPIC
-uses CONFIG_SMP
-uses FALLBACK_SIZE
-uses FAILOVER_SIZE
-uses ROM_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_IMAGE_SIZE
-uses ROM_SECTION_SIZE
-uses ROM_SECTION_OFFSET
-uses CONFIG_ROM_STREAM
-uses CONFIG_ROM_STREAM_START
-uses CONFIG_COMPRESSED_ROM_STREAM
-uses PAYLOAD_SIZE
-uses _ROMBASE
-uses XIP_ROM_SIZE
-uses XIP_ROM_BASE
-uses STACK_SIZE
-uses HEAP_SIZE
-uses USE_OPTION_TABLE
-uses LB_CKS_RANGE_START
-uses LB_CKS_RANGE_END
-uses LB_CKS_LOC
-uses MAINBOARD_PART_NUMBER
-uses MAINBOARD_VENDOR
-uses MAINBOARD
-uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
-uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
-uses LINUXBIOS_EXTRA_VERSION
-uses _RAMBASE
-uses TTYS0_BAUD
-uses TTYS0_BASE
-uses TTYS0_LCS
-uses DEFAULT_CONSOLE_LOGLEVEL
-uses MAXIMUM_CONSOLE_LOGLEVEL
-uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
-uses CONFIG_CONSOLE_SERIAL8250
-uses HAVE_INIT_TIMER
-uses CONFIG_GDB_STUB
-uses CONFIG_GDB_STUB
-uses CROSS_COMPILE
-uses CC
-uses HOSTCC
-uses OBJCOPY
-uses CONFIG_CHIP_NAME
-uses CONFIG_CONSOLE_VGA
-uses CONFIG_PCI_ROM_RUN
-uses HW_MEM_HOLE_SIZEK
-uses HW_MEM_HOLE_SIZE_AUTO_INC
-uses K8_HT_FREQ_1G_SUPPORT
-
-uses HT_CHAIN_UNITID_BASE
-uses HT_CHAIN_END_UNITID_BASE
-uses SB_HT_CHAIN_ON_BUS0
-uses SB_HT_CHAIN_UNITID_OFFSET_ONLY
-
-uses USE_DCACHE_RAM
-uses DCACHE_RAM_BASE
-uses DCACHE_RAM_SIZE
-uses DCACHE_RAM_GLOBAL_VAR_SIZE
-uses CONFIG_USE_INIT
-
-uses SERIAL_CPU_INIT
-
-uses ENABLE_APIC_EXT_ID
-uses APIC_ID_OFFSET
-uses LIFT_BSP_APIC_ID
-
-uses CONFIG_PCI_64BIT_PREF_MEM
-
-uses CONFIG_LB_MEM_TOPK
-
-uses CONFIG_AP_CODE_IN_CAR
-
-uses MEM_TRAIN_SEQ
-
-uses WAIT_BEFORE_CPUS_INIT
-
-uses CONFIG_USE_PRINTK_IN_CAR
-
-###
-### Build options
-###
-
-##
-## ROM_SIZE is the size of boot ROM that this board will use.
-##
-default ROM_SIZE=524288
-
-##
-## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
-##
-#default FALLBACK_SIZE=131072
-#default FALLBACK_SIZE=0x40000
-
-#FALLBACK: 256K-4K
-default FALLBACK_SIZE=0x3f000
-#FAILOVER: 4K
-default FAILOVER_SIZE=0x01000
-
-#more 1M for pgtbl
-default CONFIG_LB_MEM_TOPK=2048
-
-##
-## Build code for the fallback boot
-##
-default HAVE_FALLBACK_BOOT=1
-default HAVE_FAILOVER_BOOT=1
-
-##
-## Build code to reset the motherboard from linuxBIOS
-##
-default HAVE_HARD_RESET=1
-
-##
-## Build code to export a programmable irq routing table
-##
-default HAVE_PIRQ_TABLE=1
-default IRQ_SLOT_COUNT=11
-
-##
-## Build code to export an x86 MP table
-## Useful for specifying IRQ routing values
-##
-default HAVE_MP_TABLE=1
-
-## ACPI tables will be included
-default HAVE_ACPI_TABLES=1
-## extra SSDT num
-default ACPI_SSDTX_NUM=3
-
-##
-## Build code to export a CMOS option table
-##
-default HAVE_OPTION_TABLE=1
-
-##
-## Move the default LinuxBIOS cmos range off of AMD RTC registers
-##
-default LB_CKS_RANGE_START=49
-default LB_CKS_RANGE_END=122
-default LB_CKS_LOC=123
-
-##
-## Build code for SMP support
-## Only worry about 2 micro processors
-##
-default CONFIG_SMP=1
-default CONFIG_MAX_CPUS=4
-default CONFIG_MAX_PHYSICAL_CPUS=2
-default CONFIG_LOGICAL_CPUS=1
-
-default SERIAL_CPU_INIT=0
-
-default ENABLE_APIC_EXT_ID=0
-default APIC_ID_OFFSET=0x10
-default LIFT_BSP_APIC_ID=1
-
-#CHIP_NAME ?
-default CONFIG_CHIP_NAME=1
-
-#memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead.
-#2G
-#default HW_MEM_HOLE_SIZEK=0x200000
-#1G
-#default HW_MEM_HOLE_SIZEK=0x100000
-#512M
-default HW_MEM_HOLE_SIZEK=0x80000
-
-#make auto increase hole size to avoid hole_startk equal to basek so as to make some kernel happy
-#default HW_MEM_HOLE_SIZE_AUTO_INC=1
-
-#Opteron K8 1G HT Support
-default K8_HT_FREQ_1G_SUPPORT=1
-
-#VGA Console
-default CONFIG_CONSOLE_VGA=1
-default CONFIG_PCI_ROM_RUN=1
-
-#HT Unit ID offset, default is 1, the typical one
-default HT_CHAIN_UNITID_BASE=0xa
-
-#real SB Unit ID, default is 0x20, mean dont touch it at last
-default HT_CHAIN_END_UNITID_BASE=0x6
-
-#make the SB HT chain on bus 0, default is not (0)
-default SB_HT_CHAIN_ON_BUS0=2
-
-#only offset for SB chain?, default is yes(1)
-#default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
-
-#allow capable device use that above 4G
-#default CONFIG_PCI_64BIT_PREF_MEM=1
-
-##
-## enable CACHE_AS_RAM specifics
-##
-default USE_DCACHE_RAM=1
-default DCACHE_RAM_BASE=0xc4000
-default DCACHE_RAM_SIZE=0x0c000
-default DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000
-default CONFIG_USE_INIT=0
-
-##
-## for rev F training on AP purpose
-##
-#default CONFIG_AP_CODE_IN_CAR=1
-#default MEM_TRAIN_SEQ=1
-#default WAIT_BEFORE_CPUS_INIT=1
-
-##
-## Build code to setup a generic IOAPIC
-##
-default CONFIG_IOAPIC=1
-
-##
-## Clean up the motherboard id strings
-##
-default MAINBOARD_PART_NUMBER="dk8_htx"
-default MAINBOARD_VENDOR="Iwill"
-default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022
-default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2b80
-
-###
-### LinuxBIOS layout values
-###
-
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
-default ROM_IMAGE_SIZE = 65536
-
-##
-## Use a small 8K stack
-##
-default STACK_SIZE=0x2000
-
-##
-## Use a small 32K heap
-##
-default HEAP_SIZE=0x8000
-
-##
-## Only use the option table in a normal image
-##
-default USE_OPTION_TABLE = (!USE_FALLBACK_IMAGE) && (!USE_FAILOVER_IMAGE )
-
-##
-## LinuxBIOS C code runs at this location in RAM
-##
-default _RAMBASE=0x00100000
-
-##
-## Load the payload from the ROM
-##
-default CONFIG_ROM_STREAM = 1
-
-#default CONFIG_COMPRESSED_ROM_STREAM = 1
-
-###
-### Defaults of options that you may want to override in the target config file
-###
-
-##
-## The default compiler
-##
-default CC="$(CROSS_COMPILE)gcc -m32"
-default HOSTCC="gcc"
-
-##
-## Disable the gdb stub by default
-##
-default CONFIG_GDB_STUB=0
-
-##
-## The Serial Console
-##
-default CONFIG_USE_PRINTK_IN_CAR=1
-
-# To Enable the Serial Console
-default CONFIG_CONSOLE_SERIAL8250=1
-
-## Select the serial console baud rate
-default TTYS0_BAUD=115200
-#default TTYS0_BAUD=57600
-#default TTYS0_BAUD=38400
-#default TTYS0_BAUD=19200
-#default TTYS0_BAUD=9600
-#default TTYS0_BAUD=4800
-#default TTYS0_BAUD=2400
-#default TTYS0_BAUD=1200
-
-# Select the serial console base port
-default TTYS0_BASE=0x3f8
-
-# Select the serial protocol
-# This defaults to 8 data bits, 1 stop bit, and no parity
-default TTYS0_LCS=0x3
-
-##
-### Select the linuxBIOS loglevel
-##
-## EMERG 1 system is unusable
-## ALERT 2 action must be taken immediately
-## CRIT 3 critical conditions
-## ERR 4 error conditions
-## WARNING 5 warning conditions
-## NOTICE 6 normal but significant condition
-## INFO 7 informational
-## DEBUG 8 debug-level messages
-## SPEW 9 Way too many details
-
-## Request this level of debugging output
-default DEFAULT_CONSOLE_LOGLEVEL=8
-## At a maximum only compile in this level of debugging
-default MAXIMUM_CONSOLE_LOGLEVEL=8
-
-##
-## Select power on after power fail setting
-default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
-
-### End Options.lb
-end
+++ /dev/null
-/*
- * Island Aruma ACPI support
- * written by Stefan Reinauer <stepan@openbios.org>
- * (C) 2005 Stefan Reinauer
- *
- *
- * Copyright 2005 AMD
- * 2005.9 yhlu modify that to more dynamic for AMD Opteron Based MB
- */
-
-#include <console/console.h>
-#include <string.h>
-#include <arch/acpi.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <cpu/x86/msr.h>
-#include <cpu/amd/mtrr.h>
-#include <cpu/amd/amdk8_sysconf.h>
-
-#include "mb_sysconf.h"
-
-#define DUMP_ACPI_TABLES 0
-
-#if DUMP_ACPI_TABLES == 1
-static void dump_mem(unsigned start, unsigned end)
-{
-
- unsigned i;
- print_debug("dump_mem:");
- for(i=start;i<end;i++) {
- if((i & 0xf)==0) {
- printk_debug("\n%08x:", i);
- }
- printk_debug(" %02x", (unsigned char)*((unsigned char *)i));
- }
- print_debug("\n");
- }
-#endif
-
-extern unsigned char AmlCode[];
-extern unsigned char AmlCode_ssdt[];
-
-#if ACPI_SSDTX_NUM >= 1
-extern unsigned char AmlCode_ssdt2[];
-extern unsigned char AmlCode_ssdt3[];
-extern unsigned char AmlCode_ssdt4[];
-#endif
-
-#define IO_APIC_ADDR 0xfec00000UL
-
-unsigned long acpi_fill_madt(unsigned long current)
-{
- unsigned int gsi_base=0x18;
-
- struct mb_sysconf_t *m;
-
- m = sysconf.mb;
-
- /* create all subtables for processors */
- current = acpi_create_madt_lapics(current);
-
- /* Write 8111 IOAPIC */
- current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8111,
- IO_APIC_ADDR, 0);
-
- /* Write all 8131 IOAPICs */
- {
- device_t dev;
- struct resource *res;
- dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN((sysconf.hcdn[0]&0xff), 1));
- if (dev) {
- res = find_resource(dev, PCI_BASE_ADDRESS_0);
- if (res) {
- current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8132_1,
- res->base, gsi_base );
- gsi_base+=4;
-
- }
- }
- dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN((sysconf.hcdn[0] & 0xff)+1, 1));
- if (dev) {
- res = find_resource(dev, PCI_BASE_ADDRESS_0);
- if (res) {
- current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8132_2,
- res->base, gsi_base );
- gsi_base+=4;
- }
- }
-
- int i;
- int j = 0;
-
- for(i=1; i< sysconf.hc_possible_num; i++) {
- unsigned d;
- if(!(sysconf.pci1234[i] & 0x1) ) continue;
- // 8131 need to use +4
-
- switch (sysconf.hcid[i]) {
- case 1:
- d = 7;
- break;
- case 3:
- d = 4;
- break;
- }
- switch (sysconf.hcid[i]) {
- case 1:
- case 3:
- dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j], 1));
- if (dev) {
- res = find_resource(dev, PCI_BASE_ADDRESS_0);
- if (res) {
- current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8132a[j][0],
- res->base, gsi_base );
- gsi_base+=d;
- }
- }
- dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1, 1));
- if (dev) {
- res = find_resource(dev, PCI_BASE_ADDRESS_0);
- if (res) {
- current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8132a[j][1],
- res->base, gsi_base );
- gsi_base+=d;
-
- }
- }
- break;
- }
-
- j++;
- }
-
- }
-
- current += acpi_create_madt_irqoverride( (acpi_madt_irqoverride_t *)
- current, 0, 0, 2, 5 );
- /* 0: mean bus 0--->ISA */
- /* 0: PIC 0 */
- /* 2: APIC 2 */
- /* 5 mean: 0101 --> Edige-triggered, Active high*/
-
-
- /* create all subtables for processors */
- current = acpi_create_madt_lapic_nmis(current, 5, 1);
- /* 1: LINT1 connect to NMI */
-
-
- return current;
-}
-
-extern void get_bus_conf(void);
-
-extern void update_ssdt(void *ssdt);
-
-void update_ssdtx(void *ssdtx, int i)
-{
- uint8_t *PCI;
- uint8_t *HCIN;
- uint8_t *UID;
-
- PCI = ssdtx + 0x32;
- HCIN = ssdtx + 0x39;
- UID = ssdtx + 0x40;
-
- if(i<7) {
- *PCI = (uint8_t) ('4' + i - 1);
- }
- else {
- *PCI = (uint8_t) ('A' + i - 1 - 6);
- }
- *HCIN = (uint8_t) i;
- *UID = (uint8_t) (i+3);
-
- /* FIXME: need to update the GSI id in the ssdtx too */
-
-}
-
-unsigned long write_acpi_tables(unsigned long start)
-{
- unsigned long current;
- acpi_rsdp_t *rsdp;
- acpi_rsdt_t *rsdt;
- acpi_hpet_t *hpet;
- acpi_madt_t *madt;
- acpi_srat_t *srat;
- acpi_slit_t *slit;
- acpi_fadt_t *fadt;
- acpi_facs_t *facs;
- acpi_header_t *dsdt;
- acpi_header_t *ssdt;
- acpi_header_t *ssdtx;
- unsigned char *p;
-
- unsigned char *AmlCode_ssdtx[HC_POSSIBLE_NUM];
-
- int i;
-
- get_bus_conf(); //it will get sblk, pci1234, hcdn, and sbdn
-
- /* Align ACPI tables to 16byte */
- start = ( start + 0x0f ) & -0x10;
- current = start;
-
- printk_info("ACPI: Writing ACPI tables at %lx...\n", start);
-
- /* We need at least an RSDP and an RSDT Table */
- rsdp = (acpi_rsdp_t *) current;
- current += sizeof(acpi_rsdp_t);
- rsdt = (acpi_rsdt_t *) current;
- current += sizeof(acpi_rsdt_t);
-
- /* clear all table memory */
- memset((void *)start, 0, current - start);
-
- acpi_write_rsdp(rsdp, rsdt);
- acpi_write_rsdt(rsdt);
-
- /*
- * We explicitly add these tables later on:
- */
- printk_debug("ACPI: * HPET\n");
- hpet = (acpi_hpet_t *) current;
- current += sizeof(acpi_hpet_t);
- acpi_create_hpet(hpet);
- acpi_add_table(rsdt,hpet);
-
- /* If we want to use HPET Timers Linux wants an MADT */
- printk_debug("ACPI: * MADT\n");
- madt = (acpi_madt_t *) current;
- acpi_create_madt(madt);
- current+=madt->header.length;
- acpi_add_table(rsdt,madt);
-
-
- /* SRAT */
- printk_debug("ACPI: * SRAT\n");
- srat = (acpi_srat_t *) current;
- acpi_create_srat(srat);
- current+=srat->header.length;
- acpi_add_table(rsdt,srat);
-
- /* SLIT */
- printk_debug("ACPI: * SLIT\n");
- slit = (acpi_slit_t *) current;
- acpi_create_slit(slit);
- current+=slit->header.length;
- acpi_add_table(rsdt,slit);
-
- /* SSDT */
- printk_debug("ACPI: * SSDT\n");
- ssdt = (acpi_header_t *)current;
- current += ((acpi_header_t *)AmlCode_ssdt)->length;
- memcpy((void *)ssdt, (void *)AmlCode_ssdt, ((acpi_header_t *)AmlCode_ssdt)->length);
- //Here you need to set value in pci1234, sblk and sbdn in get_bus_conf.c
- update_ssdt((void*)ssdt);
- /* recalculate checksum */
- ssdt->checksum = 0;
- ssdt->checksum = acpi_checksum((unsigned char *)ssdt,ssdt->length);
- acpi_add_table(rsdt,ssdt);
-
-#if ACPI_SSDTX_NUM >= 1
-
- //same htio, but different position? We may have to copy, change HCIN, and recalculate the checknum and add_table
-
- for(i=1;i<sysconf.hc_possible_num;i++) { // 0: is hc sblink
- if((sysconf.pci1234[i] & 1) != 1 ) continue;
- uint8_t c;
- if(i<7) {
- c = (uint8_t) ('4' + i - 1);
- }
- else {
- c = (uint8_t) ('A' + i - 1 - 6);
- }
- printk_debug("ACPI: * SSDT for PCI%c Aka hcid = %d\n", c, sysconf.hcid[i]); //pci0 and pci1 are in dsdt
- current = ( current + 0x07) & -0x08;
- ssdtx = (acpi_header_t *)current;
- switch(sysconf.hcid[i]) {
- case 1: //8132
- p = AmlCode_ssdt2;
- break;
- case 2: //8151
- p = AmlCode_ssdt3;
- break;
- case 3: //8131
- p = AmlCode_ssdt4;
- break;
- default:
- continue;
- }
- current += ((acpi_header_t *)p)->length;
- memcpy((void *)ssdtx, (void *)p, ((acpi_header_t *)p)->length);
- update_ssdtx((void *)ssdtx, i);
- ssdtx->checksum = 0;
- ssdtx->checksum = acpi_checksum((unsigned char *)ssdtx,ssdtx->length);
- acpi_add_table(rsdt,ssdtx);
- }
-#endif
-
- /* FACS */
- printk_debug("ACPI: * FACS\n");
- facs = (acpi_facs_t *) current;
- current += sizeof(acpi_facs_t);
- acpi_create_facs(facs);
-
- /* DSDT */
- printk_debug("ACPI: * DSDT\n");
- dsdt = (acpi_header_t *)current;
- current += ((acpi_header_t *)AmlCode)->length;
- memcpy((void *)dsdt,(void *)AmlCode, \
- ((acpi_header_t *)AmlCode)->length);
- printk_debug("ACPI: * DSDT @ %08x Length %x\n",dsdt,dsdt->length);
-
- /* FDAT */
- printk_debug("ACPI: * FADT\n");
- fadt = (acpi_fadt_t *) current;
- current += sizeof(acpi_fadt_t);
-
- acpi_create_fadt(fadt,facs,dsdt);
- acpi_add_table(rsdt,fadt);
-
-#if DUMP_ACPI_TABLES == 1
- printk_debug("rsdp\n");
- dump_mem(rsdp, ((void *)rsdp) + sizeof(acpi_rsdp_t));
-
- printk_debug("rsdt\n");
- dump_mem(rsdt, ((void *)rsdt) + sizeof(acpi_rsdt_t));
-
- printk_debug("madt\n");
- dump_mem(madt, ((void *)madt) + madt->header.length);
-
- printk_debug("srat\n");
- dump_mem(srat, ((void *)srat) + srat->header.length);
-
- printk_debug("slit\n");
- dump_mem(slit, ((void *)slit) + slit->header.length);
-
- printk_debug("ssdt\n");
- dump_mem(ssdt, ((void *)ssdt) + ssdt->length);
-
- printk_debug("fadt\n");
- dump_mem(fadt, ((void *)fadt) + fadt->header.length);
-#endif
-
- printk_info("ACPI: done.\n");
- return current;
-}
-
+++ /dev/null
-#define ASSEMBLY 1
-#define __ROMCC__
-
-#define RAMINIT_SYSINFO 1
-#define CACHE_AS_RAM_ADDRESS_DEBUG 0
-
-#define SET_NB_CFG_54 1
-
-//used by raminit
-#define QRANK_DIMM_SUPPORT 1
-
-//used by incoherent_ht
-//#define K8_SCAN_PCI_BUS 1
-//#define K8_ALLOCATE_IO_RANGE 1
-
-
-//used by init_cpus and fidvid
-#define K8_SET_FIDVID 0
-//if we want to wait for core1 done before DQS training, set it to 0
-#define K8_SET_FIDVID_CORE0_ONLY 1
-
-#if K8_REV_F_SUPPORT == 1
-#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
-#endif
-
-#include <stdint.h>
-#include <device/pci_def.h>
-#include <device/pci_ids.h>
-#include <arch/io.h>
-#include <device/pnp_def.h>
-#include <arch/romcc_io.h>
-#include <cpu/x86/lapic.h>
-#include "option_table.h"
-#include "pc80/mc146818rtc_early.c"
-
-#if USE_FAILOVER_IMAGE==0
-#include "pc80/serial.c"
-#include "arch/i386/lib/console.c"
-#include <cpu/amd/model_fxx_rev.h>
-#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
-#include "northbridge/amd/amdk8/raminit.h"
-#include "cpu/amd/model_fxx/apic_timer.c"
-#endif
-
-
-
-#include "cpu/x86/lapic/boot_cpu.c"
-#include "northbridge/amd/amdk8/reset_test.c"
-
-#if USE_FAILOVER_IMAGE==0
-#include "cpu/x86/bist.h"
-
-#include "lib/delay.c"
-
-#if CONFIG_USE_INIT == 0
- #include "lib/memcpy.c"
- #if CONFIG_USE_PRINTK_IN_CAR == 1
- #include "lib/uart8250.c"
- #include "console/vtxprintf.c"
- #include "arch/i386/lib/printk_init.c"
- #endif
-#endif
-#include "northbridge/amd/amdk8/debug.c"
-#include "cpu/amd/mtrr/amd_earlymtrr.c"
-#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
-
-#include "northbridge/amd/amdk8/setup_resource_map.c"
-
-#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
-
-#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
-
-/*
- * GPIO28 of 8111 will control H0_MEMRESET_L
- * GPIO29 of 8111 will control H1_MEMRESET_L
- */
-static void memreset_setup(void)
-{
- if (is_cpu_pre_c0()) {
- /* Set the memreset low */
- outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
- /* Ensure the BIOS has control of the memory lines */
- outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
- } else {
- /* Ensure the CPU has controll of the memory lines */
- outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29);
- }
-}
-
-static void memreset(int controllers, const struct mem_controller *ctrl)
-{
- if (is_cpu_pre_c0()) {
- udelay(800);
- /* Set memreset_high */
- outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
- udelay(90);
- }
-}
-
-static inline void activate_spd_rom(const struct mem_controller *ctrl)
-{
-}
-
-static inline int spd_read_byte(unsigned device, unsigned address)
-{
- return smbus_read_byte(device, address);
-}
-
-#include "northbridge/amd/amdk8/amdk8.h"
-#include "northbridge/amd/amdk8/coherent_ht_car.c"
-
-#include "northbridge/amd/amdk8/incoherent_ht.c"
-
-#include "northbridge/amd/amdk8/raminit.c"
-
-#include "sdram/generic_sdram.c"
-#include "ram/ramtest.c"
-
- /* tyan does not want the default */
-#include "resourcemap.c"
-
-#include "cpu/amd/dualcore/dualcore.c"
-
-#define DIMM0 0x50
-#define DIMM1 0x51
-#define DIMM2 0x52
-#define DIMM3 0x53
-#define DIMM4 0x54
-#define DIMM5 0x55
-#define DIMM6 0x56
-#define DIMM7 0x57
-
-
-#include "cpu/amd/car/copy_and_run.c"
-#include "cpu/amd/car/post_cache_as_ram.c"
-
-#include "cpu/amd/model_fxx/init_cpus.c"
-
-#include "cpu/amd/model_fxx/fidvid.c"
-#endif
-
-#if ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE == 1)) || ((HAVE_FAILOVER_BOOT==0) && (USE_FALLBACK_IMAGE == 1))
-
-#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
-#include "northbridge/amd/amdk8/early_ht.c"
-
-void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
-{
-
- unsigned last_boot_normal_x = last_boot_normal();
-
- /* Is this a cpu only reset? or Is this a secondary cpu? */
- if ((cpu_init_detectedx) || (!boot_cpu())) {
- if (last_boot_normal_x) {
- goto normal_image;
- } else {
- goto fallback_image;
- }
- }
-
- /* Nothing special needs to be done to find bus 0 */
- /* Allow the HT devices to be found */
-
- enumerate_ht_chain();
-
- /* Setup the rom access for 4M */
- amd8111_enable_rom();
-
- /* Is this a deliberate reset by the bios */
- if (bios_reset_detected() && last_boot_normal_x) {
- goto normal_image;
- }
- /* This is the primary cpu how should I boot? */
- else if (do_normal_boot()) {
- goto normal_image;
- }
- else {
- goto fallback_image;
- }
- normal_image:
- __asm__ volatile ("jmp __normal_image"
- : /* outputs */
- : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
- );
-
- fallback_image:
-#if HAVE_FAILOVER_BOOT==1
- __asm__ volatile ("jmp __fallback_image"
- : /* outputs */
- : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
- )
-#endif
- ;
-}
-#endif
-
-void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
-
-void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
-{
-#if HAVE_FAILOVER_BOOT==1
- #if USE_FAILOVER_IMAGE==1
- failover_process(bist, cpu_init_detectedx);
- #else
- real_main(bist, cpu_init_detectedx);
- #endif
-#else
- #if USE_FALLBACK_IMAGE == 1
- failover_process(bist, cpu_init_detectedx);
- #endif
- real_main(bist, cpu_init_detectedx);
-#endif
-}
-
-#if USE_FAILOVER_IMAGE==0
-
-void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
-{
- static const uint16_t spd_addr[] = {
- //first node
- DIMM0, DIMM2, 0, 0,
- DIMM1, DIMM3, 0, 0,
-#if CONFIG_MAX_PHYSICAL_CPUS > 1
- //second node
- DIMM4, DIMM6, 0, 0,
- DIMM5, DIMM7, 0, 0,
-#endif
-
- };
-
- struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE);
-
- int needs_reset; int i;
- unsigned bsp_apicid = 0;
-
- if (bist == 0) {
- bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
- }
-
- w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
- uart_init();
- console_init();
-
- /* Halt if there was a built in self test failure */
- report_bist_failure(bist);
-
- print_debug("*sysinfo range: ["); print_debug_hex32(sysinfo); print_debug(","); print_debug_hex32((unsigned long)sysinfo+sizeof(struct sys_info)); print_debug(")\r\n");
-
- setup_mb_resource_map();
-
- print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n");
-
-#if MEM_TRAIN_SEQ == 1
- set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
-#endif
- setup_coherent_ht_domain(); // routing table and start other core0
-
- wait_all_core0_started();
-#if CONFIG_LOGICAL_CPUS==1
- // It is said that we should start core1 after all core0 launched
- /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
- * So here need to make sure last core0 is started, esp for two way system,
- * (there may be apic id conflicts in that case)
- */
- start_other_cores();
- wait_all_other_cores_started(bsp_apicid);
-#endif
-
- /* it will set up chains and store link pair for optimization later */
- ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
-
-
-#if K8_SET_FIDVID == 1
-
- {
- msr_t msr;
- msr=rdmsr(0xc0010042);
- print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n");
-
- }
-
- enable_fid_change();
-
- enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
-
- init_fidvid_bsp(bsp_apicid);
-
- // show final fid and vid
- {
- msr_t msr;
- msr=rdmsr(0xc0010042);
- print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n");
-
- }
-#endif
-
- needs_reset = optimize_link_coherent_ht();
- needs_reset |= optimize_link_incoherent_ht(sysinfo);
-
- // fidvid change will issue one LDTSTOP and the HT change will be effective too
- if (needs_reset) {
- print_info("ht reset -\r\n");
- soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn);
- }
-
- allow_all_aps_stop(bsp_apicid);
-
- //It's the time to set ctrl in sysinfo now;
- fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
-
- enable_smbus();
-
-#if 0
- dump_smbus_registers();
-#endif
-
- memreset_setup();
-
- //do we need apci timer, tsc...., only debug need it for better output
- /* all ap stopped? */
- init_timer(); // Need to use TMICT to synconize FID/VID
- sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
-
-
-#if 0
- dump_pci_devices();
-#endif
-
- post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
-
-}
-#endif
+++ /dev/null
-extern struct chip_operations mainboard_Iwill_dk8_htx_ops;
-
-struct mainboard_Iwill_dk8_htx_config {
-// int fixup_scsi;
-// int fixup_vga;
-};
+++ /dev/null
-entries
-
-#start-bit length config config-ID name
-#0 8 r 0 seconds
-#8 8 r 0 alarm_seconds
-#16 8 r 0 minutes
-#24 8 r 0 alarm_minutes
-#32 8 r 0 hours
-#40 8 r 0 alarm_hours
-#48 8 r 0 day_of_week
-#56 8 r 0 day_of_month
-#64 8 r 0 month
-#72 8 r 0 year
-#80 4 r 0 rate_select
-#84 3 r 0 REF_Clock
-#87 1 r 0 UIP
-#88 1 r 0 auto_switch_DST
-#89 1 r 0 24_hour_mode
-#90 1 r 0 binary_values_enable
-#91 1 r 0 square-wave_out_enable
-#92 1 r 0 update_finished_enable
-#93 1 r 0 alarm_interrupt_enable
-#94 1 r 0 periodic_interrupt_enable
-#95 1 r 0 disable_clock_updates
-#96 288 r 0 temporary_filler
-0 384 r 0 reserved_memory
-384 1 e 4 boot_option
-385 1 e 4 last_boot
-386 1 e 1 ECC_memory
-388 4 r 0 reboot_bits
-392 3 e 5 baud_rate
-395 1 e 1 hw_scrubber
-396 1 e 1 interleave_chip_selects
-397 2 e 8 max_mem_clock
-399 1 e 2 dual_core
-400 1 e 1 power_on_after_fail
-412 4 e 6 debug_level
-416 4 e 7 boot_first
-420 4 e 7 boot_second
-424 4 e 7 boot_third
-428 4 h 0 boot_index
-432 8 h 0 boot_countdown
-440 4 e 9 slow_cpu
-444 1 e 1 nmi
-445 1 e 1 iommu
-728 256 h 0 user_data
-984 16 h 0 check_sum
-# Reserve the extended AMD configuration registers
-1000 24 r 0 reserved_memory
-
-
-
-enumerations
-
-#ID value text
-1 0 Disable
-1 1 Enable
-2 0 Enable
-2 1 Disable
-4 0 Fallback
-4 1 Normal
-5 0 115200
-5 1 57600
-5 2 38400
-5 3 19200
-5 4 9600
-5 5 4800
-5 6 2400
-5 7 1200
-6 6 Notice
-6 7 Info
-6 8 Debug
-6 9 Spew
-7 0 Network
-7 1 HDD
-7 2 Floppy
-7 8 Fallback_Network
-7 9 Fallback_HDD
-7 10 Fallback_Floppy
-#7 3 ROM
-8 0 400Mhz
-8 1 333Mhz
-8 2 266Mhz
-8 3 200Mhz
-9 0 off
-9 1 87.5%
-9 2 75.0%
-9 3 62.5%
-9 4 50.0%
-9 5 37.5%
-9 6 25.0%
-9 7 12.5%
-
-checksums
-
-checksum 392 983 984
-
-
+++ /dev/null
-/*
- * Copyright 2005 AMD
- */
-//AMD8111
- Name (APIC, Package (0x04)
- {
- Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x10},// 0x0004ffff : assusme 8131 is present
- Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x11},
- Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x12},
- Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x13}
- })
-
- Name (PICM, Package (0x04)
- {
- Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI0.LNKA, 0x00},
- Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI0.LNKB, 0x00},
- Package (0x04) { 0x0004FFFF, 0x02, \_SB.PCI0.LNKC, 0x00},
- Package (0x04) { 0x0004FFFF, 0x03, \_SB.PCI0.LNKD, 0x00}
- })
-
- Name (DNCG, Ones)
-
- Method (_PRT, 0, NotSerialized)
- {
- If (LEqual (^DNCG, Ones)) {
- Store (DADD(\_SB.PCI0.SBDN, 0x0001ffff), Local0)
- // Update the Device Number according to SBDN
- Store(Local0, Index (DeRefOf (Index (PICM, 0)), 0))
- Store(Local0, Index (DeRefOf (Index (PICM, 1)), 0))
- Store(Local0, Index (DeRefOf (Index (PICM, 2)), 0))
- Store(Local0, Index (DeRefOf (Index (PICM, 3)), 0))
-
- Store(Local0, Index (DeRefOf (Index (APIC, 0)), 0))
- Store(Local0, Index (DeRefOf (Index (APIC, 1)), 0))
- Store(Local0, Index (DeRefOf (Index (APIC, 2)), 0))
- Store(Local0, Index (DeRefOf (Index (APIC, 3)), 0))
-
- Store (0x00, ^DNCG)
-
- }
-
- If (LNot (PICF)) {
- Return (PICM)
- }
- Else {
- Return (APIC)
- }
- }
-
- Device (SBC3)
- {
- /* acpi smbus it should be 0x00040003 if 8131 present */
- Method (_ADR, 0, NotSerialized)
- {
- Return (DADD(\_SB.PCI0.SBDN, 0x00010003))
- }
- OperationRegion (PIRQ, PCI_Config, 0x56, 0x02)
- Field (PIRQ, ByteAcc, Lock, Preserve)
- {
- PIBA, 8,
- PIDC, 8
- }
-/*
- OperationRegion (TS3_, PCI_Config, 0xC4, 0x02)
- Field (TS3_, DWordAcc, NoLock, Preserve)
- {
- PTS3, 16
- }
-*/
- }
-
- Device (HPET)
- {
- Name (HPT, 0x00)
- Name (_HID, EisaId ("PNP0103"))
- Name (_UID, 0x00)
- Method (_STA, 0, NotSerialized)
- {
- Return (0x0F)
- }
-
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUF0, ResourceTemplate ()
- {
- Memory32Fixed (ReadWrite, 0xFED00000, 0x00000400)
- })
- Return (BUF0)
- }
- }
-
- Include ("amd8111_pic.asl")
-
- Include ("amd8111_isa.asl")
-
- Device (TP2P)
- {
- /* 8111 P2P and it should 0x00030000 when 8131 present*/
- Method (_ADR, 0, NotSerialized)
- {
- Return (DADD(\_SB.PCI0.SBDN, 0x00000000))
- }
-
- Method (_PRW, 0, NotSerialized)
- {
- If (CondRefOf (\_S3, Local0)) { Return (Package (0x02) { 0x08, 0x03 }) }
- Else { Return (Package (0x02) { 0x08, 0x01 }) }
- }
-
- Device (USB0)
- {
- Name (_ADR, 0x00000000)
- Method (_PRW, 0, NotSerialized)
- {
- If (CondRefOf (\_S3, Local0)) { Return (Package (0x02) { 0x0F, 0x03 }) }
- Else { Return (Package (0x02) { 0x0F, 0x01 }) }
- }
- }
-
- Device (USB1)
- {
- Name (_ADR, 0x00000001)
- Method (_PRW, 0, NotSerialized)
- {
- If (CondRefOf (\_S3, Local0)) { Return (Package (0x02) { 0x0F, 0x03 }) }
- Else { Return (Package (0x02) { 0x0F, 0x01 }) }
- }
- }
-
- Name (APIC, Package (0x0C)
- {
- Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x10 }, //USB
- Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x11 },
- Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x12 },
- Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x13 },
-
- Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x10 }, //Slot 6
- Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x11 },
- Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x12 },
- Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x13 },
-
- Package (0x04) { 0x0005FFFF, 0x00, 0x00, 0x11 }, //Slot 5
- Package (0x04) { 0x0005FFFF, 0x01, 0x00, 0x12 },
- Package (0x04) { 0x0005FFFF, 0x02, 0x00, 0x13 },
- Package (0x04) { 0x0005FFFF, 0x03, 0x00, 0x10 }
- })
-
- Name (PICM, Package (0x0C)
- {
- Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 }, //USB
- Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 },
-
- Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 }, //Slot 6
- Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
- Package (0x04) { 0x0004FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
- Package (0x04) { 0x0004FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 },
-
- Package (0x04) { 0x0005FFFF, 0x00, \_SB.PCI0.LNKB, 0x00 }, //Slot 5
- Package (0x04) { 0x0005FFFF, 0x01, \_SB.PCI0.LNKC, 0x00 },
- Package (0x04) { 0x0005FFFF, 0x02, \_SB.PCI0.LNKD, 0x00 },
- Package (0x04) { 0x0005FFFF, 0x03, \_SB.PCI0.LNKA, 0x00 }
- })
-
- Method (_PRT, 0, NotSerialized)
- {
- If (LNot (PICF)) { Return (PICM) }
- Else { Return (APIC) }
- }
- }
-
+++ /dev/null
-/*
- * Copyright 2005 AMD
- */
-//AMD8111 isa
-
- Device (ISA)
- {
- /* lpc 0x00040000 */
- Method (_ADR, 0, NotSerialized)
- {
- Return (DADD(\_SB.PCI0.SBDN, 0x00010000))
- }
-
- OperationRegion (PIRY, PCI_Config, 0x51, 0x02) // LPC Decode Registers
- Field (PIRY, ByteAcc, NoLock, Preserve)
- {
- Z000, 2, // Parallel Port Range
- , 1,
- ECP, 1, // ECP Enable
- FDC1, 1, // Floppy Drive Controller 1
- FDC2, 1, // Floppy Drive Controller 2
- Offset (0x01),
- Z001, 3, // Serial Port A Range
- SAEN, 1, // Serial Post A Enabled
- Z002, 3, // Serial Port B Range
- SBEN, 1 // Serial Post B Enabled
- }
-
- Device (PIC)
- {
- Name (_HID, EisaId ("PNP0000"))
- Name (_CRS, ResourceTemplate ()
- {
- IO (Decode16, 0x0020, 0x0020, 0x01, 0x02)
- IO (Decode16, 0x00A0, 0x00A0, 0x01, 0x02)
- IRQ (Edge, ActiveHigh, Exclusive) {2}
- })
- }
-
- Device (DMA1)
- {
- Name (_HID, EisaId ("PNP0200"))
- Name (_CRS, ResourceTemplate ()
- {
- IO (Decode16, 0x0000, 0x0000, 0x01, 0x10)
- IO (Decode16, 0x0080, 0x0080, 0x01, 0x10)
- IO (Decode16, 0x00C0, 0x00C0, 0x01, 0x20)
- DMA (Compatibility, NotBusMaster, Transfer16) {4}
- })
- }
-
- Device (TMR)
- {
- Name (_HID, EisaId ("PNP0100"))
- Name (_CRS, ResourceTemplate ()
- {
- IO (Decode16, 0x0040, 0x0040, 0x01, 0x04)
- IRQ (Edge, ActiveHigh, Exclusive) {0}
- })
- }
-
- Device (RTC)
- {
- Name (_HID, EisaId ("PNP0B00"))
- Name (_CRS, ResourceTemplate ()
- {
- IO (Decode16, 0x0070, 0x0070, 0x01, 0x06)
- IRQ (Edge, ActiveHigh, Exclusive) {8}
- })
- }
-
- Device (SPKR)
- {
- Name (_HID, EisaId ("PNP0800"))
- Name (_CRS, ResourceTemplate ()
- {
- IO (Decode16, 0x0061, 0x0061, 0x01, 0x01)
- })
- }
-
- Device (COPR)
- {
- Name (_HID, EisaId ("PNP0C04"))
- Name (_CRS, ResourceTemplate ()
- {
- IO (Decode16, 0x00F0, 0x00F0, 0x01, 0x10)
- IRQ (Edge, ActiveHigh, Exclusive) {13}
- })
- }
-
- Device (SYSR)
- {
- Name (_HID, EisaId ("PNP0C02"))
- Name (_UID, 0x00)
- Name (SYR1, ResourceTemplate ()
- {
- IO (Decode16, 0x04D0, 0x04D0, 0x01, 0x02) //wrh092302 - added to report Thor NVRAM
- IO (Decode16, 0x1100, 0x117F, 0x01, 0x80) //wrh092302 - added to report Thor NVRAM
- IO (Decode16, 0x1180, 0x11FF, 0x01, 0x80)
- IO (Decode16, 0x0010, 0x0010, 0x01, 0x10)
- IO (Decode16, 0x0022, 0x0022, 0x01, 0x1E)
- IO (Decode16, 0x0044, 0x0044, 0x01, 0x1C)
- IO (Decode16, 0x0062, 0x0062, 0x01, 0x02)
- IO (Decode16, 0x0065, 0x0065, 0x01, 0x0B)
- IO (Decode16, 0x0076, 0x0076, 0x01, 0x0A)
- IO (Decode16, 0x0090, 0x0090, 0x01, 0x10)
- IO (Decode16, 0x00A2, 0x00A2, 0x01, 0x1E)
- IO (Decode16, 0x00E0, 0x00E0, 0x01, 0x10)
- IO (Decode16, 0x0B78, 0x0B78, 0x01, 0x04) // Added this to remove ACPI Unrepoted IO Error
- IO (Decode16, 0x0190, 0x0190, 0x01, 0x04) // Added this to remove ACPI Unrepoted IO Error
- })
- Method (_CRS, 0, NotSerialized)
- {
- Return (SYR1)
- }
- }
-
- Device (MEM)
- {
- Name (_HID, EisaId ("PNP0C02"))
- Name (_UID, 0x01)
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUF0, ResourceTemplate ()
- {
- Memory32Fixed (ReadWrite, 0x000E0000, 0x00020000) // BIOS E4000-FFFFF
- Memory32Fixed (ReadWrite, 0x000C0000, 0x00000000) // video BIOS c0000-c8404
- Memory32Fixed (ReadWrite, 0xFEC00000, 0x00001000) // I/O APIC
- Memory32Fixed (ReadWrite, 0xFFC00000, 0x00380000) // LPC forwarded, 4 MB w/ROM
- Memory32Fixed (ReadWrite, 0xFEE00000, 0x00001000) // Local APIC
- Memory32Fixed (ReadWrite, 0xFFF80000, 0x00080000) // Overlay BIOS
- Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) // Overlay BIOS
- Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) // Overlay BIOS
- Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) //Overlay BIOS
- Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) //Overlay BIOS
- })
- // Read the Video Memory length
- CreateDWordField (BUF0, 0x14, CLEN)
- CreateDWordField (BUF0, 0x10, CBAS)
-
- ShiftLeft (VGA1, 0x09, Local0)
- Store (Local0, CLEN)
-
- Return (BUF0)
- }
- }
-
- Device (PS2M)
- {
- Name (_HID, EisaId ("PNP0F13"))
- Name (_CRS, ResourceTemplate ()
- {
- IRQNoFlags () {12}
- })
- Method (_STA, 0, NotSerialized)
- {
- And (FLG0, 0x04, Local0)
- If (LEqual (Local0, 0x04)) { Return (0x0F) }
- Else { Return (0x00) }
- }
- }
-
- Device (PS2K)
- {
- Name (_HID, EisaId ("PNP0303"))
- Name (_CRS, ResourceTemplate ()
- {
- IO (Decode16, 0x0060, 0x0060, 0x01, 0x01)
- IO (Decode16, 0x0064, 0x0064, 0x01, 0x01)
- IRQNoFlags () {1}
- })
- }
- Include ("superio.asl")
-
- }
-
+++ /dev/null
-/*
- * Copyright 2005 AMD
- */
-//AMD8111 pic LNKA B C D
-
- Device (LNKA)
- {
- Name (_HID, EisaId ("PNP0C0F"))
- Name (_UID, 0x01)
- Method (_STA, 0, NotSerialized)
- {
- And (\_SB.PCI0.SBC3.PIBA, 0x0F, Local0)
- If (LEqual (Local0, 0x00)) { Return (0x09) } //Disabled
- Else { Return (0x0B) } //Enabled
- }
-
- Method (_PRS, 0, NotSerialized)
- {
- Name (BUFA, ResourceTemplate ()
- {
- IRQ (Level, ActiveLow, Shared) {3,5,10,11}
- })
- Return (BUFA)
- }
-
- Method (_DIS, 0, NotSerialized)
- {
- Store (0x01, Local3)
- And (\_SB.PCI0.SBC3.PIBA, 0x0F, Local1)
- Store (Local1, Local2)
- If (LGreater (Local1, 0x07))
- {
- Subtract (Local1, 0x08, Local1)
- }
-
- ShiftLeft (Local3, Local1, Local3)
- Not (Local3, Local3)
- And (\_SB.PCI0.SBC3.PIBA, 0xF0, \_SB.PCI0.SBC3.PIBA)
- }
-
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUFA, ResourceTemplate ()
- {
- IRQ (Level, ActiveLow, Shared) {}
- })
- CreateByteField (BUFA, 0x01, IRA1)
- CreateByteField (BUFA, 0x02, IRA2)
- Store (0x00, Local3)
- Store (0x00, Local4)
- And (\_SB.PCI0.SBC3.PIBA, 0x0F, Local1)
- If (LNot (LEqual (Local1, 0x00)))
- { // Routing enable
- If (LGreater (Local1, 0x07))
- {
- Subtract (Local1, 0x08, Local2)
- ShiftLeft (One, Local2, Local4)
- }
- Else
- {
- If (LGreater (Local1, 0x00))
- {
- ShiftLeft (One, Local1, Local3)
- }
- }
-
- Store (Local3, IRA1)
- Store (Local4, IRA2)
- }
-
- Return (BUFA)
- }
-
- Method (_SRS, 1, NotSerialized)
- {
- CreateByteField (Arg0, 0x01, IRA1)
- CreateByteField (Arg0, 0x02, IRA2)
- ShiftLeft (IRA2, 0x08, Local0)
- Or (Local0, IRA1, Local0)
- Store (0x00, Local1)
- ShiftRight (Local0, 0x01, Local0)
- While (LGreater (Local0, 0x00))
- {
- Increment (Local1)
- ShiftRight (Local0, 0x01, Local0)
- }
-
- And (\_SB.PCI0.SBC3.PIBA, 0xF0, \_SB.PCI0.SBC3.PIBA)
- Or (\_SB.PCI0.SBC3.PIBA, Local1, \_SB.PCI0.SBC3.PIBA)
- }
- }
-
- Device (LNKB)
- {
- Name (_HID, EisaId ("PNP0C0F"))
- Name (_UID, 0x02)
- Method (_STA, 0, NotSerialized)
- {
- And (\_SB.PCI0.SBC3.PIBA, 0xF0, Local0)
- If (LEqual (Local0, 0x00)) { Return (0x09) }
- Else { Return (0x0B) }
- }
-
- Method (_PRS, 0, NotSerialized)
- {
- Name (BUFB, ResourceTemplate ()
- {
- IRQ (Level, ActiveLow, Shared) {3,5,10,11}
- })
- Return (BUFB)
- }
-
- Method (_DIS, 0, NotSerialized)
- {
- Store (0x01, Local3)
- And (\_SB.PCI0.SBC3.PIBA, 0xF0, Local1)
- ShiftRight (Local1, 0x04, Local1)
- Store (Local1, Local2)
- If (LGreater (Local1, 0x07))
- {
- Subtract (Local1, 0x08, Local1)
- }
-
- ShiftLeft (Local3, Local1, Local3)
- Not (Local3, Local3)
- And (\_SB.PCI0.SBC3.PIBA, 0x0F, \_SB.PCI0.SBC3.PIBA)
- }
-
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUFB, ResourceTemplate ()
- {
- IRQ (Level, ActiveLow, Shared) {}
- })
- CreateByteField (BUFB, 0x01, IRB1)
- CreateByteField (BUFB, 0x02, IRB2)
- Store (0x00, Local3)
- Store (0x00, Local4)
- And (\_SB.PCI0.SBC3.PIBA, 0xF0, Local1)
- ShiftRight (Local1, 0x04, Local1)
- If (LNot (LEqual (Local1, 0x00)))
- {
- If (LGreater (Local1, 0x07))
- {
- Subtract (Local1, 0x08, Local2)
- ShiftLeft (One, Local2, Local4)
- }
- Else
- {
- If (LGreater (Local1, 0x00))
- {
- ShiftLeft (One, Local1, Local3)
- }
- }
-
- Store (Local3, IRB1)
- Store (Local4, IRB2)
- }
-
- Return (BUFB)
- }
-
- Method (_SRS, 1, NotSerialized)
- {
- CreateByteField (Arg0, 0x01, IRB1)
- CreateByteField (Arg0, 0x02, IRB2)
- ShiftLeft (IRB2, 0x08, Local0)
- Or (Local0, IRB1, Local0)
- Store (0x00, Local1)
- ShiftRight (Local0, 0x01, Local0)
- While (LGreater (Local0, 0x00))
- {
- Increment (Local1)
- ShiftRight (Local0, 0x01, Local0)
- }
-
- And (\_SB.PCI0.SBC3.PIBA, 0x0F, \_SB.PCI0.SBC3.PIBA)
- ShiftLeft (Local1, 0x04, Local1)
- Or (\_SB.PCI0.SBC3.PIBA, Local1, \_SB.PCI0.SBC3.PIBA)
- }
- }
-
- Device (LNKC)
- {
- Name (_HID, EisaId ("PNP0C0F"))
- Name (_UID, 0x03)
- Method (_STA, 0, NotSerialized)
- {
- And (\_SB.PCI0.SBC3.PIDC, 0x0F, Local0)
- If (LEqual (Local0, 0x00)) { Return (0x09) }
- Else { Return (0x0B) }
- }
-
- Method (_PRS, 0, NotSerialized)
- {
- Name (BUFA, ResourceTemplate ()
- {
- IRQ (Level, ActiveLow, Shared) {3,5,10,11}
- })
- Return (BUFA)
- }
-
- Method (_DIS, 0, NotSerialized)
- {
- Store (0x01, Local3)
- And (\_SB.PCI0.SBC3.PIDC, 0x0F, Local1)
- Store (Local1, Local2)
- If (LGreater (Local1, 0x07))
- {
- Subtract (Local1, 0x08, Local1)
- }
-
- ShiftLeft (Local3, Local1, Local3)
- Not (Local3, Local3)
- And (\_SB.PCI0.SBC3.PIDC, 0xF0, \_SB.PCI0.SBC3.PIDC)
- }
-
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUFA, ResourceTemplate ()
- {
- IRQ (Level, ActiveLow, Shared) {}
- })
- CreateByteField (BUFA, 0x01, IRA1)
- CreateByteField (BUFA, 0x02, IRA2)
- Store (0x00, Local3)
- Store (0x00, Local4)
- And (\_SB.PCI0.SBC3.PIDC, 0x0F, Local1)
- If (LNot (LEqual (Local1, 0x00)))
- {
- If (LGreater (Local1, 0x07))
- {
- Subtract (Local1, 0x08, Local2)
- ShiftLeft (One, Local2, Local4)
- }
- Else
- {
- If (LGreater (Local1, 0x00))
- {
- ShiftLeft (One, Local1, Local3)
- }
- }
-
- Store (Local3, IRA1)
- Store (Local4, IRA2)
- }
-
- Return (BUFA)
- }
-
- Method (_SRS, 1, NotSerialized)
- {
- CreateByteField (Arg0, 0x01, IRA1)
- CreateByteField (Arg0, 0x02, IRA2)
- ShiftLeft (IRA2, 0x08, Local0)
- Or (Local0, IRA1, Local0)
- Store (0x00, Local1)
- ShiftRight (Local0, 0x01, Local0)
- While (LGreater (Local0, 0x00))
- {
- Increment (Local1)
- ShiftRight (Local0, 0x01, Local0)
- }
-
- And (\_SB.PCI0.SBC3.PIDC, 0xF0, \_SB.PCI0.SBC3.PIDC)
- Or (\_SB.PCI0.SBC3.PIDC, Local1, \_SB.PCI0.SBC3.PIDC)
- }
- }
-
- Device (LNKD)
- {
- Name (_HID, EisaId ("PNP0C0F"))
- Name (_UID, 0x04)
- Method (_STA, 0, NotSerialized)
- {
- And (\_SB.PCI0.SBC3.PIDC, 0xF0, Local0)
- If (LEqual (Local0, 0x00)) { Return (0x09) }
- Else { Return (0x0B) }
- }
-
- Method (_PRS, 0, NotSerialized)
- {
- Name (BUFB, ResourceTemplate ()
- {
- IRQ (Level, ActiveLow, Shared) {3,5,10,11}
- })
- Return (BUFB)
- }
-
- Method (_DIS, 0, NotSerialized)
- {
- Store (0x01, Local3)
- And (\_SB.PCI0.SBC3.PIDC, 0xF0, Local1)
- ShiftRight (Local1, 0x04, Local1)
- Store (Local1, Local2)
- If (LGreater (Local1, 0x07))
- {
- Subtract (Local1, 0x08, Local1)
- }
-
- ShiftLeft (Local3, Local1, Local3)
- Not (Local3, Local3)
- And (\_SB.PCI0.SBC3.PIDC, 0x0F, \_SB.PCI0.SBC3.PIDC)
- }
-
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUFB, ResourceTemplate ()
- {
- IRQ (Level, ActiveLow, Shared) {}
- })
- CreateByteField (BUFB, 0x01, IRB1)
- CreateByteField (BUFB, 0x02, IRB2)
- Store (0x00, Local3)
- Store (0x00, Local4)
- And (\_SB.PCI0.SBC3.PIDC, 0xF0, Local1)
- ShiftRight (Local1, 0x04, Local1)
- If (LNot (LEqual (Local1, 0x00)))
- {
- If (LGreater (Local1, 0x07))
- {
- Subtract (Local1, 0x08, Local2)
- ShiftLeft (One, Local2, Local4)
- }
- Else
- {
- If (LGreater (Local1, 0x00))
- {
- ShiftLeft (One, Local1, Local3)
- }
- }
-
- Store (Local3, IRB1)
- Store (Local4, IRB2)
- }
-
- Return (BUFB)
- }
-
- Method (_SRS, 1, NotSerialized)
- {
- CreateByteField (Arg0, 0x01, IRB1)
- CreateByteField (Arg0, 0x02, IRB2)
- ShiftLeft (IRB2, 0x08, Local0)
- Or (Local0, IRB1, Local0)
- Store (0x00, Local1)
- ShiftRight (Local0, 0x01, Local0)
- While (LGreater (Local0, 0x00))
- {
- Increment (Local1)
- ShiftRight (Local0, 0x01, Local0)
- }
-
- And (\_SB.PCI0.SBC3.PIDC, 0x0F, \_SB.PCI0.SBC3.PIDC)
- ShiftLeft (Local1, 0x04, Local1)
- Or (\_SB.PCI0.SBC3.PIDC, Local1, \_SB.PCI0.SBC3.PIDC)
- }
- }
-
-
+++ /dev/null
-/*
- * Copyright 2005 AMD
- */
-
- Device (PG0A)
- {
- /* 8132 pcix bridge*/
- Method (_ADR, 0, NotSerialized)
- {
- Return (DADD(GHCD(HCIN, 0), 0x00000000))
- }
-
- Method (_PRW, 0, NotSerialized)
- {
- If (CondRefOf (\_S3, Local0)) { Return (Package (0x02) { 0x29, 0x03 }) }
- Else { Return (Package (0x02) { 0x29, 0x01 }) }
- }
-
- Name (APIC, Package (0x14)
- {
- // Slot 3 - PIRQ BCDA ---- verified
- Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x19 }, //Slot 3
- Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x1A },
- Package (0x04) { 0x0001FFFF, 0x02, 0x00, 0x1B },
- Package (0x04) { 0x0001FFFF, 0x03, 0x00, 0x18 },
-
- //Slot 4 - PIRQ CDAB ---- verified
- Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x1A }, //?
- Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x1B },
- Package (0x04) { 0x0002FFFF, 0x02, 0x00, 0x18 },
- Package (0x04) { 0x0002FFFF, 0x03, 0x00, 0x19 },
-
- //Onboard NIC 1 - PIRQ DABC
- Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x1B }, //?
- Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x18 },
- Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x19 },
- Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x1A },
-
- // NIC 2 - PIRQ ABCD -- verified
- Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x18 }, //?
- Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x19 },
- Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x1A },
- Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x1B },
-
- //SERIAL ATA - PIRQ BCDA
- Package (0x04) { 0x0005FFFF, 0x00, 0x00, 0x19 }, //?
- Package (0x04) { 0x0005FFFF, 0x01, 0x00, 0x1A },
- Package (0x04) { 0x0005FFFF, 0x02, 0x00, 0x1B },
- Package (0x04) { 0x0005FFFF, 0x03, 0x00, 0x18 }
- })
- Name (PICM, Package (0x14)
- {
- Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI0.LNKB, 0x00 },//Slot 3
- Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI0.LNKC, 0x00 },
- Package (0x04) { 0x0001FFFF, 0x02, \_SB.PCI0.LNKD, 0x00 },
- Package (0x04) { 0x0001FFFF, 0x03, \_SB.PCI0.LNKA, 0x00 },
-
- Package (0x04) { 0x0002FFFF, 0x00, \_SB.PCI0.LNKC, 0x00 },
- Package (0x04) { 0x0002FFFF, 0x01, \_SB.PCI0.LNKD, 0x00 },
- Package (0x04) { 0x0002FFFF, 0x02, \_SB.PCI0.LNKA, 0x00 },
- Package (0x04) { 0x0002FFFF, 0x03, \_SB.PCI0.LNKB, 0x00 },
-
- Package (0x04) { 0x0003FFFF, 0x00, \_SB.PCI0.LNKD, 0x00 },
- Package (0x04) { 0x0003FFFF, 0x01, \_SB.PCI0.LNKA, 0x00 },
- Package (0x04) { 0x0003FFFF, 0x02, \_SB.PCI0.LNKB, 0x00 },
- Package (0x04) { 0x0003FFFF, 0x03, \_SB.PCI0.LNKC, 0x00 },
-
- Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },
- Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
- Package (0x04) { 0x0004FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
- Package (0x04) { 0x0004FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 },
-
- Package (0x04) { 0x0005FFFF, 0x00, \_SB.PCI0.LNKB, 0x00 },
- Package (0x04) { 0x0005FFFF, 0x01, \_SB.PCI0.LNKC, 0x00 },
- Package (0x04) { 0x0005FFFF, 0x02, \_SB.PCI0.LNKD, 0x00 },
- Package (0x04) { 0x0005FFFF, 0x03, \_SB.PCI0.LNKA, 0x00 }
- })
- Method (_PRT, 0, NotSerialized)
- {
- If (LNot (PICF)) { Return (PICM) }
- Else { Return (APIC) }
- }
- }
-
- Device (PG0B)
- {
- /* 8132 pcix bridge 2 */
- Method (_ADR, 0, NotSerialized)
- {
- Return (DADD(GHCD(HCIN, 0), 0x00010000))
- }
-
- Method (_PRW, 0, NotSerialized)
- {
- If (CondRefOf (\_S3, Local0)) { Return (Package (0x02) { 0x22, 0x03 }) }
- Else { Return (Package (0x02) { 0x22, 0x01 }) }
- }
-
- Name (APIC, Package (0x04)
- {
- // Slot A - PIRQ CDAB -- verfied
- Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x1E },// Slot 2
- Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x1F },
- Package (0x04) { 0x0002FFFF, 0x02, 0x00, 0x1C },
- Package (0x04) { 0x0002FFFF, 0x03, 0x00, 0x1D }
- })
- Name (PICM, Package (0x04)
- {
- Package (0x04) { 0x0002FFFF, 0x00, \_SB.PCI0.LNKC, 0x00 },//Slot 2
- Package (0x04) { 0x0002FFFF, 0x01, \_SB.PCI0.LNKD, 0x00 },
- Package (0x04) { 0x0002FFFF, 0x02, \_SB.PCI0.LNKA, 0x00 },
- Package (0x04) { 0x0002FFFF, 0x03, \_SB.PCI0.LNKB, 0x00 }
- })
- Method (_PRT, 0, NotSerialized)
- {
- If (LNot (PICF)) { Return (PICM) }
- Else { Return (APIC) }
- }
- }
+++ /dev/null
-/*
- * Copyright 2005 AMD
- */
-
- Device (PG0A)
- {
- /* 8132 pcix bridge*/
- Method (_ADR, 0, NotSerialized)
- {
- Return (DADD(GHCD(HCIN, 0), 0x00000000))
- }
-
- Method (_PRW, 0, NotSerialized)
- {
- If (CondRefOf (\_S3, Local0)) { Return (Package (0x02) { 0x29, 0x03 }) }
- Else { Return (Package (0x02) { 0x29, 0x01 }) }
- }
-
- Name (APIC, Package (0x04)
- {
- // Slot A - PIRQ BCDA
- Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x0018 }, //Slot 2
- Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x0019 },
- Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x001A },
- Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x001B },
-
- })
- Name (PICM, Package (0x04)
- {
- Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },//Slot 2
- Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 },
- })
-
- Name (DNCG, Ones)
-
- Method (_PRT, 0, NotSerialized)
- {
- If (LEqual (^DNCG, Ones)) {
- Multiply (HCIN, 0x0008, Local2) // GSI for 8132 is 4 so we get 8
- Store (0x00, Local1)
- While (LLess (Local1, 0x04))
- {
- // Update the GSI according to HCIN
- Store(DeRefOf(Index (DeRefOf (Index (APIC, Local1)), 3)), Local0)
- Add(Local2, Local0, Local0)
- Store(Local0, Index (DeRefOf (Index (APIC, Local1)), 3))
- Increment (Local1)
- }
-
- Store (0x00, ^DNCG)
-
- }
-
- If (LNot (PICF)) { Return (PICM) }
- Else { Return (APIC) }
- }
- }
-
- Device (PG0B)
- {
- /* 8132 pcix bridge 2 */
- Method (_ADR, 0, NotSerialized)
- {
- Return (DADD(GHCD(HCIN, 0), 0x00010000))
- }
-
- Method (_PRW, 0, NotSerialized)
- {
- If (CondRefOf (\_S3, Local0)) { Return (Package (0x02) { 0x22, 0x03 }) }
- Else { Return (Package (0x02) { 0x22, 0x01 }) }
- }
-
- Name (APIC, Package (0x04)
- {
- // Slot A - PIRQ ABCD
- Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x001F },// Slot 1
- Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x0020 },
- Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x0021 },
- Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x0022 }
- })
- Name (PICM, Package (0x04)
- {
- Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },//Slot 1
- Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 }
- })
-
- Name (DNCG, Ones)
-
- Method (_PRT, 0, NotSerialized)
- {
- If (LEqual (^DNCG, Ones)) {
- Multiply (HCIN, 0x0008, Local2) // GSI for 8132 is 4 so we get 8
- Store (0x00, Local1)
- While (LLess (Local1, 0x04))
- {
- // Update the GSI according to HCIN
- Store(DeRefOf(Index (DeRefOf (Index (APIC, Local1)), 3)), Local0)
- Add(Local2, Local0, Local0)
- Store(Local0, Index (DeRefOf (Index (APIC, Local1)), 3))
- Increment (Local1)
- }
-
- Store (0x00, ^DNCG)
-
- }
-
- If (LNot (PICF)) { Return (PICM) }
- Else { Return (APIC) }
- }
- }
+++ /dev/null
-/*
- * Copyright 2005 AMD
- */
-
- Device (PG0A)
- {
- /* 8132 pcix bridge*/
- Method (_ADR, 0, NotSerialized)
- {
- Return (DADD(GHCD(HCIN, 0), 0x00000000))
- }
-
- Method (_PRW, 0, NotSerialized)
- {
- If (CondRefOf (\_S3, Local0)) { Return (Package (0x02) { 0x29, 0x03 }) }
- Else { Return (Package (0x02) { 0x29, 0x01 }) }
- }
-
- Name (APIC, Package (0x04)
- {
- // Slot A - PIRQ BCDA
- Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x0018 }, //Slot 2
- Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x0019 },
- Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x001A },
- Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x001B },
-
- })
- Name (PICM, Package (0x04)
- {
- Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },//Slot 2
- Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 },
- })
-
- Name (DNCG, Ones)
-
- Method (_PRT, 0, NotSerialized)
- {
- If (LEqual (^DNCG, Ones)) {
- Multiply (HCIN, 0x000e, Local2) // GSI for 8132 is 7 so we get 14
- Store (0x00, Local1)
- While (LLess (Local1, 0x04))
- {
- // Update the GSI according to HCIN
- Store(DeRefOf(Index (DeRefOf (Index (APIC, Local1)), 3)), Local0)
- Add(Local2, Local0, Local0)
- Store(Local0, Index (DeRefOf (Index (APIC, Local1)), 3))
- Increment (Local1)
- }
-
- Store (0x00, ^DNCG)
-
- }
-
- If (LNot (PICF)) { Return (PICM) }
- Else { Return (APIC) }
- }
- }
-
- Device (PG0B)
- {
- /* 8132 pcix bridge 2 */
- Method (_ADR, 0, NotSerialized)
- {
- Return (DADD(GHCD(HCIN, 0), 0x00010000))
- }
-
- Method (_PRW, 0, NotSerialized)
- {
- If (CondRefOf (\_S3, Local0)) { Return (Package (0x02) { 0x22, 0x03 }) }
- Else { Return (Package (0x02) { 0x22, 0x01 }) }
- }
-
- Name (APIC, Package (0x04)
- {
- // Slot A - PIRQ ABCD
- Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x001F },// Slot 1
- Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x0020 },
- Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x0021 },
- Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x0022 }
- })
- Name (PICM, Package (0x04)
- {
- Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },//Slot 1
- Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 }
- })
-
- Name (DNCG, Ones)
-
- Method (_PRT, 0, NotSerialized)
- {
- If (LEqual (^DNCG, Ones)) {
- Multiply (HCIN, 0x000e, Local2) // GSI for 8132 is 7 so we get 14
- Store (0x00, Local1)
- While (LLess (Local1, 0x04))
- {
- // Update the GSI according to HCIN
- Store(DeRefOf(Index (DeRefOf (Index (APIC, Local1)), 3)), Local0)
- Add(Local2, Local0, Local0)
- Store(Local0, Index (DeRefOf (Index (APIC, Local1)), 3))
- Increment (Local1)
- }
-
- Store (0x00, ^DNCG)
-
- }
-
- If (LNot (PICF)) { Return (PICM) }
- Else { Return (APIC) }
- }
- }
+++ /dev/null
-// AMD8151
- Device (AGPB)
- {
- Method (_ADR, 0, NotSerialized)
- {
- Return (DADD(GHCD(HCIN, 0), 0x00010000))
- }
-
- Name (APIC, Package (0x04)
- {
- Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x10 },
- Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x11 },
- Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x12 },
- Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x13 }
- })
- Name (PICM, Package (0x04)
- {
- Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
- Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 }
- })
- Method (_PRT, 0, NotSerialized)
- {
- If (LNot (PICF)) { Return (PICM) }
- Else { Return (APIC) }
- }
- }
-
+++ /dev/null
-/*
- * Copyright 2005 AMD
- */
-
-//AMD k8 util for BUSB and res range
-
- Scope (\_SB)
- {
-
- Name (OSTB, Ones)
- Method (OSTP, 0, NotSerialized)
- {
- If (LEqual (^OSTB, Ones))
- {
- Store (0x00, ^OSTB)
- }
-
- Return (^OSTB)
- }
-
- Method (SEQL, 2, Serialized)
- {
- Store (SizeOf (Arg0), Local0)
- Store (SizeOf (Arg1), Local1)
- If (LNot (LEqual (Local0, Local1))) { Return (Zero) }
-
- Name (BUF0, Buffer (Local0) {})
- Store (Arg0, BUF0)
- Name (BUF1, Buffer (Local0) {})
- Store (Arg1, BUF1)
- Store (Zero, Local2)
- While (LLess (Local2, Local0))
- {
- Store (DerefOf (Index (BUF0, Local2)), Local3)
- Store (DerefOf (Index (BUF1, Local2)), Local4)
- If (LNot (LEqual (Local3, Local4))) { Return (Zero) }
-
- Increment (Local2)
- }
-
- Return (One)
- }
-
-
- Method (DADD, 2, NotSerialized)
- {
- Store( Arg1, Local0)
- Store( Arg0, Local1)
- Add( ShiftLeft(Local1,16), Local0, Local0)
- Return (Local0)
- }
-
-
- Method (GHCE, 1, NotSerialized) // check if the HC enabled
- {
- Store (DerefOf (Index (\_SB.PCI0.HCLK, Arg0)), Local1)
- if(LEqual ( And(Local1, 0x01), 0x01)) { Return (0x0F) }
- Else { Return (0x00) }
- }
-
- Method (GHCN, 1, NotSerialized) // get the node num for the HC
- {
- Store (0x00, Local0)
- Store (DerefOf (Index (\_SB.PCI0.HCLK, Arg0)), Local1)
- Store (ShiftRight( And (Local1, 0xf0), 0x04), Local0)
- Return (Local0)
- }
-
- Method (GHCL, 1, NotSerialized) // get the link num on node for the HC
- {
- Store (0x00, Local0)
- Store (DerefOf (Index (\_SB.PCI0.HCLK, Arg0)), Local1)
- Store (ShiftRight( And (Local1, 0xf00), 0x08), Local0)
- Return (Local0)
- }
-
- Method (GHCD, 2, NotSerialized) // get the unit id base for the HT device in HC
- {
- Store (0x00, Local0)
- Store (DerefOf (Index (\_SB.PCI0.HCDN, Arg0)), Local1)
- Store (Arg1, Local2) // Arg1 could be 3, 2, 1, 0
- Multiply (Local2, 0x08, Local2) // change to 24, 16, 8, 0
- Store (And (ShiftRight( Local1, Local2), 0xff), Local0)
- Return (Local0)
- }
-
- Method (GBUS, 2, NotSerialized)
- {
- Store (0x00, Local0)
- While (LLess (Local0, 0x04))
- {
- Store (DerefOf (Index (\_SB.PCI0.BUSN, Local0)), Local1)
- If (LEqual (And (Local1, 0x03), 0x03))
- {
- If (LEqual (Arg0, ShiftRight (And (Local1, 0x70), 0x04)))
- {
- If (LOr (LEqual (Arg1, 0xFF), LEqual (Arg1, ShiftRight (And (Local1, 0x0300), 0x08))))
- {
- Return (ShiftRight (And (Local1, 0x00FF0000), 0x10))
- }
- }
- }
-
- Increment (Local0)
- }
-
- Return (0x00)
- }
-
- Method (GWBN, 2, NotSerialized)
- {
- Name (BUF0, ResourceTemplate ()
- {
- WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
- 0x0000, // Address Space Granularity
- 0x0000, // Address Range Minimum
- 0x0000, // Address Range Maximum
- 0x0000, // Address Translation Offset
- 0x0000,,,)
- })
- CreateWordField (BUF0, 0x08, BMIN)
- CreateWordField (BUF0, 0x0A, BMAX)
- CreateWordField (BUF0, 0x0E, BLEN)
- Store (0x00, Local0)
- While (LLess (Local0, 0x04))
- {
- Store (DerefOf (Index (\_SB.PCI0.BUSN, Local0)), Local1)
- If (LEqual (And (Local1, 0x03), 0x03))
- {
- If (LEqual (Arg0, ShiftRight (And (Local1, 0x70), 0x04)))
- {
- If (LOr (LEqual (Arg1, 0xFF), LEqual (Arg1, ShiftRight (And (Local1, 0x0300), 0x08))))
- {
- Store (ShiftRight (And (Local1, 0x00FF0000), 0x10), BMIN)
- Store (ShiftRight (Local1, 0x18), BMAX)
- Subtract (BMAX, BMIN, BLEN)
- Increment (BLEN)
- Return (RTAG (BUF0))
- }
- }
- }
-
- Increment (Local0)
- }
-
- Return (RTAG (BUF0))
- }
-
- Method (GMEM, 2, NotSerialized)
- {
- Name (BUF0, ResourceTemplate ()
- {
- DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
- 0x00000000, // Address Space Granularity
- 0x00000000, // Address Range Minimum
- 0x00000000, // Address Range Maximum
- 0x00000000, // Address Translation Offset
- 0x00000000,,,
- , AddressRangeMemory, TypeStatic)
- })
- CreateDWordField (BUF0, 0x0A, MMIN)
- CreateDWordField (BUF0, 0x0E, MMAX)
- CreateDWordField (BUF0, 0x16, MLEN)
- Store (0x00, Local0)
- Store (0x00, Local4)
- Store (0x00, Local3)
- While (LLess (Local0, 0x10))
- {
- Store (DerefOf (Index (\_SB.PCI0.MMIO, Local0)), Local1)
- Increment (Local0)
- Store (DerefOf (Index (\_SB.PCI0.MMIO, Local0)), Local2)
- If (LEqual (And (Local1, 0x03), 0x03))
- {
- If (LEqual (Arg0, And (Local2, 0x07)))
- {
- If (LOr (LEqual (Arg1, 0xFF), LEqual (Arg1, ShiftRight (And (Local2, 0x30), 0x04))))
- {
- Store (ShiftLeft (And (Local1, 0xFFFFFF00), 0x08), MMIN)
- Store (ShiftLeft (And (Local2, 0xFFFFFF00), 0x08), MMAX)
- Or (MMAX, 0xFFFF, MMAX)
- Subtract (MMAX, MMIN, MLEN)
-
- If (Local4)
- {
- Concatenate (RTAG (BUF0), Local3, Local5)
- Store (Local5, Local3)
- }
- Else
- {
- If (LOr (LAnd (LEqual (Arg1, 0xFF), LEqual (Arg0, 0x00)), LEqual (Arg1, \_SB.PCI0.SBLK)))
- {
- Store (\_SB.PCI0.TOM1, MMIN)
- Subtract (MMAX, MMIN, MLEN)
- Increment (MLEN)
- }
-
- Store (RTAG (BUF0), Local3)
- }
-
- Increment (Local4)
- }
- }
- }
-
- Increment (Local0)
- }
-
- If (LNot (Local4))
- {
- Store (BUF0, Local3)
- }
-
- Return (Local3)
- }
-
- Method (GIOR, 2, NotSerialized)
- {
- Name (BUF0, ResourceTemplate ()
- {
- DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
- 0x00000000, // Address Space Granularity
- 0x00000000, // Address Range Minimum
- 0x00000000, // Address Range Maximum
- 0x00000000, // Address Translation Offset
- 0x00000000,,,
- , TypeStatic)
- })
- CreateDWordField (BUF0, 0x0A, PMIN)
- CreateDWordField (BUF0, 0x0E, PMAX)
- CreateDWordField (BUF0, 0x16, PLEN)
- Store (0x00, Local0)
- Store (0x00, Local4)
- Store (0x00, Local3)
- While (LLess (Local0, 0x08))
- {
- Store (DerefOf (Index (\_SB.PCI0.PCIO, Local0)), Local1)
- Increment (Local0)
- Store (DerefOf (Index (\_SB.PCI0.PCIO, Local0)), Local2)
- If (LEqual (And (Local1, 0x03), 0x03))
- {
- If (LEqual (Arg0, And (Local2, 0x07)))
- {
- If (LOr (LEqual (Arg1, 0xFF), LEqual (Arg1, ShiftRight (And (Local2, 0x30), 0x04))))
- {
- Store (And (Local1, 0x01FFF000), PMIN)
- Store (And (Local2, 0x01FFF000), PMAX)
- Or (PMAX, 0x0FFF, PMAX)
- Subtract (PMAX, PMIN, PLEN)
- Increment (PLEN)
-
- If (Local4)
- {
- Concatenate (RTAG (BUF0), Local3, Local5)
- Store (Local5, Local3)
- }
- Else
- {
- If (LGreater (PMAX, PMIN))
- {
- If (LOr (LAnd (LEqual (Arg1, 0xFF), LEqual (Arg0, 0x00)), LEqual (Arg1, \_SB.PCI0.SBLK)))
- {
- Store (0x0D00, PMIN)
- Subtract (PMAX, PMIN, PLEN)
- Increment (PLEN)
- }
-
- Store (RTAG (BUF0), Local3)
- Increment (Local4)
- }
-
- If (And (Local1, 0x10))
- {
- Store (0x03B0, PMIN)
- Store (0x03DF, PMAX)
- Store (0x30, PLEN)
- If (Local4)
- {
- Concatenate (RTAG (BUF0), Local3, Local5)
- Store (Local5, Local3)
- }
- Else
- {
- Store (RTAG (BUF0), Local3)
- }
- }
- }
-
- Increment (Local4)
- }
- }
- }
-
- Increment (Local0)
- }
-
- If (LNot (Local4))
- {
- Store (RTAG (BUF0), Local3)
- }
-
- Return (Local3)
- }
-
- Method (RTAG, 1, NotSerialized)
- {
- Store (Arg0, Local0)
- Store (SizeOf (Local0), Local1)
- Subtract (Local1, 0x02, Local1)
- Multiply (Local1, 0x08, Local1)
- CreateField (Local0, 0x00, Local1, RETB)
- Store (RETB, Local2)
- Return (Local2)
- }
- }
-
+++ /dev/null
-/*
- * Copyright 2005 AMD
- */
-DefinitionBlock ("DSDT.aml", "DSDT", 1, "AMD-K8", "AMDACPI", 100925440)
-{
- Scope (_PR)
- {
- Processor (CPU0, 0x00, 0x0000C010, 0x06) {}
- Processor (CPU1, 0x01, 0x00000000, 0x00) {}
- Processor (CPU2, 0x02, 0x00000000, 0x00) {}
- Processor (CPU3, 0x03, 0x00000000, 0x00) {}
-
- }
-
- Method (FWSO, 0, NotSerialized) { }
-
- Name (_S0, Package (0x04) { 0x00, 0x00, 0x00, 0x00 })
- Name (_S1, Package (0x04) { 0x01, 0x01, 0x01, 0x01 })
- Name (_S3, Package (0x04) { 0x05, 0x05, 0x05, 0x05 })
- Name (_S5, Package (0x04) { 0x07, 0x07, 0x07, 0x07 })
-
- Scope (_SB)
- {
- Device (PCI0)
- {
- /* BUS0 root bus */
-
- External (BUSN)
- External (MMIO)
- External (PCIO)
- External (SBLK)
- External (TOM1)
- External (HCLK)
- External (SBDN)
- External (HCDN)
- External (CBST)
-
-
- Name (_HID, EisaId ("PNP0A03"))
- Name (_ADR, 0x00180000)
- Name (_UID, 0x01)
-
- Name (HCIN, 0x00) // HC1
-
- Method (_BBN, 0, NotSerialized)
- {
- Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
- }
-
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUF0, ResourceTemplate ()
- {
- IO (Decode16, 0x0CF8, 0x0CF8, 0x01, 0x08) //CF8-CFFh
- IO (Decode16, 0xC000, 0xC000, 0x01, 0x80) //8000h
- IO (Decode16, 0xC080, 0xC080, 0x01, 0x80) //8080h
-
- WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
- 0x0000, // Address Space Granularity
- 0x8100, // Address Range Minimum
- 0xFFFF, // Address Range Maximum
- 0x0000, // Address Translation Offset
- 0x7F00,,,
- , TypeStatic) //8100h-FFFFh
-
- DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
- 0x00000000, // Address Space Granularity
- 0x000C0000, // Address Range Minimum
- 0x00000000, // Address Range Maximum
- 0x00000000, // Address Translation Offset
- 0x00000000,,,
- , AddressRangeMemory, TypeStatic) //Video BIOS A0000h-C7FFFh
-
- Memory32Fixed (ReadWrite, 0x000D8000, 0x00004000)//USB HC D8000-DBFFF
-
- WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
- 0x0000, // Address Space Granularity
- 0x0000, // Address Range Minimum
- 0x03AF, // Address Range Maximum
- 0x0000, // Address Translation Offset
- 0x03B0,,,
- , TypeStatic) //0-CF7h
-
- WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
- 0x0000, // Address Space Granularity
- 0x03E0, // Address Range Minimum
- 0x0CF7, // Address Range Maximum
- 0x0000, // Address Translation Offset
- 0x0918,,,
- , TypeStatic) //0-CF7h
- })
- \_SB.OSTP ()
- CreateDWordField (BUF0, 0x3E, VLEN)
- CreateDWordField (BUF0, 0x36, VMAX)
- CreateDWordField (BUF0, 0x32, VMIN)
- ShiftLeft (VGA1, 0x09, Local0)
- Add (VMIN, Local0, VMAX)
- Decrement (VMAX)
- Store (Local0, VLEN)
- Concatenate (\_SB.GMEM (0x00, \_SB.PCI0.SBLK), BUF0, Local1)
- Concatenate (\_SB.GIOR (0x00, \_SB.PCI0.SBLK), Local1, Local2)
- Concatenate (\_SB.GWBN (0x00, \_SB.PCI0.SBLK), Local2, Local3)
- Return (Local3)
- }
-
- Include ("pci0_hc.asl")
-
- }
- Device (PCI1)
- {
- Name (_HID, "PNP0A03")
- Name (_ADR, 0x00000000)
- Name (_UID, 0x02)
- Method (_STA, 0, NotSerialized)
- {
- Return (\_SB.PCI0.CBST)
- }
- Name (_BBN, 0x00)
- }
-
-
- }
-
- Scope (_GPE)
- {
- Method (_L08, 0, NotSerialized)
- {
- Notify (\_SB.PCI0, 0x02) //PME# Wakeup
- }
-
- Method (_L0F, 0, NotSerialized)
- {
- Notify (\_SB.PCI0.TP2P.USB0, 0x02) //USB Wakeup
- }
-
- Method (_L22, 0, NotSerialized) // GPIO18 (LID) - Pogo 0 Bridge B
- {
- Notify (\_SB.PCI0.PG0B, 0x02)
- }
-
- Method (_L29, 0, NotSerialized) // GPIO25 (Suspend) - Pogo 0 Bridge A
- {
- Notify (\_SB.PCI0.PG0A, 0x02)
- }
- }
-
- Method (_PTS, 1, NotSerialized)
- {
- Or (Arg0, 0xF0, Local0)
- Store (Local0, DBG1)
- }
-/*
- Method (_WAK, 1, NotSerialized)
- {
- Or (Arg0, 0xE0, Local0)
- Store (Local0, DBG1)
- }
-*/
- Name (PICF, 0x00) //Flag Variable for PIC vs. I/O APIC Mode
- Method (_PIC, 1, NotSerialized) //PIC Flag and Interface Method
- {
- Store (Arg0, PICF)
- }
-
- OperationRegion (DEBG, SystemIO, 0x80, 0x01)
- Field (DEBG, ByteAcc, Lock, Preserve)
- {
- DBG1, 8
- }
-
- OperationRegion (EXTM, SystemMemory, 0x000FF83C, 0x04)
- Field (EXTM, WordAcc, Lock, Preserve)
- {
- AMEM, 32
- }
-
- OperationRegion (VGAM, SystemMemory, 0x000C0002, 0x01)
- Field (VGAM, ByteAcc, Lock, Preserve)
- {
- VGA1, 8
- }
-
- OperationRegion (GRAM, SystemMemory, 0x0400, 0x0100)
- Field (GRAM, ByteAcc, Lock, Preserve)
- {
- Offset (0x10),
- FLG0, 8
- }
-
- OperationRegion (GSTS, SystemIO, 0xC028, 0x02)
- Field (GSTS, ByteAcc, NoLock, Preserve)
- {
- , 4,
- IRQR, 1
- }
-
- OperationRegion (Z007, SystemIO, 0x21, 0x01)
- Field (Z007, ByteAcc, NoLock, Preserve)
- {
- Z008, 8
- }
-
- OperationRegion (Z009, SystemIO, 0xA1, 0x01)
- Field (Z009, ByteAcc, NoLock, Preserve)
- {
- Z00A, 8
- }
-
- Include ("amdk8_util.asl")
-
-}
-
+++ /dev/null
- Include ("amd8111.asl") //real SB at first
- Include ("amd8131.asl")
+++ /dev/null
-/*
- * Copyright 2005 AMD
- */
-DefinitionBlock ("SSDT2.aml", "SSDT", 1, "AMD-K8", "AMDACPI", 100925440)
-{
- Scope (_SB)
- {
- External (DADD, MethodObj)
- External (GHCE, MethodObj)
- External (GHCN, MethodObj)
- External (GHCL, MethodObj)
- External (GHCD, MethodObj)
- External (GNUS, MethodObj)
- External (GIOR, MethodObj)
- External (GMEM, MethodObj)
- External (GWBN, MethodObj)
- External (GBUS, MethodObj)
-
- External (PICF)
-
- External (\_SB.PCI0.LNKA, DeviceObj)
- External (\_SB.PCI0.LNKB, DeviceObj)
- External (\_SB.PCI0.LNKC, DeviceObj)
- External (\_SB.PCI0.LNKD, DeviceObj)
-
- Device (PCIX)
- {
-
- // BUS ? Second HT Chain
- Name (HCIN, 0xcc) // HC2 0x01
-
- Name (_UID, 0xdd) // HC 0x03
-
- Name (_HID, "PNP0A03")
-
- Method (_ADR, 0, NotSerialized) //Fake bus should be 0
- {
- Return (DADD(GHCN(HCIN), 0x00000000))
- }
-
- Method (_BBN, 0, NotSerialized)
- {
- Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
- }
-
- Method (_STA, 0, NotSerialized)
- {
- Return (\_SB.GHCE(HCIN))
- }
-
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUF0, ResourceTemplate () { })
- Store( GHCN(HCIN), Local4)
- Store( GHCL(HCIN), Local5)
-
- Concatenate (\_SB.GIOR (Local4, Local5), BUF0, Local1)
- Concatenate (\_SB.GMEM (Local4, Local5), Local1, Local2)
- Concatenate (\_SB.GWBN (Local4, Local5), Local2, Local3)
- Return (Local3)
- }
-
- Include ("pci2_hc.asl")
- }
- }
-
-}
-
+++ /dev/null
- Include ("amd8132_2.asl")
+++ /dev/null
-/*
- * Copyright 2005 AMD
- */
-DefinitionBlock ("SSDT3.aml", "SSDT", 1, "AMD-K8", "AMDACPI", 100925440)
-{
- Scope (_SB)
- {
- External (DADD, MethodObj)
- External (GHCE, MethodObj)
- External (GHCN, MethodObj)
- External (GHCL, MethodObj)
- External (GHCD, MethodObj)
- External (GNUS, MethodObj)
- External (GIOR, MethodObj)
- External (GMEM, MethodObj)
- External (GWBN, MethodObj)
- External (GBUS, MethodObj)
-
- External (PICF)
-
- External (\_SB.PCI0.LNKA, DeviceObj)
- External (\_SB.PCI0.LNKB, DeviceObj)
- External (\_SB.PCI0.LNKC, DeviceObj)
- External (\_SB.PCI0.LNKD, DeviceObj)
-
- Device (PCIX)
- {
-
- // BUS ? Second HT Chain
- Name (HCIN, 0xcc) // HC2 0x01
-
- Name (_UID, 0xdd) // HC 0x03
-
- Name (_HID, "PNP0A03")
-
- Method (_ADR, 0, NotSerialized) //Fake bus should be 0
- {
- Return (DADD(GHCN(HCIN), 0x00000000))
- }
-
- Method (_BBN, 0, NotSerialized)
- {
- Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
- }
-
- Method (_STA, 0, NotSerialized)
- {
- Return (\_SB.GHCE(HCIN))
- }
-
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUF0, ResourceTemplate () { })
- Store( GHCN(HCIN), Local4)
- Store( GHCL(HCIN), Local5)
-
- Concatenate (\_SB.GIOR (Local4, Local5), BUF0, Local1)
- Concatenate (\_SB.GMEM (Local4, Local5), Local1, Local2)
- Concatenate (\_SB.GWBN (Local4, Local5), Local2, Local3)
- Return (Local3)
- }
-
- Include ("pci3_hc.asl")
- }
- }
-
-}
-
+++ /dev/null
- Include ("amd8151.asl")
+++ /dev/null
-/*
- * Copyright 2005 AMD
- */
-DefinitionBlock ("SSDT4.aml", "SSDT", 1, "AMD-K8", "AMDACPI", 100925440)
-{
- Scope (_SB)
- {
- External (DADD, MethodObj)
- External (GHCE, MethodObj)
- External (GHCN, MethodObj)
- External (GHCL, MethodObj)
- External (GHCD, MethodObj)
- External (GNUS, MethodObj)
- External (GIOR, MethodObj)
- External (GMEM, MethodObj)
- External (GWBN, MethodObj)
- External (GBUS, MethodObj)
-
- External (PICF)
-
- External (\_SB.PCI0.LNKA, DeviceObj)
- External (\_SB.PCI0.LNKB, DeviceObj)
- External (\_SB.PCI0.LNKC, DeviceObj)
- External (\_SB.PCI0.LNKD, DeviceObj)
-
- Device (PCIX)
- {
-
- // BUS ? Second HT Chain
- Name (HCIN, 0xcc) // HC2 0x01
-
- Name (_UID, 0xdd) // HC 0x03
-
- Name (_HID, "PNP0A03")
-
- Method (_ADR, 0, NotSerialized) //Fake bus should be 0
- {
- Return (DADD(GHCN(HCIN), 0x00000000))
- }
-
- Method (_BBN, 0, NotSerialized)
- {
- Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
- }
-
- Method (_STA, 0, NotSerialized)
- {
- Return (\_SB.GHCE(HCIN))
- }
-
- Method (_CRS, 0, NotSerialized)
- {
- Name (BUF0, ResourceTemplate () { })
- Store( GHCN(HCIN), Local4)
- Store( GHCL(HCIN), Local5)
-
- Concatenate (\_SB.GIOR (Local4, Local5), BUF0, Local1)
- Concatenate (\_SB.GMEM (Local4, Local5), Local1, Local2)
- Concatenate (\_SB.GWBN (Local4, Local5), Local2, Local3)
- Return (Local3)
- }
-
- Include ("pci4_hc.asl")
- }
- }
-
-}
-
+++ /dev/null
- Include ("amd8131_2.asl")
+++ /dev/null
-// Include ("w83627hf.asl")
+++ /dev/null
-/*
- * ACPI - create the Fixed ACPI Description Tables (FADT)
- * (C) Copyright 2005 Stefan Reinauer <stepan@openbios.org>
- */
-
-#include <string.h>
-#include <console/console.h>
-#include <arch/acpi.h>
-
-extern unsigned pm_base; /* pm_base should be set in sb acpi */
-
-void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){
-
- acpi_header_t *header=&(fadt->header);
-
- printk_debug("pm_base: 0x%04x\n", pm_base);
-
- /* Prepare the header */
- memset((void *)fadt,0,sizeof(acpi_fadt_t));
- memcpy(header->signature,"FACP",4);
- header->length = 244;
- header->revision = 1;
- memcpy(header->oem_id,OEM_ID,6);
- memcpy(header->oem_table_id,"LXBACPI ",8);
- memcpy(header->asl_compiler_id,ASLC,4);
- header->asl_compiler_revision=0;
-
- fadt->firmware_ctrl=(u32)facs;
- fadt->dsdt= (u32)dsdt;
- fadt->res1=0x0;
- // 3=Workstation,4=Enterprise Server, 7=Performance Server
- fadt->preferred_pm_profile=0x03;
- fadt->sci_int=9;
- // disable system management mode by setting to 0:
- fadt->smi_cmd = 0;//pm_base+0x2f;
- fadt->acpi_enable = 0xf0;
- fadt->acpi_disable = 0xf1;
- fadt->s4bios_req = 0x0;
- fadt->pstate_cnt = 0xe2;
-
- fadt->pm1a_evt_blk = pm_base;
- fadt->pm1b_evt_blk = 0x0000;
- fadt->pm1a_cnt_blk = pm_base+0x04;
- fadt->pm1b_cnt_blk = 0x0000;
- fadt->pm2_cnt_blk = 0x0000;
- fadt->pm_tmr_blk = pm_base+0x08;
- fadt->gpe0_blk = pm_base+0x20;
- fadt->gpe1_blk = pm_base+0xb0;
-
- fadt->pm1_evt_len = 4;
- fadt->pm1_cnt_len = 2;
- fadt->pm2_cnt_len = 0;
- fadt->pm_tmr_len = 4;
- fadt->gpe0_blk_len = 4;
- fadt->gpe1_blk_len = 8;
- fadt->gpe1_base = 16;
-
- fadt->cst_cnt = 0xe3;
- fadt->p_lvl2_lat = 101;
- fadt->p_lvl3_lat = 1001;
- fadt->flush_size = 0;
- fadt->flush_stride = 0;
- fadt->duty_offset = 1;
- fadt->duty_width = 3;
- fadt->day_alrm = 0; // 0x7d these have to be
- fadt->mon_alrm = 0; // 0x7e added to cmos.layout
- fadt->century = 0; // 0x7f to make rtc alrm work
- fadt->iapc_boot_arch = 0x3; // See table 5-11
- fadt->flags = 0x25;
-
- fadt->res2 = 0;
-
- fadt->reset_reg.space_id = 1;
- fadt->reset_reg.bit_width = 8;
- fadt->reset_reg.bit_offset = 0;
- fadt->reset_reg.resv = 0;
- fadt->reset_reg.addrl = 0xcf9;
- fadt->reset_reg.addrh = 0x0;
-
- fadt->reset_value = 6;
- fadt->x_firmware_ctl_l = (u32)facs;
- fadt->x_firmware_ctl_h = 0;
- fadt->x_dsdt_l = (u32)dsdt;
- fadt->x_dsdt_h = 0;
-
- fadt->x_pm1a_evt_blk.space_id = 1;
- fadt->x_pm1a_evt_blk.bit_width = 32;
- fadt->x_pm1a_evt_blk.bit_offset = 0;
- fadt->x_pm1a_evt_blk.resv = 0;
- fadt->x_pm1a_evt_blk.addrl = pm_base;
- fadt->x_pm1a_evt_blk.addrh = 0x0;
-
- fadt->x_pm1b_evt_blk.space_id = 1;
- fadt->x_pm1b_evt_blk.bit_width = 4;
- fadt->x_pm1b_evt_blk.bit_offset = 0;
- fadt->x_pm1b_evt_blk.resv = 0;
- fadt->x_pm1b_evt_blk.addrl = 0x0;
- fadt->x_pm1b_evt_blk.addrh = 0x0;
-
-
- fadt->x_pm1a_cnt_blk.space_id = 1;
- fadt->x_pm1a_cnt_blk.bit_width = 16;
- fadt->x_pm1a_cnt_blk.bit_offset = 0;
- fadt->x_pm1a_cnt_blk.resv = 0;
- fadt->x_pm1a_cnt_blk.addrl = pm_base+4;
- fadt->x_pm1a_cnt_blk.addrh = 0x0;
-
- fadt->x_pm1b_cnt_blk.space_id = 1;
- fadt->x_pm1b_cnt_blk.bit_width = 2;
- fadt->x_pm1b_cnt_blk.bit_offset = 0;
- fadt->x_pm1b_cnt_blk.resv = 0;
- fadt->x_pm1b_cnt_blk.addrl = 0x0;
- fadt->x_pm1b_cnt_blk.addrh = 0x0;
-
-
- fadt->x_pm2_cnt_blk.space_id = 1;
- fadt->x_pm2_cnt_blk.bit_width = 0;
- fadt->x_pm2_cnt_blk.bit_offset = 0;
- fadt->x_pm2_cnt_blk.resv = 0;
- fadt->x_pm2_cnt_blk.addrl = 0x0;
- fadt->x_pm2_cnt_blk.addrh = 0x0;
-
-
- fadt->x_pm_tmr_blk.space_id = 1;
- fadt->x_pm_tmr_blk.bit_width = 32;
- fadt->x_pm_tmr_blk.bit_offset = 0;
- fadt->x_pm_tmr_blk.resv = 0;
- fadt->x_pm_tmr_blk.addrl = pm_base+0x08;
- fadt->x_pm_tmr_blk.addrh = 0x0;
-
-
- fadt->x_gpe0_blk.space_id = 1;
- fadt->x_gpe0_blk.bit_width = 32;
- fadt->x_gpe0_blk.bit_offset = 0;
- fadt->x_gpe0_blk.resv = 0;
- fadt->x_gpe0_blk.addrl = pm_base+0x20;
- fadt->x_gpe0_blk.addrh = 0x0;
-
-
- fadt->x_gpe1_blk.space_id = 1;
- fadt->x_gpe1_blk.bit_width = 64;
- fadt->x_gpe1_blk.bit_offset = 16;
- fadt->x_gpe1_blk.resv = 0;
- fadt->x_gpe1_blk.addrl = pm_base+0xb0;
- fadt->x_gpe1_blk.addrh = 0x0;
-
- header->checksum = acpi_checksum((void *)fadt, sizeof(acpi_fadt_t));
-
-}
+++ /dev/null
-#include <console/console.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <string.h>
-#include <stdint.h>
-#if CONFIG_LOGICAL_CPUS==1
-#include <cpu/amd/dualcore.h>
-#endif
-
-#include <cpu/amd/amdk8_sysconf.h>
-
-#include "mb_sysconf.h"
-
-// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
-struct mb_sysconf_t mb_sysconf;
-
-static unsigned pci1234x[] =
-{ //Here you only need to set value in pci1234 for HT-IO that could be installed or not
- //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
- 0x0000ff0, // SB chain m
- 0x0000000, // HTX
- 0x0000100, // co processor on socket 1
-// 0x0000ff0,
-// 0x0000ff0,
-// 0x0000ff0,
-// 0x0000ff0,
-// 0x0000ff0
-};
-static unsigned hcdnx[] =
-{ //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most
- 0x20202020,
- 0x20202020,
- 0x20202020,
-// 0x20202020,
-// 0x20202020,
-// 0x20202020,
-// 0x20202020,
-// 0x20202020,
-};
-
-extern void get_sblk_pci1234(void);
-
-static unsigned get_bus_conf_done = 0;
-
-static unsigned get_hcid(unsigned i)
-{
- unsigned id = 0;
-
- unsigned busn = (sysconf.pci1234[i] >> 16) & 0xff;
-
- unsigned devn = sysconf.hcdn[i] & 0xff;
-
- device_t dev;
-
- dev = dev_find_slot(busn, PCI_DEVFN(devn,0));
-
- switch (dev->device) {
- case 0x7458: //8132
- id = 1;
- break;
- case 0x7454: //8151
- id = 2;
- break;
- case 0x7450: //8131
- id = 3;
- break;
- }
-
- // we may need more way to find out hcid: subsystem id? GPIO read ?
-
- // we need use id for 1. bus num, 2. mptable, 3. acpi table
-
- return id;
-}
-
-void get_bus_conf(void)
-{
-
- unsigned apicid_base;
-
- device_t dev;
- int i, j;
- struct mb_sysconf_t *m;
-
- if(get_bus_conf_done == 1) return; //do it only once
-
- get_bus_conf_done = 1;
-
- sysconf.mb = &mb_sysconf;
-
- m = sysconf.mb;
-
- sysconf.hc_possible_num = sizeof(pci1234x)/sizeof(pci1234x[0]);
- for(i=0;i<sysconf.hc_possible_num; i++) {
- sysconf.pci1234[i] = pci1234x[i];
- sysconf.hcdn[i] = hcdnx[i];
- }
-
- get_sblk_pci1234();
-
- sysconf.sbdn = (sysconf.hcdn[0] >> 8) & 0xff;
- m->sbdn3 = sysconf.hcdn[0] & 0xff;
-
- m->bus_8132_0 = (sysconf.pci1234[0] >> 16) & 0xff;
- m->bus_8111_0 = m->bus_8132_0;
-
- /* 8111 */
- dev = dev_find_slot(m->bus_8111_0, PCI_DEVFN(sysconf.sbdn,0));
- if (dev) {
- m->bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
-#if HT_CHAIN_END_UNITID_BASE >= HT_CHAIN_UNITID_BASE
- m->bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
- m->bus_isa++;
-// printk_debug("bus_isa=%d\n",bus_isa);
-#endif
- }
- else {
- printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_8111_0, sysconf.sbdn);
- }
-
- /* 8132-1 */
- dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3,0));
- if (dev) {
- m->bus_8132_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
- else {
- printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_8132_0, m->sbdn3);
- }
-
- /* 8132-2 */
- dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3+1,0));
- if (dev) {
- m->bus_8132_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
-#if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE
- m->bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
- m->bus_isa++;
-// printk_debug("bus_isa=%d\n",bus_isa);
-#endif
- }
- else {
- printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_8132_0, m->sbdn3+1);
- }
-
- /* HT chain 1 */
- j=0;
- for(i=1; i< sysconf.hc_possible_num; i++) {
- if(!(sysconf.pci1234[i] & 0x1) ) continue;
-
- // check hcid type here
- sysconf.hcid[i] = get_hcid(i);
-
- switch(sysconf.hcid[i]) {
-
- case 1: //8132
- case 3: //8131
-
- m->bus_8132a[j][0] = (sysconf.pci1234[i] >> 16) & 0xff;
-
- m->sbdn3a[j] = sysconf.hcdn[i] & 0xff;
-
- /* 8132-1 */
- dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j],0));
- if (dev) {
- m->bus_8132a[j][1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- }
- else {
- printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_8132a[j][0], m->sbdn3a[j]);
- }
-
- /* 8132-2 */
- dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1,0));
- if (dev) {
- m->bus_8132a[j][2] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- m->bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
- m->bus_isa++;
- // printk_debug("bus_isa=%d\n",bus_isa);
- }
- else {
- printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_8132a[j][0], m->sbdn3a[j]+1);
- }
-
- break;
-
- case 2: //8151
-
- m->bus_8151[j][0] = (sysconf.pci1234[i] >> 16) & 0xff;
- m->sbdn5[j] = sysconf.hcdn[i] & 0xff;
- /* 8151 */
- dev = dev_find_slot(m->bus_8151[j][0], PCI_DEVFN(m->sbdn5[j]+1, 0));
-
- if (dev) {
- m->bus_8151[j][1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
- // printk_debug("bus_8151_1=%d\n",bus_8151[j][1]);
- m->bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
- m->bus_isa++;
- }
- else {
- printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_8151[j][0], m->sbdn5[j]+1);
- }
-
- break;
- }
-
- j++;
- }
-
-
-/*I/O APICs: APIC ID Version State Address*/
-#if CONFIG_LOGICAL_CPUS==1
- apicid_base = get_apicid_base(3);
-#else
- apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
-#endif
- m->apicid_8111 = apicid_base+0;
- m->apicid_8132_1 = apicid_base+1;
- m->apicid_8132_2 = apicid_base+2;
- for(i=0;i<j;i++) {
- m->apicid_8132a[i][0] = apicid_base + 3 + i*2;
- m->apicid_8132a[i][1] = apicid_base + 3 + i*2 + 1;
- }
-
-}
+++ /dev/null
-/* This file was generated by getpir.c, do not modify!
- (but if you do, please run checkpir on it to verify)
- Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up
-
- Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM
-*/
-#include <console/console.h>
-#include <device/pci.h>
-#include <string.h>
-#include <stdint.h>
-#include <arch/pirq_routing.h>
-#include <cpu/amd/amdk8_sysconf.h>
-
-#include "mb_sysconf.h"
-
-static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0,
- uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3,
- uint8_t slot, uint8_t rfu)
-{
- pirq_info->bus = bus;
- pirq_info->devfn = devfn;
-
- pirq_info->irq[0].link = link0;
- pirq_info->irq[0].bitmap = bitmap0;
- pirq_info->irq[1].link = link1;
- pirq_info->irq[1].bitmap = bitmap1;
- pirq_info->irq[2].link = link2;
- pirq_info->irq[2].bitmap = bitmap2;
- pirq_info->irq[3].link = link3;
- pirq_info->irq[3].bitmap = bitmap3;
-
- pirq_info->slot = slot;
- pirq_info->rfu = rfu;
-}
-
-
-extern void get_bus_conf(void);
-
-unsigned long write_pirq_routing_table(unsigned long addr)
-{
-
- struct irq_routing_table *pirq;
- struct irq_info *pirq_info;
- unsigned slot_num;
- uint8_t *v;
-
- uint8_t sum=0;
- int i;
-
- struct mb_sysconf_t *m;
-
- get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c
-
- m = sysconf.mb;
-
- /* Align the table to be 16 byte aligned. */
- addr += 15;
- addr &= ~15;
-
- /* This table must be betweeen 0xf0000 & 0x100000 */
- printk_info("Writing IRQ routing tables to 0x%x...", addr);
-
- pirq = (void *)(addr);
- v = (uint8_t *)(addr);
-
- pirq->signature = PIRQ_SIGNATURE;
- pirq->version = PIRQ_VERSION;
-
- pirq->rtr_bus = m->bus_8111_0;
- pirq->rtr_devfn = ((sysconf.sbdn+1)<<3)|0;
-
- pirq->exclusive_irqs = 0;
-
- pirq->rtr_vendor = 0x1022;
- pirq->rtr_device = 0x746b;
-
- pirq->miniport_data = 0;
-
- memset(pirq->rfu, 0, sizeof(pirq->rfu));
-
- pirq_info = (void *) ( &pirq->checksum + 1);
- slot_num = 0;
-
- {
- device_t dev;
- dev = dev_find_slot(m->bus_8111_0, PCI_DEVFN(sysconf.sbdn+1,3));
- if (dev) {
- /* initialize PCI interupts - these assignments depend
- on the PCB routing of PINTA-D
-
- PINTA = IRQ3
- PINTB = IRQ5
- PINTC = IRQ10
- PINTD = IRQ11
- */
- pci_write_config16(dev, 0x56, 0xba53);
- }
- }
-
-//pci bridge
- printk_debug("setting Onboard AMD Southbridge \n");
- static const unsigned char slotIrqs_1_4[4] = { 3, 5, 10, 11 };
- pci_assign_irqs(m->bus_8111_0, sysconf.sbdn+1, slotIrqs_1_4);
- write_pirq_info(pirq_info, m->bus_8111_0, ((sysconf.sbdn+1)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
- pirq_info++; slot_num++;
-
- printk_debug("setting Onboard AMD USB \n");
- static const unsigned char slotIrqs_8111_1_0[4] = { 0, 0, 0, 11};
- pci_assign_irqs(m->bus_8111_1, 0, slotIrqs_8111_1_0);
- write_pirq_info(pirq_info, m->bus_8111_1,0, 0, 0, 0, 0, 0, 0, 0x4, 0xdef8, 0, 0);
- pirq_info++; slot_num++;
-
-//pcix bridge
-// write_pirq_info(pirq_info, m->bus_8132_0, (sbdn3<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
-// pirq_info++; slot_num++;
-
- int j = 0;
-
- for(i=1; i< sysconf.hc_possible_num; i++) {
- if(!(sysconf.pci1234[i] & 0x1) ) continue;
- unsigned busn = (sysconf.pci1234[i] >> 16) & 0xff;
- unsigned devn = sysconf.hcdn[i] & 0xff;
-
- write_pirq_info(pirq_info, busn, (devn<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
- pirq_info++; slot_num++;
- j++;
-
- }
-
- pirq->size = 32 + 16 * slot_num;
-
- for (i = 0; i < pirq->size; i++)
- sum += v[i];
-
- sum = pirq->checksum - sum;
-
- if (sum != pirq->checksum) {
- pirq->checksum = sum;
- }
-
- printk_info("done.\n");
-
- return (unsigned long) pirq_info;
-
-}
+++ /dev/null
-#include <console/console.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <device/pci_ids.h>
-#include <device/pci_ops.h>
-#include "chip.h"
-
-#if CONFIG_CHIP_NAME == 1
-struct chip_operations mainboard_Iwill_dk8_htx_ops = {
- CHIP_NAME("Iwill DK8-HTX mainboard")
-};
-#endif
+++ /dev/null
-#ifndef MB_SYSCONF_H
-
-#define MB_SYSCONF_H
-
-struct mb_sysconf_t {
- unsigned char bus_isa;
- unsigned char bus_8132_0;
- unsigned char bus_8132_1;
- unsigned char bus_8132_2;
- unsigned char bus_8111_0;
- unsigned char bus_8111_1;
-
- unsigned char bus_8132a[7][3];
-
- unsigned char bus_8151[7][2];
-
- unsigned apicid_8111;
- unsigned apicid_8132_1;
- unsigned apicid_8132_2;
- unsigned apicid_8132a[7][2];
-
- unsigned sbdn3;
- unsigned sbdn3a[7];
- unsigned sbdn5[7];
-
-};
-
-#endif
-
+++ /dev/null
-#include <console/console.h>
-#include <arch/smp/mpspec.h>
-#include <device/pci.h>
-#include <string.h>
-#include <stdint.h>
-#if CONFIG_LOGICAL_CPUS==1
-#include <cpu/amd/dualcore.h>
-#endif
-
-#include <cpu/amd/amdk8_sysconf.h>
-#include "mb_sysconf.h"
-
-extern void get_bus_conf(void);
-
-void *smp_write_config_table(void *v)
-{
- static const char sig[4] = "PCMP";
- static const char oem[8] = "IWILL ";
- static const char productid[12] = "DK8-HTX ";
- struct mp_config_table *mc;
-
- unsigned char bus_num;
- int i, j;
- struct mb_sysconf_t *m;
-
- mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
- memset(mc, 0, sizeof(*mc));
-
- memcpy(mc->mpc_signature, sig, sizeof(sig));
- mc->mpc_length = sizeof(*mc); /* initially just the header */
- mc->mpc_spec = 0x04;
- mc->mpc_checksum = 0; /* not yet computed */
- memcpy(mc->mpc_oem, oem, sizeof(oem));
- memcpy(mc->mpc_productid, productid, sizeof(productid));
- mc->mpc_oemptr = 0;
- mc->mpc_oemsize = 0;
- mc->mpc_entry_count = 0; /* No entries yet... */
- mc->mpc_lapic = LAPIC_ADDR;
- mc->mpe_length = 0;
- mc->mpe_checksum = 0;
- mc->reserved = 0;
-
- smp_write_processors(mc);
-
- get_bus_conf();
-
- m = sysconf.mb;
-
-/*Bus: Bus ID Type*/
- /* define bus and isa numbers */
- for(bus_num = 0; bus_num < m->bus_isa; bus_num++) {
- smp_write_bus(mc, bus_num, "PCI ");
- }
- smp_write_bus(mc, m->bus_isa, "ISA ");
-
-/*I/O APICs: APIC ID Version State Address*/
- smp_write_ioapic(mc, m->apicid_8111, 0x11, 0xfec00000); //8111
- {
- device_t dev;
- struct resource *res;
- dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3, 1));
- if (dev) {
- res = find_resource(dev, PCI_BASE_ADDRESS_0);
- if (res) {
- smp_write_ioapic(mc, m->apicid_8132_1, 0x11, res->base);
- }
- }
- dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3+1, 1));
- if (dev) {
- res = find_resource(dev, PCI_BASE_ADDRESS_0);
- if (res) {
- smp_write_ioapic(mc, m->apicid_8132_2, 0x11, res->base);
- }
- }
-
- j = 0;
-
- for(i=1; i< sysconf.hc_possible_num; i++) {
- if(!(sysconf.pci1234[i] & 0x1) ) continue;
-
- switch(sysconf.hcid[i]) {
- case 1: // 8132
- case 3: // 8131
- dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j], 1));
- if (dev) {
- res = find_resource(dev, PCI_BASE_ADDRESS_0);
- if (res) {
- smp_write_ioapic(mc, m->apicid_8132a[j][0], 0x11, res->base);
- }
- }
- dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1, 1));
- if (dev) {
- res = find_resource(dev, PCI_BASE_ADDRESS_0);
- if (res) {
- smp_write_ioapic(mc, m->apicid_8132a[j][1], 0x11, res->base);
- }
- }
- break;
- }
- j++;
- }
-
- }
-
-/*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
- smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, m->apicid_8111, 0x0);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x1, m->apicid_8111, 0x1);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, m->apicid_8111, 0x2);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x3, m->apicid_8111, 0x3);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x4, m->apicid_8111, 0x4);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x5, m->apicid_8111, 0x5);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x6, m->apicid_8111, 0x6);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x7, m->apicid_8111, 0x7);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x8, m->apicid_8111, 0x8);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x9, m->apicid_8111, 0x9);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0xc, m->apicid_8111, 0xc);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0xd, m->apicid_8111, 0xd);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0xe, m->apicid_8111, 0xe);
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0xf, m->apicid_8111, 0xf);
-//??? What
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_0, ((sysconf.sbdn+1)<<2)|3, m->apicid_8111, 0x13);
-
-// Onboard AMD USB
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (0<<2)|3, m->apicid_8111, 0x13);
-
-// Onboard VGA
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (6<<2)|0, m->apicid_8111, 0x12);
-
-//Slot 5 PCI 32
- for(i=0;i<4;i++) {
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (5<<2)|i, m->apicid_8111, 0x10 + (1+i)%4); //16
- }
-
-//Slot 6 PCI 32
- for(i=0;i<4;i++) {
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (4<<2)|i, m->apicid_8111, 0x10 + (0+i)%4); //16
- }
-//Slot 1: HTX
-
-//Slot 2 PCI-X 133/100/66
- for(i=0;i<4;i++) {
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_2, (2<<2)|i, m->apicid_8132_2, (2+i)%4); //30
- }
-
-//Slot 3 PCI-X 133/100/66
- for(i=0;i<4;i++) {
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (1<<2)|i, m->apicid_8132_1, (1+i)%4); //25
- }
-
-//Slot 4 PCI-X 133/100/66
- for(i=0;i<4;i++) {
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (2<<2)|i, m->apicid_8132_1, (2+i)%4); //26
- }
-
-//Onboard NICS
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (3<<2)|0, m->apicid_8132_1, 3); //27
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (4<<2)|0, m->apicid_8132_1, 0); //24
-
-//Onboard SATA
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (5<<2)|0, m->apicid_8132_1, 1); //25
-
- j = 0;
-
- for(i=1; i< sysconf.hc_possible_num; i++) {
- if(!(sysconf.pci1234[i] & 0x1) ) continue;
- int ii;
- device_t dev;
- struct resource *res;
- switch(sysconf.hcid[i]) {
- case 1:
- case 3:
- dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j], 1));
- if (dev) {
- res = find_resource(dev, PCI_BASE_ADDRESS_0);
- if (res) {
- //Slot 1 PCI-X 133/100/66
- for(ii=0;ii<4;ii++) {
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][1], (0<<2)|ii, m->apicid_8132a[j][0], (0+ii)%4); //
- }
- }
- }
-
- dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1, 1));
- if (dev) {
- res = find_resource(dev, PCI_BASE_ADDRESS_0);
- if (res) {
- //Slot 2 PCI-X 133/100/66
- for(ii=0;ii<4;ii++) {
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][2], (0<<2)|ii, m->apicid_8132a[j][1], (0+ii)%4); //25
- }
- }
- }
-
- break;
- case 2:
-
- // Slot AGP
- smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8151[j][1], 0x0, m->apicid_8111, 0x11);
- break;
- }
-
- j++;
- }
-
-
-
-/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
- smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x0);
- smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x1);
- /* There is no extension information... */
-
- /* Compute the checksums */
- mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
- mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
- printk_debug("Wrote the mp table end at: %p - %p\n",
- mc, smp_next_mpe_entry(mc));
- return smp_next_mpe_entry(mc);
-}
-
-unsigned long write_smp_table(unsigned long addr)
-{
- void *v;
- v = smp_write_floating_table(addr);
- return (unsigned long)smp_write_config_table(v);
-}
+++ /dev/null
-/*
- *
- */
-
-static void setup_mb_resource_map(void)
-{
- static const unsigned int register_values[] = {
- /* Careful set limit registers before base registers which contain the enables */
- /* DRAM Limit i Registers
- * F1:0x44 i = 0
- * F1:0x4C i = 1
- * F1:0x54 i = 2
- * F1:0x5C i = 3
- * F1:0x64 i = 4
- * F1:0x6C i = 5
- * F1:0x74 i = 6
- * F1:0x7C i = 7
- * [ 2: 0] Destination Node ID
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 7: 3] Reserved
- * [10: 8] Interleave select
- * specifies the values of A[14:12] to use with interleave enable.
- * [15:11] Reserved
- * [31:16] DRAM Limit Address i Bits 39-24
- * This field defines the upper address bits of a 40 bit address
- * that define the end of the DRAM region.
- */
- PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001,
- PCI_ADDR(0, 0x18, 1, 0x54), 0x0000f8f8, 0x00000002,
- PCI_ADDR(0, 0x18, 1, 0x5C), 0x0000f8f8, 0x00000003,
- PCI_ADDR(0, 0x18, 1, 0x64), 0x0000f8f8, 0x00000004,
- PCI_ADDR(0, 0x18, 1, 0x6C), 0x0000f8f8, 0x00000005,
- PCI_ADDR(0, 0x18, 1, 0x74), 0x0000f8f8, 0x00000006,
- PCI_ADDR(0, 0x18, 1, 0x7C), 0x0000f8f8, 0x00000007,
- /* DRAM Base i Registers
- * F1:0x40 i = 0
- * F1:0x48 i = 1
- * F1:0x50 i = 2
- * F1:0x58 i = 3
- * F1:0x60 i = 4
- * F1:0x68 i = 5
- * F1:0x70 i = 6
- * F1:0x78 i = 7
- * [ 0: 0] Read Enable
- * 0 = Reads Disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes Disabled
- * 1 = Writes Enabled
- * [ 7: 2] Reserved
- * [10: 8] Interleave Enable
- * 000 = No interleave
- * 001 = Interleave on A[12] (2 nodes)
- * 010 = reserved
- * 011 = Interleave on A[12] and A[14] (4 nodes)
- * 100 = reserved
- * 101 = reserved
- * 110 = reserved
- * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
- * [15:11] Reserved
- * [13:16] DRAM Base Address i Bits 39-24
- * This field defines the upper address bits of a 40-bit address
- * that define the start of the DRAM region.
- */
- PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00000000,
-
- /* Memory-Mapped I/O Limit i Registers
- * F1:0x84 i = 0
- * F1:0x8C i = 1
- * F1:0x94 i = 2
- * F1:0x9C i = 3
- * F1:0xA4 i = 4
- * F1:0xAC i = 5
- * F1:0xB4 i = 6
- * F1:0xBC i = 7
- * [ 2: 0] Destination Node ID
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 3: 3] Reserved
- * [ 5: 4] Destination Link ID
- * 00 = Link 0
- * 01 = Link 1
- * 10 = Link 2
- * 11 = Reserved
- * [ 6: 6] Reserved
- * [ 7: 7] Non-Posted
- * 0 = CPU writes may be posted
- * 1 = CPU writes must be non-posted
- * [31: 8] Memory-Mapped I/O Limit Address i (39-16)
- * This field defines the upp adddress bits of a 40-bit address that
- * defines the end of a memory-mapped I/O region n
- */
- PCI_ADDR(0, 0x18, 1, 0x84), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x8C), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x94), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x9C), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xA4), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xB4), 0x00000048, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00ffff20,
-
- /* Memory-Mapped I/O Base i Registers
- * F1:0x80 i = 0
- * F1:0x88 i = 1
- * F1:0x90 i = 2
- * F1:0x98 i = 3
- * F1:0xA0 i = 4
- * F1:0xA8 i = 5
- * F1:0xB0 i = 6
- * F1:0xB8 i = 7
- * [ 0: 0] Read Enable
- * 0 = Reads disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes disabled
- * 1 = Writes Enabled
- * [ 2: 2] Cpu Disable
- * 0 = Cpu can use this I/O range
- * 1 = Cpu requests do not use this I/O range
- * [ 3: 3] Lock
- * 0 = base/limit registers i are read/write
- * 1 = base/limit registers i are read-only
- * [ 7: 4] Reserved
- * [31: 8] Memory-Mapped I/O Base Address i (39-16)
- * This field defines the upper address bits of a 40bit address
- * that defines the start of memory-mapped I/O region i
- */
- PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x88), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x90), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0x98), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xA0), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00fc0003,
-
- /* PCI I/O Limit i Registers
- * F1:0xC4 i = 0
- * F1:0xCC i = 1
- * F1:0xD4 i = 2
- * F1:0xDC i = 3
- * [ 2: 0] Destination Node ID
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 3: 3] Reserved
- * [ 5: 4] Destination Link ID
- * 00 = Link 0
- * 01 = Link 1
- * 10 = Link 2
- * 11 = reserved
- * [11: 6] Reserved
- * [24:12] PCI I/O Limit Address i
- * This field defines the end of PCI I/O region n
- * [31:25] Reserved
- */
- PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x01fff020,
- PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000,
-
- /* PCI I/O Base i Registers
- * F1:0xC0 i = 0
- * F1:0xC8 i = 1
- * F1:0xD0 i = 2
- * F1:0xD8 i = 3
- * [ 0: 0] Read Enable
- * 0 = Reads Disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes Disabled
- * 1 = Writes Enabled
- * [ 3: 2] Reserved
- * [ 4: 4] VGA Enable
- * 0 = VGA matches Disabled
- * 1 = matches all address < 64K and where A[9:0] is in the
- * range 3B0-3BB or 3C0-3DF independen of the base & limit registers
- * [ 5: 5] ISA Enable
- * 0 = ISA matches Disabled
- * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block
- * from matching agains this base/limit pair
- * [11: 6] Reserved
- * [24:12] PCI I/O Base i
- * This field defines the start of PCI I/O region n
- * [31:25] Reserved
- */
- PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000003,
- PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000,
-
- /* Config Base and Limit i Registers
- * F1:0xE0 i = 0
- * F1:0xE4 i = 1
- * F1:0xE8 i = 2
- * F1:0xEC i = 3
- * [ 0: 0] Read Enable
- * 0 = Reads Disabled
- * 1 = Reads Enabled
- * [ 1: 1] Write Enable
- * 0 = Writes Disabled
- * 1 = Writes Enabled
- * [ 2: 2] Device Number Compare Enable
- * 0 = The ranges are based on bus number
- * 1 = The ranges are ranges of devices on bus 0
- * [ 3: 3] Reserved
- * [ 6: 4] Destination Node
- * 000 = Node 0
- * 001 = Node 1
- * 010 = Node 2
- * 011 = Node 3
- * 100 = Node 4
- * 101 = Node 5
- * 110 = Node 6
- * 111 = Node 7
- * [ 7: 7] Reserved
- * [ 9: 8] Destination Link
- * 00 = Link 0
- * 01 = Link 1
- * 10 = Link 2
- * 11 - Reserved
- * [15:10] Reserved
- * [23:16] Bus Number Base i
- * This field defines the lowest bus number in configuration region i
- * [31:24] Bus Number Limit i
- * This field defines the highest bus number in configuration regin i
- */
- PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x06000203, // AMD 8111 on link0 of CPU 0
- PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
- PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
- };
-
- int max;
- max = sizeof(register_values)/sizeof(register_values[0]);
- setup_resource_map(register_values, max);
-}
-
--- /dev/null
+##
+## Compute the location and size of where this firmware image
+## (linuxBIOS plus bootloader) will live in the boot rom chip.
+##
+if USE_FALLBACK_IMAGE
+ default ROM_SECTION_SIZE = FALLBACK_SIZE
+ default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
+else
+ default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
+ default ROM_SECTION_OFFSET = 0
+end
+
+##
+## Compute the start location and size size of
+## The linuxBIOS bootloader.
+##
+default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
+default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
+
+##
+## Compute where this copy of linuxBIOS will start in the boot rom
+##
+default _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
+
+##
+## Compute a range of ROM that can cached to speed up linuxBIOS,
+## execution speed.
+##
+## XIP_ROM_SIZE must be a power of 2.
+## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
+##
+default XIP_ROM_SIZE=65536
+default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
+
+##
+## Set all of the defaults for an x86 architecture
+##
+
+arch i386 end
+
+##
+## Build the objects we have code for in this directory.
+##
+
+driver mainboard.o
+if HAVE_MP_TABLE object mptable.o end
+if HAVE_PIRQ_TABLE object irq_tables.o end
+#object reset.o
+
+## ATI Rage XL framebuffering graphics driver
+dir /drivers/ati/ragexl
+
+##
+## Romcc output
+##
+makerule ./failover.E
+ depends "$(MAINBOARD)/failover.c ./romcc"
+ action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+end
+
+makerule ./failover.inc
+ depends "$(MAINBOARD)/failover.c ./romcc"
+ action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+end
+
+makerule ./auto.E
+ depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
+ action "./romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+end
+makerule ./auto.inc
+ depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
+ action "./romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+end
+
+##
+## Build our 16 bit and 32 bit linuxBIOS entry code
+##
+mainboardinit cpu/x86/16bit/entry16.inc
+mainboardinit cpu/x86/32bit/entry32.inc
+ldscript /cpu/x86/16bit/entry16.lds
+ldscript /cpu/x86/32bit/entry32.lds
+
+##
+## Build our reset vector (This is where linuxBIOS is entered)
+##
+if USE_FALLBACK_IMAGE
+ mainboardinit cpu/x86/16bit/reset16.inc
+ ldscript /cpu/x86/16bit/reset16.lds
+else
+ mainboardinit cpu/x86/32bit/reset32.inc
+ ldscript /cpu/x86/32bit/reset32.lds
+end
+
+### Should this be in the northbridge code?
+mainboardinit arch/i386/lib/cpu_reset.inc
+
+##
+## Include an id string (For safe flashing)
+##
+mainboardinit arch/i386/lib/id.inc
+ldscript /arch/i386/lib/id.lds
+
+###
+### This is the early phase of linuxBIOS startup
+### Things are delicate and we test to see if we should
+### failover to another image.
+###
+if USE_FALLBACK_IMAGE
+ ldscript /arch/i386/lib/failover.lds
+ mainboardinit ./failover.inc
+end
+
+###
+### O.k. We aren't just an intermediary anymore!
+###
+
+##
+## Setup RAM
+##
+mainboardinit cpu/x86/fpu/enable_fpu.inc
+mainboardinit cpu/x86/mmx/enable_mmx.inc
+mainboardinit cpu/x86/sse/enable_sse.inc
+mainboardinit ./auto.inc
+mainboardinit cpu/x86/sse/disable_sse.inc
+mainboardinit cpu/x86/mmx/disable_mmx.inc
+
+##
+## Include the secondary Configuration files
+##
+dir /pc80
+config chip.h
+
+# config for Iwill/DK8S2
+chip northbridge/amd/amdk8/root_complex
+ device pci_domain 0 on
+ chip northbridge/amd/amdk8
+ device pci 18.0 on # LDT 0
+ chip southbridge/amd/amd8131
+ device pci 0.0 on end
+ device pci 0.1 on end
+ device pci 1.0 on end
+ device pci 1.1 on end
+ end
+ chip southbridge/amd/amd8111
+ # this "device pci 0.0" is the parent the next one
+ # PCI bridge
+ device pci 0.0 on
+ device pci 0.0 on end
+ device pci 0.1 on end
+ device pci 0.2 on end
+ device pci 1.0 off end
+ end
+ device pci 1.0 on
+ chip superio/winbond/w83627hf
+ device pnp 2e.0 on # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 2e.1 off # Parallel Port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ end
+ device pnp 2e.2 on # Com1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.3 off # Com2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.5 on # Keyboard
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1
+ irq 0x72 = 12
+ end
+ device pnp 2e.6 off end # CIR
+ device pnp 2e.7 off end # GAME_MIDI_GIPO1
+ device pnp 2e.8 off end # GPIO2
+ device pnp 2e.9 off end # GPIO3
+ device pnp 2e.a off end # ACPI
+ device pnp 2e.b on # HW Monitor
+ io 0x60 = 0x290
+ end
+ register "com1" = "{1}"
+ # register "com1" = "{1, 0, 0x3f8, 4}"
+ # register "lpt" = "{1}"
+ end
+ end
+ device pci 1.1 on end
+ device pci 1.2 on end
+ device pci 1.3 on end
+ device pci 1.5 off end
+ device pci 1.6 off end
+ end
+ end # LDT0
+ device pci 18.0 on end # LDT1
+ device pci 18.0 on end # LDT2
+ device pci 18.1 on end
+ device pci 18.2 on end
+ device pci 18.3 on end
+ end
+ chip northbridge/amd/amdk8
+ device pci 19.0 on end
+ device pci 19.0 on end
+ device pci 19.0 on end
+ device pci 19.1 on end
+ device pci 19.2 on end
+ device pci 19.3 on end
+ end
+ end
+ device apic_cluster 0 on
+ chip cpu/amd/socket_940
+ device apic 0 on end
+ end
+ chip cpu/amd/socket_940
+ device apic 1 on end
+ end
+ end
+end
+
--- /dev/null
+uses HAVE_MP_TABLE
+uses HAVE_PIRQ_TABLE
+uses USE_FALLBACK_IMAGE
+uses HAVE_FALLBACK_BOOT
+uses HAVE_HARD_RESET
+uses IRQ_SLOT_COUNT
+uses HAVE_OPTION_TABLE
+uses CONFIG_MAX_CPUS
+uses CONFIG_MAX_PHYSICAL_CPUS
+uses CONFIG_IOAPIC
+uses CONFIG_SMP
+uses FALLBACK_SIZE
+uses ROM_SIZE
+uses ROM_SECTION_SIZE
+uses ROM_IMAGE_SIZE
+uses ROM_SECTION_SIZE
+uses ROM_SECTION_OFFSET
+uses CONFIG_ROM_STREAM
+uses CONFIG_ROM_STREAM_START
+uses PAYLOAD_SIZE
+uses _ROMBASE
+uses XIP_ROM_SIZE
+uses XIP_ROM_BASE
+uses STACK_SIZE
+uses HEAP_SIZE
+uses USE_OPTION_TABLE
+uses LB_CKS_RANGE_START
+uses LB_CKS_RANGE_END
+uses LB_CKS_LOC
+uses MAINBOARD
+uses MAINBOARD_PART_NUMBER
+uses MAINBOARD_VENDOR
+uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
+uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
+uses LINUXBIOS_EXTRA_VERSION
+uses _RAMBASE
+uses TTYS0_BAUD
+uses TTYS0_BASE
+uses TTYS0_LCS
+uses DEFAULT_CONSOLE_LOGLEVEL
+uses MAXIMUM_CONSOLE_LOGLEVEL
+uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
+uses CONFIG_CONSOLE_SERIAL8250
+uses HAVE_INIT_TIMER
+uses CONFIG_GDB_STUB
+uses CROSS_COMPILE
+uses CC
+uses HOSTCC
+uses OBJCOPY
+
+uses CONFIG_USE_INIT
+
+## ROM_SIZE is the size of boot ROM that this board will use.
+default ROM_SIZE=524288
+
+###
+### Build options
+###
+
+##
+## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
+##
+default FALLBACK_SIZE=0x40000
+
+##
+## Build code for the fallback boot
+##
+default HAVE_FALLBACK_BOOT=1
+
+##
+## Build code to reset the motherboard from linuxBIOS
+##
+default HAVE_HARD_RESET=1
+
+##
+## Build code to export a programmable irq routing table
+##
+default HAVE_PIRQ_TABLE=1
+default IRQ_SLOT_COUNT=9
+
+##
+## Build code to export an x86 MP table
+## Useful for specifying IRQ routing values
+##
+default HAVE_MP_TABLE=1
+
+##
+## Build code to export a CMOS option table
+##
+default HAVE_OPTION_TABLE=1
+
+##
+## Move the default LinuxBIOS cmos range off of AMD RTC registers
+##
+default LB_CKS_RANGE_START=49
+default LB_CKS_RANGE_END=122
+default LB_CKS_LOC=123
+
+##
+## Build code for SMP support
+## Only worry about 2 micro processors
+##
+default CONFIG_SMP=1
+default CONFIG_MAX_CPUS=2
+default CONFIG_MAX_PHYSICAL_CPUS=2
+
+##
+## Build code to setup a generic IOAPIC
+##
+default CONFIG_IOAPIC=1
+
+##
+## Clean up the motherboard id strings
+##
+default MAINBOARD_PART_NUMBER="HDAMA"
+default MAINBOARD_VENDOR="ARIMA"
+default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x161f
+default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3016
+
+
+###
+### LinuxBIOS layout values
+###
+
+## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+default ROM_IMAGE_SIZE = 65536
+
+##
+## Use a small 8K stack
+##
+default STACK_SIZE=0x2000
+
+##
+## Use a small 16K heap
+##
+default HEAP_SIZE=0x4000
+
+##
+## Only use the option table in a normal image
+##
+default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
+
+##
+## LinuxBIOS C code runs at this location in RAM
+##
+default _RAMBASE=0x00004000
+
+##
+## Load the payload from the ROM
+##
+default CONFIG_ROM_STREAM = 1
+
+###
+### Defaults of options that you may want to override in the target config file
+###
+
+##
+## The default compiler
+##
+#default CC="$(CROSS_COMPILE)gcc -m32"
+#default HOSTCC="gcc"
+
+##
+## Disable the gdb stub by default
+##
+default CONFIG_GDB_STUB=0
+
+##
+## The Serial Console
+##
+
+# To Enable the Serial Console
+default CONFIG_CONSOLE_SERIAL8250=1
+
+## Select the serial console baud rate
+default TTYS0_BAUD=115200
+#default TTYS0_BAUD=57600
+#default TTYS0_BAUD=38400
+#default TTYS0_BAUD=19200
+#default TTYS0_BAUD=9600
+#default TTYS0_BAUD=4800
+#default TTYS0_BAUD=2400
+#default TTYS0_BAUD=1200
+
+# Select the serial console base port
+default TTYS0_BASE=0x3f8
+
+# Select the serial protocol
+# This defaults to 8 data bits, 1 stop bit, and no parity
+default TTYS0_LCS=0x3
+
+##
+### Select the linuxBIOS loglevel
+##
+## EMERG 1 system is unusable
+## ALERT 2 action must be taken immediately
+## CRIT 3 critical conditions
+## ERR 4 error conditions
+## WARNING 5 warning conditions
+## NOTICE 6 normal but significant condition
+## INFO 7 informational
+## DEBUG 8 debug-level messages
+## SPEW 9 Way too many details
+
+## Request this level of debugging output
+default DEFAULT_CONSOLE_LOGLEVEL=8
+## At a maximum only compile in this level of debugging
+default MAXIMUM_CONSOLE_LOGLEVEL=8
+
+##
+## Select power on after power fail setting
+default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
+
+### End Options.lb
+end
--- /dev/null
+#define ASSEMBLY 1
+#include <stdint.h>
+#include <device/pci_def.h>
+#include <arch/io.h>
+#include <device/pnp_def.h>
+#include <arch/romcc_io.h>
+#include <cpu/x86/lapic.h>
+#include <arch/cpu.h>
+#include "option_table.h"
+#include "pc80/mc146818rtc_early.c"
+#include "pc80/serial.c"
+#include "arch/i386/lib/console.c"
+#include "ram/ramtest.c"
+#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
+#include "northbridge/amd/amdk8/raminit.h"
+#include "cpu/amd/model_fxx/apic_timer.c"
+#include "lib/delay.c"
+#include "cpu/x86/lapic/boot_cpu.c"
+#include "northbridge/amd/amdk8/reset_test.c"
+#include "northbridge/amd/amdk8/debug.c"
+#include <cpu/amd/model_fxx_rev.h>
+#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
+#include "cpu/amd/mtrr/amd_earlymtrr.c"
+#include "cpu/x86/bist.h"
+
+
+#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
+
+static void hard_reset(void)
+{
+ set_bios_reset();
+
+ /* enable cf9 */
+ pci_write_config8(PCI_DEV(0, 0x04, 3), 0x41, 0xf1);
+ /* reset */
+ outb(0x0e, 0x0cf9);
+}
+
+static void soft_reset(void)
+{
+ set_bios_reset();
+ pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1);
+}
+
+/*
+ * GPIO28 of 8111 will control H0_MEMRESET_L
+ * GPIO29 of 8111 will control H1_MEMRESET_L
+ */
+static void memreset_setup(void)
+{
+ if (is_cpu_pre_c0()) {
+ /* Set the memreset low */
+ outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
+ /* Ensure the BIOS has control of the memory lines */
+ outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
+ } else {
+ /* Ensure the CPU has controll of the memory lines */
+ outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29);
+ }
+}
+
+static void memreset(int controllers, const struct mem_controller *ctrl)
+{
+ if (is_cpu_pre_c0()) {
+ udelay(800);
+ /* Set memreset_high */
+ outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
+ udelay(90);
+ }
+}
+
+static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes)
+{
+ /* Routing Table Node i
+ *
+ * F0: 0x40, 0x44, 0x48, 0x4c, 0x50, 0x54, 0x58, 0x5c
+ * i: 0, 1, 2, 3, 4, 5, 6, 7
+ *
+ * [ 0: 3] Request Route
+ * [0] Route to this node
+ * [1] Route to Link 0
+ * [2] Route to Link 1
+ * [3] Route to Link 2
+ * [11: 8] Response Route
+ * [0] Route to this node
+ * [1] Route to Link 0
+ * [2] Route to Link 1
+ * [3] Route to Link 2
+ * [19:16] Broadcast route
+ * [0] Route to this node
+ * [1] Route to Link 0
+ * [2] Route to Link 1
+ * [3] Route to Link 2
+ */
+
+ uint32_t ret=0x00010101; /* default row entry */
+
+ static const unsigned int rows_2p[2][2] = {
+ { 0x00050101, 0x00010404 },
+ { 0x00010404, 0x00050101 }
+ };
+
+ if(maxnodes>2) {
+ print_debug("this mainboard is only designed for 2 cpus\r\n");
+ maxnodes=2;
+ }
+
+ if (!(node>=maxnodes || row>=maxnodes)) {
+ ret=rows_2p[node][row];
+ }
+
+ return ret;
+}
+
+static inline void activate_spd_rom(const struct mem_controller *ctrl)
+{
+ /* nothing to do */
+}
+
+static inline int spd_read_byte(unsigned device, unsigned address)
+{
+ return smbus_read_byte(device, address);
+}
+
+#include "northbridge/amd/amdk8/raminit.c"
+#include "northbridge/amd/amdk8/coherent_ht.c"
+#include "northbridge/amd/amdk8/incoherent_ht.c"
+#include "sdram/generic_sdram.c"
+#include "northbridge/amd/amdk8/resourcemap.c"
+#include "cpu/amd/dualcore/dualcore.c"
+
+#define FIRST_CPU 1
+#define SECOND_CPU 1
+#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
+static void main(unsigned long bist)
+{
+ static const struct mem_controller cpu[] = {
+#if FIRST_CPU
+ {
+ .node_id = 0,
+ .f0 = PCI_DEV(0, 0x18, 0),
+ .f1 = PCI_DEV(0, 0x18, 1),
+ .f2 = PCI_DEV(0, 0x18, 2),
+ .f3 = PCI_DEV(0, 0x18, 3),
+ .channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
+ .channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
+ },
+#endif
+#if SECOND_CPU
+ {
+ .node_id = 1,
+ .f0 = PCI_DEV(0, 0x19, 0),
+ .f1 = PCI_DEV(0, 0x19, 1),
+ .f2 = PCI_DEV(0, 0x19, 2),
+ .f3 = PCI_DEV(0, 0x19, 3),
+ .channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
+ .channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
+ },
+#endif
+ };
+
+ int needs_reset;
+ unsigned nodeid;
+
+ if (bist == 0) {
+ k8_init_and_stop_secondaries();
+ }
+ /* Setup the console */
+ w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
+ uart_init();
+ console_init();
+
+ /* Halt if there was a built in self test failure */
+ report_bist_failure(bist);
+
+ setup_default_resource_map();
+ needs_reset = setup_coherent_ht_domain();
+ needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80);
+ if (needs_reset) {
+ print_info("ht reset -\r\n");
+ soft_reset();
+ }
+
+#if 0
+ print_pci_devices();
+#endif
+
+ enable_smbus();
+
+#if 0
+ dump_spd_registers(&cpu[0]);
+#endif
+
+ memreset_setup();
+ sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
+
+#if 0
+ dump_pci_devices();
+ dump_pci_device(PCI_DEV(0, 0x18, 2));
+#endif
+}
--- /dev/null
+extern struct chip_operations mainboard_Iwill_DK8S2_ops;
+
+struct mainboard_Iwill_DK8S2_config {
+ int nothing;
+};
--- /dev/null
+entries
+
+#start-bit length config config-ID name
+#0 8 r 0 seconds
+#8 8 r 0 alarm_seconds
+#16 8 r 0 minutes
+#24 8 r 0 alarm_minutes
+#32 8 r 0 hours
+#40 8 r 0 alarm_hours
+#48 8 r 0 day_of_week
+#56 8 r 0 day_of_month
+#64 8 r 0 month
+#72 8 r 0 year
+#80 4 r 0 rate_select
+#84 3 r 0 REF_Clock
+#87 1 r 0 UIP
+#88 1 r 0 auto_switch_DST
+#89 1 r 0 24_hour_mode
+#90 1 r 0 binary_values_enable
+#91 1 r 0 square-wave_out_enable
+#92 1 r 0 update_finished_enable
+#93 1 r 0 alarm_interrupt_enable
+#94 1 r 0 periodic_interrupt_enable
+#95 1 r 0 disable_clock_updates
+#96 288 r 0 temporary_filler
+0 384 r 0 reserved_memory
+384 1 e 4 boot_option
+385 1 e 4 last_boot
+386 1 e 1 ECC_memory
+388 4 r 0 reboot_bits
+392 3 e 5 baud_rate
+395 1 e 1 hw_scrubber
+396 1 e 1 interleave_chip_selects
+397 2 e 8 max_mem_clock
+399 1 e 2 dual_core
+400 1 e 1 power_on_after_fail
+412 4 e 6 debug_level
+416 4 e 7 boot_first
+420 4 e 7 boot_second
+424 4 e 7 boot_third
+428 4 h 0 boot_index
+432 8 h 0 boot_countdown
+440 4 e 9 slow_cpu
+444 1 e 1 nmi
+445 1 e 1 iommu
+728 256 h 0 user_data
+984 16 h 0 check_sum
+# Reserve the extended AMD configuration registers
+1000 24 r 0 reserved_memory
+
+
+
+enumerations
+
+#ID value text
+1 0 Disable
+1 1 Enable
+2 0 Enable
+2 1 Disable
+4 0 Fallback
+4 1 Normal
+5 0 115200
+5 1 57600
+5 2 38400
+5 3 19200
+5 4 9600
+5 5 4800
+5 6 2400
+5 7 1200
+6 6 Notice
+6 7 Info
+6 8 Debug
+6 9 Spew
+7 0 Network
+7 1 HDD
+7 2 Floppy
+7 8 Fallback_Network
+7 9 Fallback_HDD
+7 10 Fallback_Floppy
+#7 3 ROM
+8 0 DDR400
+8 1 DDR333
+8 2 DDR266
+8 3 DDR200
+9 0 off
+9 1 87.5%
+9 2 75.0%
+9 3 62.5%
+9 4 50.0%
+9 5 37.5%
+9 6 25.0%
+9 7 12.5%
+
+checksums
+
+checksum 392 983 984
+
+
--- /dev/null
+#define ASSEMBLY 1
+#include <stdint.h>
+#include <device/pci_def.h>
+#include <device/pci_ids.h>
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <cpu/x86/lapic.h>
+#include "pc80/mc146818rtc_early.c"
+#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
+#include "northbridge/amd/amdk8/early_ht.c"
+#include "cpu/x86/lapic/boot_cpu.c"
+#include "cpu/x86/mtrr/earlymtrr.c"
+#include "northbridge/amd/amdk8/reset_test.c"
+
+static unsigned long main(unsigned long bist)
+{
+ unsigned nodeid;
+
+ /* Make cerain my local apic is useable */
+ enable_lapic();
+
+ /* Is this a cpu only reset? */
+ if (early_mtrr_init_detected()) {
+ if (last_boot_normal()) {
+ goto normal_image;
+ } else {
+ goto fallback_image;
+ }
+ }
+ /* Is this a secondary cpu? */
+ if (!boot_cpu()) {
+ if (last_boot_normal()) {
+ goto normal_image;
+ } else {
+ goto fallback_image;
+ }
+ }
+
+
+ /* Nothing special needs to be done to find bus 0 */
+ /* Allow the HT devices to be found */
+ enumerate_ht_chain();
+
+ /* Setup the 8111 */
+ amd8111_enable_rom();
+
+ /* Is this a deliberate reset by the bios */
+ if (bios_reset_detected() && last_boot_normal()) {
+ goto normal_image;
+ }
+ /* This is the primary cpu how should I boot? */
+ else if (do_normal_boot()) {
+ goto normal_image;
+ }
+ else {
+ goto fallback_image;
+ }
+ normal_image:
+ asm volatile ("jmp __normal_image"
+ : /* outputs */
+ : "a" (bist) /* inputs */
+ : /* clobbers */
+ );
+ fallback_image:
+ return bist;
+}
--- /dev/null
+/* This file was generated by getpir.c, do not modify!
+ (but if you do, please run checkpir on it to verify)
+ * Contains the IRQ Routing Table dumped directly from your memory, which BIOS sets up
+ *
+ * Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM
+*/
+
+#include <arch/pirq_routing.h>
+
+const struct irq_routing_table intel_irq_routing_table = {
+ PIRQ_SIGNATURE, /* u32 signature */
+ PIRQ_VERSION, /* u16 version */
+ 32+16*12, /* there can be total 12 devices on the bus */
+ 0x00, /* Where the interrupt router lies (bus) */
+ (0x07<<3)|0x3, /* Where the interrupt router lies (dev) */
+ 0, /* IRQs devoted exclusively to PCI usage */
+ 0x1022, /* Vendor */
+ 0x746b, /* Device */
+ 0, /* Crap (miniport) */
+ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
+ 0x6d, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
+ {
+ /* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
+ {0x00,(0x07<<3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x04, 0x0def8}}, 0x0, 0x0},
+ {0x03,(0x00<<3)|0x0, {{0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}, {0x04, 0x0def8}}, 0x0, 0x0},
+ {0x02,(0x01<<3)|0x0, {{0x02, 0xdef8}, {0x03, 0xdef8}, {0x04, 0xdef8}, {0x01, 0x0def8}}, 0x1, 0x0},
+ {0x02,(0x02<<3)|0x0, {{0x03, 0xdef8}, {0x04, 0xdef8}, {0x01, 0xdef8}, {0x02, 0x0def8}}, 0x2, 0x0},
+ {0x01,(0x01<<3)|0x0, {{0x02, 0xdef8}, {0x03, 0xdef8}, {0x04, 0xdef8}, {0x01, 0x0def8}}, 0x3, 0x0},
+ {0x01,(0x02<<3)|0x0, {{0x03, 0xdef8}, {0x04, 0xdef8}, {0x01, 0xdef8}, {0x02, 0x0def8}}, 0x4, 0x0},
+ {0x03,(0x04<<3)|0x0, {{0x01, 0xdef8}, {0x02, 0xdef8}, {0x03, 0xdef8}, {0x04, 0x0def8}}, 0x5, 0x0},
+ {0x03,(0x05<<3)|0x0, {{0x02, 0xdef8}, {0x03, 0xdef8}, {0x04, 0xdef8}, {0x01, 0x0def8}}, 0x6, 0x0},
+ {0x03,(0x06<<3)|0x0, {{0x03, 0xdef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
+ {0x02,(0x03<<3)|0x0, {{0x04, 0xdef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
+ {0x02,(0x04<<3)|0x0, {{0x01, 0xdef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
+ {0x02,(0x05<<3)|0x0, {{0x02, 0xdef8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x00000}}, 0x0, 0x0},
+ }
+};
+unsigned long write_pirq_routing_table(unsigned long addr)
+{
+ return copy_pirq_routing_table(addr);
+}
--- /dev/null
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include "chip.h"
+
+struct chip_operations mainboard_Iwill_DK8S2_ops = {
+ CHIP_NAME("Iwill DK8S2 mainboard")
+};
+
--- /dev/null
+#include <console/console.h>
+#include <arch/smp/mpspec.h>
+#include <device/pci.h>
+#include <string.h>
+#include <stdint.h>
+
+void *smp_write_config_table(void *v)
+{
+ static const char sig[4] = "PCMP";
+ static const char oem[8] = "IWILL ";
+ static const char productid[12] = "DK8X ";
+ struct mp_config_table *mc;
+ unsigned char bus_num;
+ unsigned char bus_isa;
+ unsigned char bus_8131_1;
+ unsigned char bus_8131_2;
+ unsigned char bus_8111_1;
+
+ mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
+ memset(mc, 0, sizeof(*mc));
+
+ memcpy(mc->mpc_signature, sig, sizeof(sig));
+ mc->mpc_length = sizeof(*mc); /* initially just the header */
+ mc->mpc_spec = 0x04;
+ mc->mpc_checksum = 0; /* not yet computed */
+ memcpy(mc->mpc_oem, oem, sizeof(oem));
+ memcpy(mc->mpc_productid, productid, sizeof(productid));
+ mc->mpc_oemptr = 0;
+ mc->mpc_oemsize = 0;
+ mc->mpc_entry_count = 0; /* No entries yet... */
+ mc->mpc_lapic = LAPIC_ADDR;
+ mc->mpe_length = 0;
+ mc->mpe_checksum = 0;
+ mc->reserved = 0;
+
+ smp_write_processors(mc);
+
+ {
+ device_t dev;
+
+ /* 8111 */
+ dev = dev_find_slot(1, PCI_DEVFN(0x03,0));
+ if (dev) {
+ bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
+ bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
+ bus_isa++;
+ }
+ else {
+ printk_debug("ERROR - could not find PCI 1:03.0, using defaults\n");
+
+ bus_8111_1 = 4;
+ bus_isa = 5;
+ }
+ /* 8131-1 */
+ dev = dev_find_slot(1, PCI_DEVFN(0x01,0));
+ if (dev) {
+ bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
+
+ }
+ else {
+ printk_debug("ERROR - could not find PCI 1:01.0, using defaults\n");
+
+ bus_8131_1 = 2;
+ }
+ /* 8131-2 */
+ dev = dev_find_slot(1, PCI_DEVFN(0x02,0));
+ if (dev) {
+ bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
+
+ }
+ else {
+ printk_debug("ERROR - could not find PCI 1:02.0, using defaults\n");
+
+ bus_8131_2 = 3;
+ }
+ }
+
+ /* define bus and isa numbers */
+ for(bus_num = 0; bus_num < bus_isa; bus_num++) {
+ smp_write_bus(mc, bus_num, "PCI ");
+ }
+ smp_write_bus(mc, bus_isa, "ISA ");
+
+ /* IOAPIC handling */
+ smp_write_ioapic(mc, 2, 0x11, 0xfec00000);
+ {
+ device_t dev;
+ struct resource *res;
+ /* 8131 apic 3 */
+ dev = dev_find_slot(1, PCI_DEVFN(0x01,1));
+ if (dev) {
+ res = find_resource(dev, PCI_BASE_ADDRESS_0);
+ if (res) {
+ smp_write_ioapic(mc, 0x03, 0x11, res->base);
+ }
+ }
+ /* 8131 apic 4 */
+ dev = dev_find_slot(1, PCI_DEVFN(0x02,1));
+ if (dev) {
+ res = find_resource(dev, PCI_BASE_ADDRESS_0);
+ if (res) {
+ smp_write_ioapic(mc, 0x04, 0x11, res->base);
+ }
+ }
+ }
+
+ /* ISA backward compatibility interrupts */
+ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_isa, 0x00, 0x02, 0x00);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_isa, 0x01, 0x02, 0x01);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_isa, 0x00, 0x02, 0x02);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_isa, 0x03, 0x02, 0x03);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_isa, 0x04, 0x02, 0x04);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_isa, 0x05, 0x02, 0x05);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_isa, 0x06, 0x02, 0x06);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_isa, 0x07, 0x02, 0x07);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_isa, 0x08, 0x02, 0x08);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_isa, 0x09, 0x02, 0x09);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_isa, 0x0a, 0x02, 0x0a);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_isa, 0x0b, 0x02, 0x0b);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_isa, 0x0c, 0x02, 0x0c);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_isa, 0x0d, 0x02, 0x0d);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_isa, 0x0e, 0x02, 0x0e);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_isa, 0x0f, 0x02, 0x0f);
+
+ /* Standard local interrupt assignments */
+ smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_isa, 0x00, MP_APIC_ALL, 0x00);
+ smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_isa, 0x00, MP_APIC_ALL, 0x01);
+
+
+ /* PCI Slot 1 */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_8131_2, (1<<2)|0, 0x02, 0x11);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_8131_2, (1<<2)|1, 0x02, 0x12);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_8131_2, (1<<2)|2, 0x02, 0x13);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_8131_2, (1<<2)|3, 0x02, 0x10);
+
+ /* PCI Slot 2 */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_8131_2, (2<<2)|0, 0x02, 0x12);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_8131_2, (2<<2)|1, 0x02, 0x13);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_8131_2, (2<<2)|2, 0x02, 0x10);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_8131_2, (2<<2)|3, 0x02, 0x11);
+
+ /* PCI Slot 3 */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_8131_1, (1<<2)|0, 0x02, 0x11);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_8131_1, (1<<2)|1, 0x02, 0x12);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_8131_1, (1<<2)|2, 0x02, 0x13);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_8131_1, (1<<2)|3, 0x02, 0x10);
+
+ /* PCI Slot 4 */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_8131_1, (2<<2)|0, 0x02, 0x12);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_8131_1, (2<<2)|1, 0x02, 0x13);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_8131_1, (2<<2)|2, 0x02, 0x10);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_8131_1, (2<<2)|3, 0x02, 0x11);
+
+ /* PCI Slot 5 */
+#warning "FIXME get the irqs right, it's just hacked to work for now"
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_8111_1, (5<<2)|0, 0x02, 0x11);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_8111_1, (5<<2)|1, 0x02, 0x12);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_8111_1, (5<<2)|2, 0x02, 0x13);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_8111_1, (5<<2)|3, 0x02, 0x10);
+
+ /* PCI Slot 6 */
+#warning "FIXME get the irqs right, it's just hacked to work for now"
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_8111_1, (4<<2)|0, 0x02, 0x10);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_8111_1, (4<<2)|1, 0x02, 0x11);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_8111_1, (4<<2)|2, 0x02, 0x12);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_8111_1, (4<<2)|3, 0x02, 0x13);
+
+ /* On board nics */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_8131_1, (3<<2)|0, 0x02, 0x13);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_8131_1, (4<<2)|0, 0x02, 0x13);
+
+ /* There is no extension information... */
+
+ /* Compute the checksums */
+ mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
+ mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
+ printk_debug("Wrote the mp table end at: %p - %p\n",
+ mc, smp_next_mpe_entry(mc));
+ return smp_next_mpe_entry(mc);
+}
+
+unsigned long write_smp_table(unsigned long addr)
+{
+ void *v;
+ v = smp_write_floating_table(addr);
+ return (unsigned long)smp_write_config_table(v);
+}
+
--- /dev/null
+#include "../../../southbridge/amd/amd8111/amd8111_reset.c"
+
+void hard_reset(void)
+{
+ amd8111_hard_reset(0, 0);
+}
--- /dev/null
+##
+## Compute the location and size of where this firmware image
+## (linuxBIOS plus bootloader) will live in the boot rom chip.
+##
+if USE_FALLBACK_IMAGE
+ default ROM_SECTION_SIZE = FALLBACK_SIZE
+ default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )
+else
+ default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )
+ default ROM_SECTION_OFFSET = 0
+end
+
+##
+## Compute the start location and size size of
+## The linuxBIOS bootloader.
+##
+default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
+default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
+
+##
+## Compute where this copy of linuxBIOS will start in the boot rom
+##
+default _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
+
+##
+## Compute a range of ROM that can cached to speed up linuxBIOS,
+## execution speed.
+##
+## XIP_ROM_SIZE must be a power of 2.
+## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
+##
+default XIP_ROM_SIZE=65536
+default XIP_ROM_BASE = ( _ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE )
+
+##
+## Set all of the defaults for an x86 architecture
+##
+
+arch i386 end
+
+##
+## Build the objects we have code for in this directory.
+##
+
+driver mainboard.o
+if HAVE_MP_TABLE object mptable.o end
+if HAVE_PIRQ_TABLE object irq_tables.o end
+#object reset.o
+
+##
+## Romcc output
+##
+makerule ./failover.E
+ depends "$(MAINBOARD)/failover.c ./romcc"
+ action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+end
+
+makerule ./failover.inc
+ depends "$(MAINBOARD)/failover.c ./romcc"
+ action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"
+end
+
+makerule ./auto.E
+ depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
+ action "./romcc -E -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+end
+makerule ./auto.inc
+ depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
+ action "./romcc -mcpu=k8 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
+end
+
+##
+## Build our 16 bit and 32 bit linuxBIOS entry code
+##
+mainboardinit cpu/x86/16bit/entry16.inc
+mainboardinit cpu/x86/32bit/entry32.inc
+ldscript /cpu/x86/16bit/entry16.lds
+ldscript /cpu/x86/32bit/entry32.lds
+
+##
+## Build our reset vector (This is where linuxBIOS is entered)
+##
+if USE_FALLBACK_IMAGE
+ mainboardinit cpu/x86/16bit/reset16.inc
+ ldscript /cpu/x86/16bit/reset16.lds
+else
+ mainboardinit cpu/x86/32bit/reset32.inc
+ ldscript /cpu/x86/32bit/reset32.lds
+end
+
+### Should this be in the northbridge code?
+mainboardinit arch/i386/lib/cpu_reset.inc
+
+##
+## Include an id string (For safe flashing)
+##
+mainboardinit arch/i386/lib/id.inc
+ldscript /arch/i386/lib/id.lds
+
+###
+### This is the early phase of linuxBIOS startup
+### Things are delicate and we test to see if we should
+### failover to another image.
+###
+if USE_FALLBACK_IMAGE
+ ldscript /arch/i386/lib/failover.lds
+ mainboardinit ./failover.inc
+end
+
+###
+### O.k. We aren't just an intermediary anymore!
+###
+
+##
+## Setup RAM
+##
+mainboardinit cpu/x86/fpu/enable_fpu.inc
+mainboardinit cpu/x86/mmx/enable_mmx.inc
+mainboardinit cpu/x86/sse/enable_sse.inc
+mainboardinit ./auto.inc
+mainboardinit cpu/x86/sse/disable_sse.inc
+mainboardinit cpu/x86/mmx/disable_mmx.inc
+
+##
+## Include the secondary Configuration files
+##
+dir /pc80
+config chip.h
+
+chip northbridge/amd/amdk8/root_complex
+ device pci_domain 0 on
+ chip northbridge/amd/amdk8
+ device pci 18.0 on # northbridge
+ # devices on link 0, link 0 == LDT 0
+ chip southbridge/amd/amd8131
+ # the on/off keyword is mandatory
+ device pci 0.0 on end
+ device pci 0.1 on end
+ device pci 1.0 on end
+ device pci 1.1 on end
+ end
+ chip southbridge/amd/amd8111
+ # this "device pci 0.0" is the parent the next one
+ # PCI bridge
+ device pci 0.0 on
+ device pci 0.0 on end
+ device pci 0.1 on end
+ device pci 0.2 on end
+ device pci 1.0 off end
+ end
+ device pci 1.0 on
+ chip superio/winbond/w83627thf
+ device pnp 2e.0 on end
+ device pnp 2e.1 on end
+ device pnp 2e.2 on end
+ device pnp 2e.3 on end
+ device pnp 2e.4 on end
+ device pnp 2e.5 on end
+ device pnp 2e.6 on end
+ device pnp 2e.7 on end
+ device pnp 2e.8 on end
+ device pnp 2e.9 on end
+ device pnp 2e.a on end
+ end
+ end
+ device pci 1.1 on end
+ device pci 1.2 on end
+ device pci 1.3 on end
+ device pci 1.5 off end
+ device pci 1.6 off end
+ end
+ end # LDT0
+ device pci 18.0 on end # LDT1
+ device pci 18.0 on end # LDT2
+ device pci 18.1 on end
+ device pci 18.2 on end
+ device pci 18.3 on end
+ end
+ chip northbridge/amd/amdk8
+ device pci 19.0 on end
+ device pci 19.0 on end
+ device pci 19.0 on end
+ device pci 19.1 on end
+ device pci 19.2 on end
+ device pci 19.3 on end
+ end
+ end
+ device apic_cluster 0 on
+ chip cpu/amd/socket_940
+ device apic 0 on end
+ end
+ chip cpu/amd/socket_940
+ device apic 1 on end
+ end
+ end
+end
+
--- /dev/null
+uses HAVE_MP_TABLE
+uses HAVE_PIRQ_TABLE
+uses USE_FALLBACK_IMAGE
+uses HAVE_FALLBACK_BOOT
+uses HAVE_HARD_RESET
+uses IRQ_SLOT_COUNT
+uses HAVE_OPTION_TABLE
+uses CONFIG_MAX_CPUS
+uses CONFIG_MAX_PHYSICAL_CPUS
+uses CONFIG_IOAPIC
+uses CONFIG_SMP
+uses FALLBACK_SIZE
+uses ROM_SIZE
+uses ROM_SECTION_SIZE
+uses ROM_IMAGE_SIZE
+uses ROM_SECTION_SIZE
+uses ROM_SECTION_OFFSET
+uses CONFIG_ROM_STREAM
+uses CONFIG_ROM_STREAM_START
+uses PAYLOAD_SIZE
+uses _ROMBASE
+uses XIP_ROM_SIZE
+uses XIP_ROM_BASE
+uses STACK_SIZE
+uses HEAP_SIZE
+uses USE_OPTION_TABLE
+uses LB_CKS_RANGE_START
+uses LB_CKS_RANGE_END
+uses LB_CKS_LOC
+uses MAINBOARD
+uses MAINBOARD_PART_NUMBER
+uses MAINBOARD_VENDOR
+uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
+uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
+uses LINUXBIOS_EXTRA_VERSION
+uses _RAMBASE
+uses TTYS0_BAUD
+uses TTYS0_BASE
+uses TTYS0_LCS
+uses DEFAULT_CONSOLE_LOGLEVEL
+uses MAXIMUM_CONSOLE_LOGLEVEL
+uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
+uses CONFIG_CONSOLE_SERIAL8250
+uses HAVE_INIT_TIMER
+uses CONFIG_GDB_STUB
+uses CROSS_COMPILE
+uses CC
+uses HOSTCC
+uses OBJCOPY
+
+uses CONFIG_USE_INIT
+
+## ROM_SIZE is the size of boot ROM that this board will use.
+default ROM_SIZE=524288
+
+###
+### Build options
+###
+
+##
+## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
+##
+default FALLBACK_SIZE=131072
+
+##
+## Build code for the fallback boot
+##
+default HAVE_FALLBACK_BOOT=1
+
+##
+## Build code to reset the motherboard from linuxBIOS
+##
+default HAVE_HARD_RESET=1
+
+##
+## Build code to export a programmable irq routing table
+##
+default HAVE_PIRQ_TABLE=1
+default IRQ_SLOT_COUNT=9
+
+##
+## Build code to export an x86 MP table
+## Useful for specifying IRQ routing values
+##
+default HAVE_MP_TABLE=1
+
+##
+## Build code to export a CMOS option table
+##
+default HAVE_OPTION_TABLE=1
+
+##
+## Move the default LinuxBIOS cmos range off of AMD RTC registers
+##
+default LB_CKS_RANGE_START=49
+default LB_CKS_RANGE_END=122
+default LB_CKS_LOC=123
+
+##
+## Build code for SMP support
+## Only worry about 2 micro processors
+##
+default CONFIG_SMP=1
+default CONFIG_MAX_CPUS=2
+default CONFIG_MAX_PHYSICAL_CPUS=2
+
+##
+## Build code to setup a generic IOAPIC
+##
+default CONFIG_IOAPIC=1
+
+##
+## Clean up the motherboard id strings
+##
+#default MAINBOARD_PART_NUMBER="HDAMA"
+#default MAINBOARD_VENDOR="ARIMA"
+#default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x161f
+#default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x3016
+
+###
+### LinuxBIOS layout values
+###
+
+## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+default ROM_IMAGE_SIZE = 65536
+
+##
+## Use a small 8K stack
+##
+default STACK_SIZE=0x2000
+
+##
+## Use a small 16K heap
+##
+default HEAP_SIZE=0x4000
+
+##
+## Only use the option table in a normal image
+##
+default USE_OPTION_TABLE = !USE_FALLBACK_IMAGE
+
+##
+## LinuxBIOS C code runs at this location in RAM
+##
+default _RAMBASE=0x00004000
+
+##
+## Load the payload from the ROM
+##
+default CONFIG_ROM_STREAM = 1
+
+###
+### Defaults of options that you may want to override in the target config file
+###
+
+##
+## The default compiler
+##
+#default CC="$(CROSS_COMPILE)gcc -m32"
+#default HOSTCC="gcc"
+
+##
+## Disable the gdb stub by default
+##
+default CONFIG_GDB_STUB=0
+
+##
+## The Serial Console
+##
+
+# To Enable the Serial Console
+default CONFIG_CONSOLE_SERIAL8250=1
+
+## Select the serial console baud rate
+default TTYS0_BAUD=115200
+#default TTYS0_BAUD=57600
+#default TTYS0_BAUD=38400
+#default TTYS0_BAUD=19200
+#default TTYS0_BAUD=9600
+#default TTYS0_BAUD=4800
+#default TTYS0_BAUD=2400
+#default TTYS0_BAUD=1200
+
+# Select the serial console base port
+default TTYS0_BASE=0x3f8
+
+# Select the serial protocol
+# This defaults to 8 data bits, 1 stop bit, and no parity
+default TTYS0_LCS=0x3
+
+##
+### Select the linuxBIOS loglevel
+##
+## EMERG 1 system is unusable
+## ALERT 2 action must be taken immediately
+## CRIT 3 critical conditions
+## ERR 4 error conditions
+## WARNING 5 warning conditions
+## NOTICE 6 normal but significant condition
+## INFO 7 informational
+## DEBUG 8 debug-level messages
+## SPEW 9 Way too many details
+
+## Request this level of debugging output
+default DEFAULT_CONSOLE_LOGLEVEL=8
+## At a maximum only compile in this level of debugging
+default MAXIMUM_CONSOLE_LOGLEVEL=8
+
+##
+## Select power on after power fail setting
+default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
+
+### End Options.lb
+end
--- /dev/null
+#define ASSEMBLY 1
+#include <stdint.h>
+#include <device/pci_def.h>
+#include <arch/io.h>
+#include <device/pnp_def.h>
+#include <arch/romcc_io.h>
+#include <cpu/x86/lapic.h>
+#include <arch/cpu.h>
+#include "option_table.h"
+#include "pc80/mc146818rtc_early.c"
+#include "pc80/serial.c"
+#include "arch/i386/lib/console.c"
+#include "ram/ramtest.c"
+#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
+#include "northbridge/amd/amdk8/raminit.h"
+#include "cpu/amd/model_fxx/apic_timer.c"
+#include "lib/delay.c"
+#include "cpu/x86/lapic/boot_cpu.c"
+#include "northbridge/amd/amdk8/reset_test.c"
+#include "northbridge/amd/amdk8/debug.c"
+#include <cpu/amd/model_fxx_rev.h>
+
+#include "superio/NSC/pc87360/pc87360_early_serial.c"
+#include "cpu/amd/mtrr/amd_earlymtrr.c"
+#include "cpu/x86/bist.h"
+
+#define SERIAL_DEV PNP_DEV(0x2e, PC87360_SP1)
+
+static void hard_reset(void)
+{
+ set_bios_reset();
+
+ /* enable cf9 */
+ pci_write_config8(PCI_DEV(0, 0x04, 3), 0x41, 0xf1);
+ /* reset */
+ outb(0x0e, 0x0cf9);
+}
+
+static void soft_reset(void)
+{
+ set_bios_reset();
+ pci_write_config8(PCI_DEV(0, 0x04, 0), 0x47, 1);
+}
+
+/*
+ * GPIO28 of 8111 will control H0_MEMRESET_L
+ * GPIO29 of 8111 will control H1_MEMRESET_L
+ */
+static void memreset_setup(void)
+{
+ if (is_cpu_pre_c0()) {
+ /* Set the memreset low */
+ outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
+ /* Ensure the BIOS has control of the memory lines */
+ outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
+ }
+ else {
+ /* Ensure the CPU has controll of the memory lines */
+ outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29);
+ }
+}
+
+static void memreset(int controllers, const struct mem_controller *ctrl)
+{
+ if (is_cpu_pre_c0()) {
+ udelay(800);
+ /* Set memreset_high */
+ outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
+ udelay(90);
+ }
+}
+
+static unsigned int generate_row(uint8_t node, uint8_t row, uint8_t maxnodes)
+{
+ /* Routing Table Node i
+ *
+ * F0: 0x40, 0x44, 0x48, 0x4c, 0x50, 0x54, 0x58, 0x5c
+ * i: 0, 1, 2, 3, 4, 5, 6, 7
+ *
+ * [ 0: 3] Request Route
+ * [0] Route to this node
+ * [1] Route to Link 0
+ * [2] Route to Link 1
+ * [3] Route to Link 2
+ * [11: 8] Response Route
+ * [0] Route to this node
+ * [1] Route to Link 0
+ * [2] Route to Link 1
+ * [3] Route to Link 2
+ * [19:16] Broadcast route
+ * [0] Route to this node
+ * [1] Route to Link 0
+ * [2] Route to Link 1
+ * [3] Route to Link 2
+ */
+
+ uint32_t ret=0x00010101; /* default row entry */
+
+ static const unsigned int rows_2p[2][2] = {
+ { 0x00050101, 0x00010404 },
+ { 0x00010404, 0x00050101 }
+ };
+
+ if(maxnodes>2) {
+ print_debug("this mainboard is only designed for 2 cpus\r\n");
+ maxnodes=2;
+ }
+
+
+ if (!(node>=maxnodes || row>=maxnodes)) {
+ ret=rows_2p[node][row];
+ }
+
+ return ret;
+}
+
+static inline void activate_spd_rom(const struct mem_controller *ctrl)
+{
+ /* nothing to do */
+}
+
+static inline int spd_read_byte(unsigned device, unsigned address)
+{
+ return smbus_read_byte(device, address);
+}
+
+#include "northbridge/amd/amdk8/raminit.c"
+#include "northbridge/amd/amdk8/coherent_ht.c"
+#include "northbridge/amd/amdk8/incoherent_ht.c"
+#include "sdram/generic_sdram.c"
+#include "northbridge/amd/amdk8/resourcemap.c"
+#include "cpu/amd/dualcore/dualcore.c"
+
+#define FIRST_CPU 1
+#define SECOND_CPU 1
+#define TOTAL_CPUS (FIRST_CPU + SECOND_CPU)
+static void main(unsigned long bist)
+{
+ static const struct mem_controller cpu[] = {
+#if FIRST_CPU
+ {
+ .node_id = 0,
+ .f0 = PCI_DEV(0, 0x18, 0),
+ .f1 = PCI_DEV(0, 0x18, 1),
+ .f2 = PCI_DEV(0, 0x18, 2),
+ .f3 = PCI_DEV(0, 0x18, 3),
+ .channel0 = { (0xa<<3)|0, (0xa<<3)|2, 0, 0 },
+ .channel1 = { (0xa<<3)|1, (0xa<<3)|3, 0, 0 },
+ },
+#endif
+#if SECOND_CPU
+ {
+ .node_id = 1,
+ .f0 = PCI_DEV(0, 0x19, 0),
+ .f1 = PCI_DEV(0, 0x19, 1),
+ .f2 = PCI_DEV(0, 0x19, 2),
+ .f3 = PCI_DEV(0, 0x19, 3),
+ .channel0 = { (0xa<<3)|4, (0xa<<3)|6, 0, 0 },
+ .channel1 = { (0xa<<3)|5, (0xa<<3)|7, 0, 0 },
+ },
+#endif
+ };
+
+ int needs_reset;
+ unsigned nodeid;
+
+ if (bist == 0) {
+ k8_init_and_stop_secondaries();
+ }
+ /* Setup the console */
+ pc87360_enable_serial(SERIAL_DEV, TTYS0_BASE);
+ uart_init();
+ console_init();
+
+ /* Halt if there was a built in self test failure */
+ report_bist_failure(bist);
+
+ setup_default_resource_map();
+ needs_reset = setup_coherent_ht_domain();
+ needs_reset |= ht_setup_chain(PCI_DEV(0, 0x18, 0), 0x80);
+ if (needs_reset) {
+ print_info("ht reset -\r\n");
+ soft_reset();
+ }
+
+#if 0
+ print_pci_devices();
+#endif
+ enable_smbus();
+#if 0
+ dump_spd_registers(&cpu[0]);
+#endif
+
+ memreset_setup();
+ sdram_initialize(sizeof(cpu)/sizeof(cpu[0]), cpu);
+
+#if 1
+ dump_pci_devices();
+#endif
+#if 0
+ dump_pci_device(PCI_DEV(0, 0x18, 2));
+#endif
+
+ /* Check all of memory */
+#if 0
+ msr_t msr;
+ msr = rdmsr(TOP_MEM);
+ print_debug("TOP_MEM: ");
+ print_debug_hex32(msr.hi);
+ print_debug_hex32(msr.lo);
+ print_debug("\r\n");
+#endif
+#if 0
+ ram_check(0x00000000, msr.lo);
+#endif
+#if 0
+ static const struct {
+ unsigned long lo, hi;
+ } check_addrs[] = {
+ /* Check 16MB of memory @ 0*/
+ { 0x00000000, 0x01000000 },
+#if TOTAL_CPUS > 1
+ /* Check 16MB of memory @ 2GB */
+ { 0x80000000, 0x81000000 },
+#endif
+ };
+ int i;
+ for(i = 0; i < sizeof(check_addrs)/sizeof(check_addrs[0]); i++) {
+ ram_check(check_addrs[i].lo, check_addrs[i].hi);
+ }
+#endif
+}
--- /dev/null
+extern struct chip_operations mainboard_Iwill_DK8X_ops;
+
+struct mainboard_Iwill_DK8X_config {
+ int nothing;
+};
--- /dev/null
+entries
+
+#start-bit length config config-ID name
+#0 8 r 0 seconds
+#8 8 r 0 alarm_seconds
+#16 8 r 0 minutes
+#24 8 r 0 alarm_minutes
+#32 8 r 0 hours
+#40 8 r 0 alarm_hours
+#48 8 r 0 day_of_week
+#56 8 r 0 day_of_month
+#64 8 r 0 month
+#72 8 r 0 year
+#80 4 r 0 rate_select
+#84 3 r 0 REF_Clock
+#87 1 r 0 UIP
+#88 1 r 0 auto_switch_DST
+#89 1 r 0 24_hour_mode
+#90 1 r 0 binary_values_enable
+#91 1 r 0 square-wave_out_enable
+#92 1 r 0 update_finished_enable
+#93 1 r 0 alarm_interrupt_enable
+#94 1 r 0 periodic_interrupt_enable
+#95 1 r 0 disable_clock_updates
+#96 288 r 0 temporary_filler
+0 384 r 0 reserved_memory
+384 1 e 4 boot_option
+385 1 e 4 last_boot
+386 1 e 1 ECC_memory
+388 4 r 0 reboot_bits
+392 3 e 5 baud_rate
+395 1 e 1 hw_scrubber
+396 1 e 1 interleave_chip_selects
+397 2 e 8 max_mem_clock
+399 1 e 2 dual_core
+400 1 e 1 power_on_after_fail
+412 4 e 6 debug_level
+416 4 e 7 boot_first
+420 4 e 7 boot_second
+424 4 e 7 boot_third
+428 4 h 0 boot_index
+432 8 h 0 boot_countdown
+440 4 e 9 slow_cpu
+444 1 e 1 nmi
+445 1 e 1 iommu
+728 256 h 0 user_data
+984 16 h 0 check_sum
+# Reserve the extended AMD configuration registers
+1000 24 r 0 reserved_memory
+
+
+
+enumerations
+
+#ID value text
+1 0 Disable
+1 1 Enable
+2 0 Enable
+2 1 Disable
+4 0 Fallback
+4 1 Normal
+5 0 115200
+5 1 57600
+5 2 38400
+5 3 19200
+5 4 9600
+5 5 4800
+5 6 2400
+5 7 1200
+6 6 Notice
+6 7 Info
+6 8 Debug
+6 9 Spew
+7 0 Network
+7 1 HDD
+7 2 Floppy
+7 8 Fallback_Network
+7 9 Fallback_HDD
+7 10 Fallback_Floppy
+#7 3 ROM
+8 0 DDR400
+8 1 DDR333
+8 2 DDR266
+8 3 DDR200
+9 0 off
+9 1 87.5%
+9 2 75.0%
+9 3 62.5%
+9 4 50.0%
+9 5 37.5%
+9 6 25.0%
+9 7 12.5%
+
+checksums
+
+checksum 392 983 984
+
+
--- /dev/null
+#define ASSEMBLY 1
+#include <stdint.h>
+#include <device/pci_def.h>
+#include <device/pci_ids.h>
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <cpu/x86/lapic.h>
+#include "pc80/mc146818rtc_early.c"
+#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
+#include "northbridge/amd/amdk8/early_ht.c"
+#include "cpu/x86/lapic/boot_cpu.c"
+#include "cpu/x86/mtrr/earlymtrr.c"
+#include "northbridge/amd/amdk8/reset_test.c"
+
+static unsigned long main(unsigned long bist)
+{
+ unsigned nodeid;
+
+ /* Make cerain my local apic is useable */
+ enable_lapic();
+
+ /* Is this a cpu only reset? */
+ if (early_mtrr_init_detected()) {
+ if (last_boot_normal()) {
+ goto normal_image;
+ } else {
+ goto fallback_image;
+ }
+ }
+ /* Is this a secondary cpu? */
+ if (!boot_cpu()) {
+ if (last_boot_normal()) {
+ goto normal_image;
+ } else {
+ goto fallback_image;
+ }
+ }
+
+
+ /* Nothing special needs to be done to find bus 0 */
+ /* Allow the HT devices to be found */
+ enumerate_ht_chain();
+
+ /* Setup the 8111 */
+ amd8111_enable_rom();
+
+ /* Is this a deliberate reset by the bios */
+ if (bios_reset_detected() && last_boot_normal()) {
+ goto normal_image;
+ }
+ /* This is the primary cpu how should I boot? */
+ else if (do_normal_boot()) {
+ goto normal_image;
+ }
+ else {
+ goto fallback_image;
+ }
+ normal_image:
+ asm volatile ("jmp __normal_image"
+ : /* outputs */
+ : "a" (bist) /* inputs */
+ : /* clobbers */
+ );
+ fallback_image:
+ return bist;
+}
--- /dev/null
+#include <arch/pirq_routing.h>
+#include <device/pci.h>
+
+#define IRQ_ROUTER_BUS 1
+#define IRQ_ROUTER_DEVFN PCI_DEVFN(4,3)
+#define IRQ_ROUTER_VENDOR 0x1022
+#define IRQ_ROUTER_DEVICE 0x746b
+
+#define AVAILABLE_IRQS 0xdef8
+#define IRQ_SLOT(slot, bus, dev, fn, linka, linkb, linkc, linkd) \
+ { bus, (dev<<3)|fn, {{ linka, AVAILABLE_IRQS}, { linkb, AVAILABLE_IRQS}, \
+ {linkc, AVAILABLE_IRQS}, {linkd, AVAILABLE_IRQS}}, slot, 0}
+
+/* Each IRQ_SLOT entry consists of:
+ * bus, devfn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu
+ */
+
+const struct irq_routing_table intel_irq_routing_table = {
+ PIRQ_SIGNATURE, /* u32 signature */
+ PIRQ_VERSION, /* u16 version */
+ 32+16*IRQ_SLOT_COUNT, /* there can be total IRQ_SLOT_COUNT
+ * devices on the bus */
+ IRQ_ROUTER_BUS, /* Where the interrupt router lies (bus) */
+ IRQ_ROUTER_DEVFN, /* Where the interrupt router lies (dev) */
+ 0x00, /* IRQs devoted exclusively to PCI usage */
+ IRQ_ROUTER_VENDOR, /* Vendor */
+ IRQ_ROUTER_DEVICE, /* Device */
+ 0x00, /* Crap (miniport) */
+ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
+ 0x00, /* u8 checksum , mod 256 checksum must give
+ * zero, will be corrected later
+ */
+ {
+
+ /* slot(0=onboard), devfn, irqlinks (line id, 0=not routed) */
+
+ /* PCI Slot 1-6 */
+ IRQ_SLOT (1, 3,1,0, 2,3,4,1 ),
+ IRQ_SLOT (2, 3,2,0, 3,4,1,2 ),
+ IRQ_SLOT (3, 2,1,0, 2,3,4,1 ),
+ IRQ_SLOT (4, 2,2,0, 3,4,1,2 ),
+ IRQ_SLOT (5, 4,5,0, 2,3,4,1 ),
+ IRQ_SLOT (6, 4,4,0, 1,2,3,4 ),
+
+ /* Onboard NICs */
+ IRQ_SLOT (0, 2,3,0, 4,0,0,0 ),
+ IRQ_SLOT (0, 2,4,0, 4,0,0,0 ),
+
+ /* Let Linux know about bus 1 */
+ IRQ_SLOT (0, 1,4,3, 0,0,0,0 ),
+ }
+};
+unsigned long write_pirq_routing_table(unsigned long addr)
+{
+ return copy_pirq_routing_table(addr);
+}
--- /dev/null
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include "chip.h"
+
+struct chip_operations mainboard_Iwill_DK8X_ops = {
+ CHIP_NAME("Iwill DK8X mainboard")
+};
+
--- /dev/null
+#include <console/console.h>
+#include <arch/smp/mpspec.h>
+#include <device/pci.h>
+#include <string.h>
+#include <stdint.h>
+
+void *smp_write_config_table(void *v)
+{
+ static const char sig[4] = "PCMP";
+ static const char oem[8] = "IWILL ";
+ static const char productid[12] = "DK8X ";
+ struct mp_config_table *mc;
+ unsigned char bus_num;
+ unsigned char bus_isa;
+ unsigned char bus_8131_1;
+ unsigned char bus_8131_2;
+ unsigned char bus_8111_1;
+
+ mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
+ memset(mc, 0, sizeof(*mc));
+
+ memcpy(mc->mpc_signature, sig, sizeof(sig));
+ mc->mpc_length = sizeof(*mc); /* initially just the header */
+ mc->mpc_spec = 0x04;
+ mc->mpc_checksum = 0; /* not yet computed */
+ memcpy(mc->mpc_oem, oem, sizeof(oem));
+ memcpy(mc->mpc_productid, productid, sizeof(productid));
+ mc->mpc_oemptr = 0;
+ mc->mpc_oemsize = 0;
+ mc->mpc_entry_count = 0; /* No entries yet... */
+ mc->mpc_lapic = LAPIC_ADDR;
+ mc->mpe_length = 0;
+ mc->mpe_checksum = 0;
+ mc->reserved = 0;
+
+ smp_write_processors(mc);
+
+ {
+ device_t dev;
+
+ /* 8111 */
+ dev = dev_find_slot(1, PCI_DEVFN(0x03,0));
+ if (dev) {
+ bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
+ bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
+ bus_isa++;
+ }
+ else {
+ printk_debug("ERROR - could not find PCI 1:03.0, using defaults\n");
+
+ bus_8111_1 = 4;
+ bus_isa = 5;
+ }
+ /* 8131-1 */
+ dev = dev_find_slot(1, PCI_DEVFN(0x01,0));
+ if (dev) {
+ bus_8131_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
+
+ }
+ else {
+ printk_debug("ERROR - could not find PCI 1:01.0, using defaults\n");
+
+ bus_8131_1 = 2;
+ }
+ /* 8131-2 */
+ dev = dev_find_slot(1, PCI_DEVFN(0x02,0));
+ if (dev) {
+ bus_8131_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
+
+ }
+ else {
+ printk_debug("ERROR - could not find PCI 1:02.0, using defaults\n");
+
+ bus_8131_2 = 3;
+ }
+ }
+
+ /* define bus and isa numbers */
+ for(bus_num = 0; bus_num < bus_isa; bus_num++) {
+ smp_write_bus(mc, bus_num, "PCI ");
+ }
+ smp_write_bus(mc, bus_isa, "ISA ");
+
+ /* IOAPIC handling */
+ smp_write_ioapic(mc, 2, 0x11, 0xfec00000);
+ {
+ device_t dev;
+ struct resource *res;
+ /* 8131 apic 3 */
+ dev = dev_find_slot(1, PCI_DEVFN(0x01,1));
+ if (dev) {
+ res = find_resource(dev, PCI_BASE_ADDRESS_0);
+ if (res) {
+ smp_write_ioapic(mc, 0x03, 0x11, res->base);
+ }
+ }
+ /* 8131 apic 4 */
+ dev = dev_find_slot(1, PCI_DEVFN(0x02,1));
+ if (dev) {
+ res = find_resource(dev, PCI_BASE_ADDRESS_0);
+ if (res) {
+ smp_write_ioapic(mc, 0x04, 0x11, res->base);
+ }
+ }
+ }
+
+ /* ISA backward compatibility interrupts */
+ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_isa, 0x00, 0x02, 0x00);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_isa, 0x01, 0x02, 0x01);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_isa, 0x00, 0x02, 0x02);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_isa, 0x03, 0x02, 0x03);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_isa, 0x04, 0x02, 0x04);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_isa, 0x05, 0x02, 0x05);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_isa, 0x06, 0x02, 0x06);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_isa, 0x07, 0x02, 0x07);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_isa, 0x08, 0x02, 0x08);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_isa, 0x09, 0x02, 0x09);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_isa, 0x0a, 0x02, 0x0a);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_isa, 0x0b, 0x02, 0x0b);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_isa, 0x0c, 0x02, 0x0c);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_isa, 0x0d, 0x02, 0x0d);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_isa, 0x0e, 0x02, 0x0e);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_isa, 0x0f, 0x02, 0x0f);
+
+ /* Standard local interrupt assignments */
+ smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_isa, 0x00, MP_APIC_ALL, 0x00);
+ smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_isa, 0x00, MP_APIC_ALL, 0x01);
+
+
+ /* PCI Slot 1 */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_8131_2, (1<<2)|0, 0x02, 0x11);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_8131_2, (1<<2)|1, 0x02, 0x12);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_8131_2, (1<<2)|2, 0x02, 0x13);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_8131_2, (1<<2)|3, 0x02, 0x10);
+
+ /* PCI Slot 2 */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_8131_2, (2<<2)|0, 0x02, 0x12);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_8131_2, (2<<2)|1, 0x02, 0x13);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_8131_2, (2<<2)|2, 0x02, 0x10);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_8131_2, (2<<2)|3, 0x02, 0x11);
+
+ /* PCI Slot 3 */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_8131_1, (1<<2)|0, 0x02, 0x11);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_8131_1, (1<<2)|1, 0x02, 0x12);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_8131_1, (1<<2)|2, 0x02, 0x13);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_8131_1, (1<<2)|3, 0x02, 0x10);
+
+ /* PCI Slot 4 */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_8131_1, (2<<2)|0, 0x02, 0x12);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_8131_1, (2<<2)|1, 0x02, 0x13);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_8131_1, (2<<2)|2, 0x02, 0x10);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_8131_1, (2<<2)|3, 0x02, 0x11);
+
+ /* PCI Slot 5 */
+#warning "FIXME get the irqs right, it's just hacked to work for now"
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_8111_1, (5<<2)|0, 0x02, 0x11);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_8111_1, (5<<2)|1, 0x02, 0x12);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_8111_1, (5<<2)|2, 0x02, 0x13);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_8111_1, (5<<2)|3, 0x02, 0x10);
+
+ /* PCI Slot 6 */
+#warning "FIXME get the irqs right, it's just hacked to work for now"
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_8111_1, (4<<2)|0, 0x02, 0x10);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_8111_1, (4<<2)|1, 0x02, 0x11);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_8111_1, (4<<2)|2, 0x02, 0x12);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_8111_1, (4<<2)|3, 0x02, 0x13);
+
+ /* On board nics */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_8131_1, (3<<2)|0, 0x02, 0x13);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT,
+ bus_8131_1, (4<<2)|0, 0x02, 0x13);
+
+ /* There is no extension information... */
+
+ /* Compute the checksums */
+ mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
+ mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
+ printk_debug("Wrote the mp table end at: %p - %p\n",
+ mc, smp_next_mpe_entry(mc));
+ return smp_next_mpe_entry(mc);
+}
+
+unsigned long write_smp_table(unsigned long addr)
+{
+ void *v;
+ v = smp_write_floating_table(addr);
+ return (unsigned long)smp_write_config_table(v);
+}
+
--- /dev/null
+#include "../../../southbridge/amd/amd8111/amd8111_reset.c"
+
+void hard_reset(void)
+{
+ amd8111_hard_reset(0, 0);
+}
--- /dev/null
+##
+## Compute the location and size of where this firmware image
+## (linuxBIOS plus bootloader) will live in the boot rom chip.
+##
+if USE_FAILOVER_IMAGE
+ default ROM_SECTION_SIZE = FAILOVER_SIZE
+ default ROM_SECTION_OFFSET = ( ROM_SIZE - FAILOVER_SIZE )
+else
+ if USE_FALLBACK_IMAGE
+ default ROM_SECTION_SIZE = FALLBACK_SIZE
+ default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE )
+ else
+ default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE - FAILOVER_SIZE )
+ default ROM_SECTION_OFFSET = 0
+ end
+end
+
+##
+## Compute the start location and size size of
+## The linuxBIOS bootloader.
+##
+default PAYLOAD_SIZE = ( ROM_SECTION_SIZE - ROM_IMAGE_SIZE )
+default CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
+
+##
+## Compute where this copy of linuxBIOS will start in the boot rom
+##
+default _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )
+
+##
+## Compute a range of ROM that can cached to speed up linuxBIOS,
+## execution speed.
+##
+## XIP_ROM_SIZE must be a power of 2.
+## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE
+##
+default XIP_ROM_SIZE=65536
+
+if USE_FAILOVER_IMAGE
+ default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE)
+else
+ if USE_FALLBACK_IMAGE
+ default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE + FAILOVER_SIZE)
+ else
+ default XIP_ROM_BASE = ( _ROMBASE - XIP_ROM_SIZE + ROM_IMAGE_SIZE)
+ end
+end
+
+arch i386 end
+
+##
+## Build the objects we have code for in this directory.
+##
+
+driver mainboard.o
+
+#dir /drivers/si/3114
+
+#needed by irq_tables and mptable and acpi_tables
+object get_bus_conf.o
+
+if HAVE_MP_TABLE
+ object mptable.o
+end
+
+if HAVE_PIRQ_TABLE
+ object irq_tables.o
+end
+
+#if HAVE_ACPI_TABLES
+# object acpi_tables.o
+# object fadt.o
+# if SB_HT_CHAIN_ON_BUS0
+# object dsdt_bus0.o
+# else
+# object dsdt.o
+# end
+# object ssdt.o
+# if ACPI_SSDTX_NUM
+# if SB_HT_CHAIN_ON_BUS0
+# object ssdt2_bus0.o
+# else
+# object ssdt2.o
+# end
+# end
+#end
+
+if HAVE_ACPI_TABLES
+ object acpi_tables.o
+ object fadt.o
+ makerule dsdt.c
+ depends "$(MAINBOARD)/dx/dsdt_lb.dsl"
+ action "/usr/sbin/iasl -tc $(MAINBOARD)/dx/dsdt_lb.dsl"
+ action "mv dsdt_lb.hex dsdt.c"
+ end
+ object ./dsdt.o
+
+ #./ssdt.o is moved to northbridge/amd/amdk8/Config.lb
+
+ if ACPI_SSDTX_NUM
+ makerule ssdt2.c
+ depends "$(MAINBOARD)/dx/pci2.asl"
+ action "/usr/sbin/iasl -tc $(MAINBOARD)/dx/pci2.asl"
+ action "perl -pi -e 's/AmlCode/AmlCode_ssdt2/g' pci2.hex"
+ action "mv pci2.hex ssdt2.c"
+ end
+ object ./ssdt2.o
+ makerule ssdt3.c
+ depends "$(MAINBOARD)/dx/pci3.asl"
+ action "/usr/sbin/iasl -tc $(MAINBOARD)/dx/pci3.asl"
+ action "perl -pi -e 's/AmlCode/AmlCode_ssdt3/g' pci3.hex"
+ action "mv pci3.hex ssdt3.c"
+ end
+ object ./ssdt3.o
+ makerule ssdt4.c
+ depends "$(MAINBOARD)/dx/pci4.asl"
+ action "/usr/sbin/iasl -tc $(MAINBOARD)/dx/pci4.asl"
+ action "perl -pi -e 's/AmlCode/AmlCode_ssdt4/g' pci4.hex"
+ action "mv pci4.hex ssdt4.c"
+ end
+ object ./ssdt4.o
+ end
+end
+
+if USE_DCACHE_RAM
+
+ if CONFIG_USE_INIT
+ # compile cache_as_ram.c to auto.o
+ makerule ./cache_as_ram_auto.o
+ depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
+ action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@"
+ end
+
+ else
+ #compile cache_as_ram.c to auto.inc
+ makerule ./cache_as_ram_auto.inc
+ depends "$(MAINBOARD)/cache_as_ram_auto.c option_table.h"
+ action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/cache_as_ram_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -S -o $@"
+ action "perl -e 's/.rodata/.rom.data/g' -pi $@"
+ action "perl -e 's/.text/.section .rom.text/g' -pi $@"
+ end
+
+ end
+end
+
+if USE_FAILOVER_IMAGE
+else
+ if CONFIG_AP_CODE_IN_CAR
+ makerule ./apc_auto.o
+ depends "$(MAINBOARD)/apc_auto.c option_table.h"
+ action "$(CC) -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/apc_auto.c -Os -nostdinc -nostdlib -fno-builtin -Wall -c -o $@"
+ end
+ ldscript /arch/i386/init/ldscript_apc.lb
+ end
+end
+
+##
+## Build our 16 bit and 32 bit linuxBIOS entry code
+##
+
+if HAVE_FAILOVER_BOOT
+ if USE_FAILOVER_IMAGE
+ mainboardinit cpu/x86/16bit/entry16.inc
+ ldscript /cpu/x86/16bit/entry16.lds
+ end
+else
+ if USE_FALLBACK_IMAGE
+ mainboardinit cpu/x86/16bit/entry16.inc
+ ldscript /cpu/x86/16bit/entry16.lds
+ end
+end
+
+mainboardinit cpu/x86/32bit/entry32.inc
+if USE_DCACHE_RAM
+ if CONFIG_USE_INIT
+ ldscript /cpu/x86/32bit/entry32.lds
+ end
+
+ if CONFIG_USE_INIT
+ ldscript /cpu/amd/car/cache_as_ram.lds
+ end
+end
+
+##
+## Build our reset vector (This is where linuxBIOS is entered)
+##
+if HAVE_FAILOVER_BOOT
+ if USE_FAILOVER_IMAGE
+ mainboardinit cpu/x86/16bit/reset16.inc
+ ldscript /cpu/x86/16bit/reset16.lds
+ else
+ mainboardinit cpu/x86/32bit/reset32.inc
+ ldscript /cpu/x86/32bit/reset32.lds
+ end
+else
+ if USE_FALLBACK_IMAGE
+ mainboardinit cpu/x86/16bit/reset16.inc
+ ldscript /cpu/x86/16bit/reset16.lds
+ else
+ mainboardinit cpu/x86/32bit/reset32.inc
+ ldscript /cpu/x86/32bit/reset32.lds
+ end
+end
+
+##
+## Include an id string (For safe flashing)
+##
+mainboardinit arch/i386/lib/id.inc
+ldscript /arch/i386/lib/id.lds
+
+if USE_DCACHE_RAM
+ ##
+ ## Setup Cache-As-Ram
+ ##
+ mainboardinit cpu/amd/car/cache_as_ram.inc
+end
+
+###
+### This is the early phase of linuxBIOS startup
+### Things are delicate and we test to see if we should
+### failover to another image.
+###
+if HAVE_FAILOVER_BOOT
+ if USE_FAILOVER_IMAGE
+ if USE_DCACHE_RAM
+ ldscript /arch/i386/lib/failover_failover.lds
+ end
+ end
+else
+ if USE_FALLBACK_IMAGE
+ if USE_DCACHE_RAM
+ ldscript /arch/i386/lib/failover.lds
+ end
+ end
+end
+
+###
+### O.k. We aren't just an intermediary anymore!
+###
+
+##
+## Setup RAM
+##
+if USE_DCACHE_RAM
+
+ if CONFIG_USE_INIT
+ initobject cache_as_ram_auto.o
+ else
+ mainboardinit ./cache_as_ram_auto.inc
+ end
+
+end
+
+##
+## Include the secondary Configuration files
+##
+if CONFIG_CHIP_NAME
+ config chip.h
+end
+
+dir /southbridge/amd/amd8132
+
+chip northbridge/amd/amdk8/root_complex
+ device apic_cluster 0 on
+ chip cpu/amd/socket_940
+ device apic 0 on end
+ end
+ end
+ device pci_domain 0 on
+ chip northbridge/amd/amdk8
+ device pci 18.0 on end
+ device pci 18.0 on end
+ device pci 18.0 on # northbridge
+ chip southbridge/amd/amd8131
+ # the on/off keyword is mandatory
+ device pci 0.0 on end
+ device pci 0.1 on end
+ device pci 1.0 on end
+ device pci 1.1 on end
+ end
+ chip southbridge/amd/amd8111
+ # this "device pci 0.0" is the parent the next one
+ # PCI bridge
+ device pci 0.0 on
+ device pci 0.0 on end
+ device pci 0.1 on end
+ device pci 0.2 off end
+ device pci 1.0 off end
+ #chip drivers/pci/onboard
+ # device pci 6.0 on end
+ # register "rom_address" = "0xfff80000"
+ #end
+ end
+ device pci 1.0 on
+ chip superio/winbond/w83627hf
+ device pnp 2e.0 off # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 2e.1 off # Parallel Port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ end
+ device pnp 2e.2 on # Com1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 2e.3 off # Com2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ device pnp 2e.5 on # Keyboard
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1
+ irq 0x72 = 12
+ end
+ device pnp 2e.6 off # CIR
+ io 0x60 = 0x100
+ end
+ device pnp 2e.7 off # GAME_MIDI_GIPO1
+ io 0x60 = 0x220
+ io 0x62 = 0x300
+ irq 0x70 = 9
+ end
+ device pnp 2e.8 off end # GPIO2
+ device pnp 2e.9 off end # GPIO3
+ device pnp 2e.a off end # ACPI
+ device pnp 2e.b on # HW Monitor
+ io 0x60 = 0x290
+ irq 0x70 = 5
+ end
+ end
+ end
+ device pci 1.1 on end
+ device pci 1.2 on end
+ device pci 1.3 on
+ chip drivers/generic/generic #dimm 0-0-0
+ device i2c 50 on end
+ end
+ chip drivers/generic/generic #dimm 0-0-1
+ device i2c 51 on end
+ end
+ chip drivers/generic/generic #dimm 0-1-0
+ device i2c 52 on end
+ end
+ chip drivers/generic/generic #dimm 0-1-1
+ device i2c 53 on end
+ end
+ chip drivers/generic/generic #dimm 1-0-0
+ device i2c 54 on end
+ end
+ chip drivers/generic/generic #dimm 1-0-1
+ device i2c 55 on end
+ end
+ chip drivers/generic/generic #dimm 1-1-0
+ device i2c 56 on end
+ end
+ chip drivers/generic/generic #dimm 1-1-1
+ device i2c 57 on end
+ end
+ end # acpi
+ device pci 1.5 off end
+ device pci 1.6 off end
+ register "ide0_enable" = "1"
+ register "ide1_enable" = "1"
+ end
+ end # device pci 18.0
+
+ device pci 18.1 on end
+ device pci 18.2 on end
+ device pci 18.3 on end
+ end
+
+ end #pci_domain
+# chip drivers/generic/debug
+# device pnp 0.0 off end # chip name
+# device pnp 0.1 on end # pci_regs_all
+# device pnp 0.2 off end # mem
+# device pnp 0.3 off end # cpuid
+# device pnp 0.4 off end # smbus_regs_all
+# device pnp 0.5 off end # dual core msr
+# device pnp 0.6 off end # cache size
+# device pnp 0.7 off end # tsc
+# end
+
+end
+
+
--- /dev/null
+uses HAVE_MP_TABLE
+uses HAVE_PIRQ_TABLE
+uses HAVE_ACPI_TABLES
+uses ACPI_SSDTX_NUM
+uses USE_FALLBACK_IMAGE
+uses USE_FAILOVER_IMAGE
+uses HAVE_FALLBACK_BOOT
+uses HAVE_FAILOVER_BOOT
+uses HAVE_HARD_RESET
+uses IRQ_SLOT_COUNT
+uses HAVE_OPTION_TABLE
+uses CONFIG_MAX_CPUS
+uses CONFIG_MAX_PHYSICAL_CPUS
+uses CONFIG_LOGICAL_CPUS
+uses CONFIG_IOAPIC
+uses CONFIG_SMP
+uses FALLBACK_SIZE
+uses FAILOVER_SIZE
+uses ROM_SIZE
+uses ROM_SECTION_SIZE
+uses ROM_IMAGE_SIZE
+uses ROM_SECTION_SIZE
+uses ROM_SECTION_OFFSET
+uses CONFIG_ROM_STREAM
+uses CONFIG_ROM_STREAM_START
+uses CONFIG_COMPRESSED_ROM_STREAM
+uses PAYLOAD_SIZE
+uses _ROMBASE
+uses XIP_ROM_SIZE
+uses XIP_ROM_BASE
+uses STACK_SIZE
+uses HEAP_SIZE
+uses USE_OPTION_TABLE
+uses LB_CKS_RANGE_START
+uses LB_CKS_RANGE_END
+uses LB_CKS_LOC
+uses MAINBOARD_PART_NUMBER
+uses MAINBOARD_VENDOR
+uses MAINBOARD
+uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
+uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
+uses LINUXBIOS_EXTRA_VERSION
+uses _RAMBASE
+uses TTYS0_BAUD
+uses TTYS0_BASE
+uses TTYS0_LCS
+uses DEFAULT_CONSOLE_LOGLEVEL
+uses MAXIMUM_CONSOLE_LOGLEVEL
+uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL
+uses CONFIG_CONSOLE_SERIAL8250
+uses HAVE_INIT_TIMER
+uses CONFIG_GDB_STUB
+uses CONFIG_GDB_STUB
+uses CROSS_COMPILE
+uses CC
+uses HOSTCC
+uses OBJCOPY
+uses CONFIG_CHIP_NAME
+uses CONFIG_CONSOLE_VGA
+uses CONFIG_PCI_ROM_RUN
+uses HW_MEM_HOLE_SIZEK
+uses HW_MEM_HOLE_SIZE_AUTO_INC
+uses K8_HT_FREQ_1G_SUPPORT
+
+uses HT_CHAIN_UNITID_BASE
+uses HT_CHAIN_END_UNITID_BASE
+uses SB_HT_CHAIN_ON_BUS0
+uses SB_HT_CHAIN_UNITID_OFFSET_ONLY
+
+uses USE_DCACHE_RAM
+uses DCACHE_RAM_BASE
+uses DCACHE_RAM_SIZE
+uses DCACHE_RAM_GLOBAL_VAR_SIZE
+uses CONFIG_USE_INIT
+
+uses SERIAL_CPU_INIT
+
+uses ENABLE_APIC_EXT_ID
+uses APIC_ID_OFFSET
+uses LIFT_BSP_APIC_ID
+
+uses CONFIG_PCI_64BIT_PREF_MEM
+
+uses CONFIG_LB_MEM_TOPK
+
+uses CONFIG_AP_CODE_IN_CAR
+
+uses MEM_TRAIN_SEQ
+
+uses WAIT_BEFORE_CPUS_INIT
+
+uses CONFIG_USE_PRINTK_IN_CAR
+
+###
+### Build options
+###
+
+##
+## ROM_SIZE is the size of boot ROM that this board will use.
+##
+default ROM_SIZE=524288
+
+##
+## FALLBACK_SIZE is the amount of the ROM the complete fallback image will use
+##
+#default FALLBACK_SIZE=131072
+#default FALLBACK_SIZE=0x40000
+
+#FALLBACK: 256K-4K
+default FALLBACK_SIZE=0x3f000
+#FAILOVER: 4K
+default FAILOVER_SIZE=0x01000
+
+#more 1M for pgtbl
+default CONFIG_LB_MEM_TOPK=2048
+
+##
+## Build code for the fallback boot
+##
+default HAVE_FALLBACK_BOOT=1
+default HAVE_FAILOVER_BOOT=1
+
+##
+## Build code to reset the motherboard from linuxBIOS
+##
+default HAVE_HARD_RESET=1
+
+##
+## Build code to export a programmable irq routing table
+##
+default HAVE_PIRQ_TABLE=1
+default IRQ_SLOT_COUNT=11
+
+##
+## Build code to export an x86 MP table
+## Useful for specifying IRQ routing values
+##
+default HAVE_MP_TABLE=1
+
+## ACPI tables will be included
+default HAVE_ACPI_TABLES=1
+## extra SSDT num
+default ACPI_SSDTX_NUM=3
+
+##
+## Build code to export a CMOS option table
+##
+default HAVE_OPTION_TABLE=1
+
+##
+## Move the default LinuxBIOS cmos range off of AMD RTC registers
+##
+default LB_CKS_RANGE_START=49
+default LB_CKS_RANGE_END=122
+default LB_CKS_LOC=123
+
+##
+## Build code for SMP support
+## Only worry about 2 micro processors
+##
+default CONFIG_SMP=1
+default CONFIG_MAX_CPUS=4
+default CONFIG_MAX_PHYSICAL_CPUS=2
+default CONFIG_LOGICAL_CPUS=1
+
+default SERIAL_CPU_INIT=0
+
+default ENABLE_APIC_EXT_ID=0
+default APIC_ID_OFFSET=0x10
+default LIFT_BSP_APIC_ID=1
+
+#CHIP_NAME ?
+default CONFIG_CHIP_NAME=1
+
+#memory hole size, 0 mean disable, others will enable the hole, at that case if it is small than mmio_basek, it will use mmio_basek instead.
+#2G
+#default HW_MEM_HOLE_SIZEK=0x200000
+#1G
+#default HW_MEM_HOLE_SIZEK=0x100000
+#512M
+default HW_MEM_HOLE_SIZEK=0x80000
+
+#make auto increase hole size to avoid hole_startk equal to basek so as to make some kernel happy
+#default HW_MEM_HOLE_SIZE_AUTO_INC=1
+
+#Opteron K8 1G HT Support
+default K8_HT_FREQ_1G_SUPPORT=1
+
+#VGA Console
+default CONFIG_CONSOLE_VGA=1
+default CONFIG_PCI_ROM_RUN=1
+
+#HT Unit ID offset, default is 1, the typical one
+default HT_CHAIN_UNITID_BASE=0xa
+
+#real SB Unit ID, default is 0x20, mean dont touch it at last
+default HT_CHAIN_END_UNITID_BASE=0x6
+
+#make the SB HT chain on bus 0, default is not (0)
+default SB_HT_CHAIN_ON_BUS0=2
+
+#only offset for SB chain?, default is yes(1)
+#default SB_HT_CHAIN_UNITID_OFFSET_ONLY=0
+
+#allow capable device use that above 4G
+#default CONFIG_PCI_64BIT_PREF_MEM=1
+
+##
+## enable CACHE_AS_RAM specifics
+##
+default USE_DCACHE_RAM=1
+default DCACHE_RAM_BASE=0xc4000
+default DCACHE_RAM_SIZE=0x0c000
+default DCACHE_RAM_GLOBAL_VAR_SIZE=0x01000
+default CONFIG_USE_INIT=0
+
+##
+## for rev F training on AP purpose
+##
+#default CONFIG_AP_CODE_IN_CAR=1
+#default MEM_TRAIN_SEQ=1
+#default WAIT_BEFORE_CPUS_INIT=1
+
+##
+## Build code to setup a generic IOAPIC
+##
+default CONFIG_IOAPIC=1
+
+##
+## Clean up the motherboard id strings
+##
+default MAINBOARD_PART_NUMBER="dk8_htx"
+default MAINBOARD_VENDOR="Iwill"
+default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x1022
+default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2b80
+
+###
+### LinuxBIOS layout values
+###
+
+## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+default ROM_IMAGE_SIZE = 65536
+
+##
+## Use a small 8K stack
+##
+default STACK_SIZE=0x2000
+
+##
+## Use a small 32K heap
+##
+default HEAP_SIZE=0x8000
+
+##
+## Only use the option table in a normal image
+##
+default USE_OPTION_TABLE = (!USE_FALLBACK_IMAGE) && (!USE_FAILOVER_IMAGE )
+
+##
+## LinuxBIOS C code runs at this location in RAM
+##
+default _RAMBASE=0x00100000
+
+##
+## Load the payload from the ROM
+##
+default CONFIG_ROM_STREAM = 1
+
+#default CONFIG_COMPRESSED_ROM_STREAM = 1
+
+###
+### Defaults of options that you may want to override in the target config file
+###
+
+##
+## The default compiler
+##
+default CC="$(CROSS_COMPILE)gcc -m32"
+default HOSTCC="gcc"
+
+##
+## Disable the gdb stub by default
+##
+default CONFIG_GDB_STUB=0
+
+##
+## The Serial Console
+##
+default CONFIG_USE_PRINTK_IN_CAR=1
+
+# To Enable the Serial Console
+default CONFIG_CONSOLE_SERIAL8250=1
+
+## Select the serial console baud rate
+default TTYS0_BAUD=115200
+#default TTYS0_BAUD=57600
+#default TTYS0_BAUD=38400
+#default TTYS0_BAUD=19200
+#default TTYS0_BAUD=9600
+#default TTYS0_BAUD=4800
+#default TTYS0_BAUD=2400
+#default TTYS0_BAUD=1200
+
+# Select the serial console base port
+default TTYS0_BASE=0x3f8
+
+# Select the serial protocol
+# This defaults to 8 data bits, 1 stop bit, and no parity
+default TTYS0_LCS=0x3
+
+##
+### Select the linuxBIOS loglevel
+##
+## EMERG 1 system is unusable
+## ALERT 2 action must be taken immediately
+## CRIT 3 critical conditions
+## ERR 4 error conditions
+## WARNING 5 warning conditions
+## NOTICE 6 normal but significant condition
+## INFO 7 informational
+## DEBUG 8 debug-level messages
+## SPEW 9 Way too many details
+
+## Request this level of debugging output
+default DEFAULT_CONSOLE_LOGLEVEL=8
+## At a maximum only compile in this level of debugging
+default MAXIMUM_CONSOLE_LOGLEVEL=8
+
+##
+## Select power on after power fail setting
+default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
+
+### End Options.lb
+end
--- /dev/null
+/*
+ * Island Aruma ACPI support
+ * written by Stefan Reinauer <stepan@openbios.org>
+ * (C) 2005 Stefan Reinauer
+ *
+ *
+ * Copyright 2005 AMD
+ * 2005.9 yhlu modify that to more dynamic for AMD Opteron Based MB
+ */
+
+#include <console/console.h>
+#include <string.h>
+#include <arch/acpi.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <cpu/x86/msr.h>
+#include <cpu/amd/mtrr.h>
+#include <cpu/amd/amdk8_sysconf.h>
+
+#include "mb_sysconf.h"
+
+#define DUMP_ACPI_TABLES 0
+
+#if DUMP_ACPI_TABLES == 1
+static void dump_mem(unsigned start, unsigned end)
+{
+
+ unsigned i;
+ print_debug("dump_mem:");
+ for(i=start;i<end;i++) {
+ if((i & 0xf)==0) {
+ printk_debug("\n%08x:", i);
+ }
+ printk_debug(" %02x", (unsigned char)*((unsigned char *)i));
+ }
+ print_debug("\n");
+ }
+#endif
+
+extern unsigned char AmlCode[];
+extern unsigned char AmlCode_ssdt[];
+
+#if ACPI_SSDTX_NUM >= 1
+extern unsigned char AmlCode_ssdt2[];
+extern unsigned char AmlCode_ssdt3[];
+extern unsigned char AmlCode_ssdt4[];
+#endif
+
+#define IO_APIC_ADDR 0xfec00000UL
+
+unsigned long acpi_fill_madt(unsigned long current)
+{
+ unsigned int gsi_base=0x18;
+
+ struct mb_sysconf_t *m;
+
+ m = sysconf.mb;
+
+ /* create all subtables for processors */
+ current = acpi_create_madt_lapics(current);
+
+ /* Write 8111 IOAPIC */
+ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8111,
+ IO_APIC_ADDR, 0);
+
+ /* Write all 8131 IOAPICs */
+ {
+ device_t dev;
+ struct resource *res;
+ dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN((sysconf.hcdn[0]&0xff), 1));
+ if (dev) {
+ res = find_resource(dev, PCI_BASE_ADDRESS_0);
+ if (res) {
+ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8132_1,
+ res->base, gsi_base );
+ gsi_base+=4;
+
+ }
+ }
+ dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN((sysconf.hcdn[0] & 0xff)+1, 1));
+ if (dev) {
+ res = find_resource(dev, PCI_BASE_ADDRESS_0);
+ if (res) {
+ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8132_2,
+ res->base, gsi_base );
+ gsi_base+=4;
+ }
+ }
+
+ int i;
+ int j = 0;
+
+ for(i=1; i< sysconf.hc_possible_num; i++) {
+ unsigned d;
+ if(!(sysconf.pci1234[i] & 0x1) ) continue;
+ // 8131 need to use +4
+
+ switch (sysconf.hcid[i]) {
+ case 1:
+ d = 7;
+ break;
+ case 3:
+ d = 4;
+ break;
+ }
+ switch (sysconf.hcid[i]) {
+ case 1:
+ case 3:
+ dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j], 1));
+ if (dev) {
+ res = find_resource(dev, PCI_BASE_ADDRESS_0);
+ if (res) {
+ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8132a[j][0],
+ res->base, gsi_base );
+ gsi_base+=d;
+ }
+ }
+ dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1, 1));
+ if (dev) {
+ res = find_resource(dev, PCI_BASE_ADDRESS_0);
+ if (res) {
+ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, m->apicid_8132a[j][1],
+ res->base, gsi_base );
+ gsi_base+=d;
+
+ }
+ }
+ break;
+ }
+
+ j++;
+ }
+
+ }
+
+ current += acpi_create_madt_irqoverride( (acpi_madt_irqoverride_t *)
+ current, 0, 0, 2, 5 );
+ /* 0: mean bus 0--->ISA */
+ /* 0: PIC 0 */
+ /* 2: APIC 2 */
+ /* 5 mean: 0101 --> Edige-triggered, Active high*/
+
+
+ /* create all subtables for processors */
+ current = acpi_create_madt_lapic_nmis(current, 5, 1);
+ /* 1: LINT1 connect to NMI */
+
+
+ return current;
+}
+
+extern void get_bus_conf(void);
+
+extern void update_ssdt(void *ssdt);
+
+void update_ssdtx(void *ssdtx, int i)
+{
+ uint8_t *PCI;
+ uint8_t *HCIN;
+ uint8_t *UID;
+
+ PCI = ssdtx + 0x32;
+ HCIN = ssdtx + 0x39;
+ UID = ssdtx + 0x40;
+
+ if(i<7) {
+ *PCI = (uint8_t) ('4' + i - 1);
+ }
+ else {
+ *PCI = (uint8_t) ('A' + i - 1 - 6);
+ }
+ *HCIN = (uint8_t) i;
+ *UID = (uint8_t) (i+3);
+
+ /* FIXME: need to update the GSI id in the ssdtx too */
+
+}
+
+unsigned long write_acpi_tables(unsigned long start)
+{
+ unsigned long current;
+ acpi_rsdp_t *rsdp;
+ acpi_rsdt_t *rsdt;
+ acpi_hpet_t *hpet;
+ acpi_madt_t *madt;
+ acpi_srat_t *srat;
+ acpi_slit_t *slit;
+ acpi_fadt_t *fadt;
+ acpi_facs_t *facs;
+ acpi_header_t *dsdt;
+ acpi_header_t *ssdt;
+ acpi_header_t *ssdtx;
+ unsigned char *p;
+
+ unsigned char *AmlCode_ssdtx[HC_POSSIBLE_NUM];
+
+ int i;
+
+ get_bus_conf(); //it will get sblk, pci1234, hcdn, and sbdn
+
+ /* Align ACPI tables to 16byte */
+ start = ( start + 0x0f ) & -0x10;
+ current = start;
+
+ printk_info("ACPI: Writing ACPI tables at %lx...\n", start);
+
+ /* We need at least an RSDP and an RSDT Table */
+ rsdp = (acpi_rsdp_t *) current;
+ current += sizeof(acpi_rsdp_t);
+ rsdt = (acpi_rsdt_t *) current;
+ current += sizeof(acpi_rsdt_t);
+
+ /* clear all table memory */
+ memset((void *)start, 0, current - start);
+
+ acpi_write_rsdp(rsdp, rsdt);
+ acpi_write_rsdt(rsdt);
+
+ /*
+ * We explicitly add these tables later on:
+ */
+ printk_debug("ACPI: * HPET\n");
+ hpet = (acpi_hpet_t *) current;
+ current += sizeof(acpi_hpet_t);
+ acpi_create_hpet(hpet);
+ acpi_add_table(rsdt,hpet);
+
+ /* If we want to use HPET Timers Linux wants an MADT */
+ printk_debug("ACPI: * MADT\n");
+ madt = (acpi_madt_t *) current;
+ acpi_create_madt(madt);
+ current+=madt->header.length;
+ acpi_add_table(rsdt,madt);
+
+
+ /* SRAT */
+ printk_debug("ACPI: * SRAT\n");
+ srat = (acpi_srat_t *) current;
+ acpi_create_srat(srat);
+ current+=srat->header.length;
+ acpi_add_table(rsdt,srat);
+
+ /* SLIT */
+ printk_debug("ACPI: * SLIT\n");
+ slit = (acpi_slit_t *) current;
+ acpi_create_slit(slit);
+ current+=slit->header.length;
+ acpi_add_table(rsdt,slit);
+
+ /* SSDT */
+ printk_debug("ACPI: * SSDT\n");
+ ssdt = (acpi_header_t *)current;
+ current += ((acpi_header_t *)AmlCode_ssdt)->length;
+ memcpy((void *)ssdt, (void *)AmlCode_ssdt, ((acpi_header_t *)AmlCode_ssdt)->length);
+ //Here you need to set value in pci1234, sblk and sbdn in get_bus_conf.c
+ update_ssdt((void*)ssdt);
+ /* recalculate checksum */
+ ssdt->checksum = 0;
+ ssdt->checksum = acpi_checksum((unsigned char *)ssdt,ssdt->length);
+ acpi_add_table(rsdt,ssdt);
+
+#if ACPI_SSDTX_NUM >= 1
+
+ //same htio, but different position? We may have to copy, change HCIN, and recalculate the checknum and add_table
+
+ for(i=1;i<sysconf.hc_possible_num;i++) { // 0: is hc sblink
+ if((sysconf.pci1234[i] & 1) != 1 ) continue;
+ uint8_t c;
+ if(i<7) {
+ c = (uint8_t) ('4' + i - 1);
+ }
+ else {
+ c = (uint8_t) ('A' + i - 1 - 6);
+ }
+ printk_debug("ACPI: * SSDT for PCI%c Aka hcid = %d\n", c, sysconf.hcid[i]); //pci0 and pci1 are in dsdt
+ current = ( current + 0x07) & -0x08;
+ ssdtx = (acpi_header_t *)current;
+ switch(sysconf.hcid[i]) {
+ case 1: //8132
+ p = AmlCode_ssdt2;
+ break;
+ case 2: //8151
+ p = AmlCode_ssdt3;
+ break;
+ case 3: //8131
+ p = AmlCode_ssdt4;
+ break;
+ default:
+ continue;
+ }
+ current += ((acpi_header_t *)p)->length;
+ memcpy((void *)ssdtx, (void *)p, ((acpi_header_t *)p)->length);
+ update_ssdtx((void *)ssdtx, i);
+ ssdtx->checksum = 0;
+ ssdtx->checksum = acpi_checksum((unsigned char *)ssdtx,ssdtx->length);
+ acpi_add_table(rsdt,ssdtx);
+ }
+#endif
+
+ /* FACS */
+ printk_debug("ACPI: * FACS\n");
+ facs = (acpi_facs_t *) current;
+ current += sizeof(acpi_facs_t);
+ acpi_create_facs(facs);
+
+ /* DSDT */
+ printk_debug("ACPI: * DSDT\n");
+ dsdt = (acpi_header_t *)current;
+ current += ((acpi_header_t *)AmlCode)->length;
+ memcpy((void *)dsdt,(void *)AmlCode, \
+ ((acpi_header_t *)AmlCode)->length);
+ printk_debug("ACPI: * DSDT @ %08x Length %x\n",dsdt,dsdt->length);
+
+ /* FDAT */
+ printk_debug("ACPI: * FADT\n");
+ fadt = (acpi_fadt_t *) current;
+ current += sizeof(acpi_fadt_t);
+
+ acpi_create_fadt(fadt,facs,dsdt);
+ acpi_add_table(rsdt,fadt);
+
+#if DUMP_ACPI_TABLES == 1
+ printk_debug("rsdp\n");
+ dump_mem(rsdp, ((void *)rsdp) + sizeof(acpi_rsdp_t));
+
+ printk_debug("rsdt\n");
+ dump_mem(rsdt, ((void *)rsdt) + sizeof(acpi_rsdt_t));
+
+ printk_debug("madt\n");
+ dump_mem(madt, ((void *)madt) + madt->header.length);
+
+ printk_debug("srat\n");
+ dump_mem(srat, ((void *)srat) + srat->header.length);
+
+ printk_debug("slit\n");
+ dump_mem(slit, ((void *)slit) + slit->header.length);
+
+ printk_debug("ssdt\n");
+ dump_mem(ssdt, ((void *)ssdt) + ssdt->length);
+
+ printk_debug("fadt\n");
+ dump_mem(fadt, ((void *)fadt) + fadt->header.length);
+#endif
+
+ printk_info("ACPI: done.\n");
+ return current;
+}
+
--- /dev/null
+#define ASSEMBLY 1
+#define __ROMCC__
+
+#define RAMINIT_SYSINFO 1
+#define CACHE_AS_RAM_ADDRESS_DEBUG 0
+
+#define SET_NB_CFG_54 1
+
+//used by raminit
+#define QRANK_DIMM_SUPPORT 1
+
+//used by incoherent_ht
+//#define K8_SCAN_PCI_BUS 1
+//#define K8_ALLOCATE_IO_RANGE 1
+
+
+//used by init_cpus and fidvid
+#define K8_SET_FIDVID 0
+//if we want to wait for core1 done before DQS training, set it to 0
+#define K8_SET_FIDVID_CORE0_ONLY 1
+
+#if K8_REV_F_SUPPORT == 1
+#define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
+#endif
+
+#include <stdint.h>
+#include <device/pci_def.h>
+#include <device/pci_ids.h>
+#include <arch/io.h>
+#include <device/pnp_def.h>
+#include <arch/romcc_io.h>
+#include <cpu/x86/lapic.h>
+#include "option_table.h"
+#include "pc80/mc146818rtc_early.c"
+
+#if USE_FAILOVER_IMAGE==0
+#include "pc80/serial.c"
+#include "arch/i386/lib/console.c"
+#include <cpu/amd/model_fxx_rev.h>
+#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
+#include "northbridge/amd/amdk8/raminit.h"
+#include "cpu/amd/model_fxx/apic_timer.c"
+#endif
+
+
+
+#include "cpu/x86/lapic/boot_cpu.c"
+#include "northbridge/amd/amdk8/reset_test.c"
+
+#if USE_FAILOVER_IMAGE==0
+#include "cpu/x86/bist.h"
+
+#include "lib/delay.c"
+
+#if CONFIG_USE_INIT == 0
+ #include "lib/memcpy.c"
+ #if CONFIG_USE_PRINTK_IN_CAR == 1
+ #include "lib/uart8250.c"
+ #include "console/vtxprintf.c"
+ #include "arch/i386/lib/printk_init.c"
+ #endif
+#endif
+#include "northbridge/amd/amdk8/debug.c"
+#include "cpu/amd/mtrr/amd_earlymtrr.c"
+#include "superio/winbond/w83627hf/w83627hf_early_serial.c"
+
+#include "northbridge/amd/amdk8/setup_resource_map.c"
+
+#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
+
+#include "southbridge/amd/amd8111/amd8111_early_ctrl.c"
+
+/*
+ * GPIO28 of 8111 will control H0_MEMRESET_L
+ * GPIO29 of 8111 will control H1_MEMRESET_L
+ */
+static void memreset_setup(void)
+{
+ if (is_cpu_pre_c0()) {
+ /* Set the memreset low */
+ outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 28);
+ /* Ensure the BIOS has control of the memory lines */
+ outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(0<<0), SMBUS_IO_BASE + 0xc0 + 29);
+ } else {
+ /* Ensure the CPU has controll of the memory lines */
+ outb((0 << 7)|(0 << 6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 29);
+ }
+}
+
+static void memreset(int controllers, const struct mem_controller *ctrl)
+{
+ if (is_cpu_pre_c0()) {
+ udelay(800);
+ /* Set memreset_high */
+ outb((0<<7)|(0<<6)|(0<<5)|(0<<4)|(1<<2)|(1<<0), SMBUS_IO_BASE + 0xc0 + 28);
+ udelay(90);
+ }
+}
+
+static inline void activate_spd_rom(const struct mem_controller *ctrl)
+{
+}
+
+static inline int spd_read_byte(unsigned device, unsigned address)
+{
+ return smbus_read_byte(device, address);
+}
+
+#include "northbridge/amd/amdk8/amdk8.h"
+#include "northbridge/amd/amdk8/coherent_ht_car.c"
+
+#include "northbridge/amd/amdk8/incoherent_ht.c"
+
+#include "northbridge/amd/amdk8/raminit.c"
+
+#include "sdram/generic_sdram.c"
+#include "ram/ramtest.c"
+
+ /* tyan does not want the default */
+#include "resourcemap.c"
+
+#include "cpu/amd/dualcore/dualcore.c"
+
+#define DIMM0 0x50
+#define DIMM1 0x51
+#define DIMM2 0x52
+#define DIMM3 0x53
+#define DIMM4 0x54
+#define DIMM5 0x55
+#define DIMM6 0x56
+#define DIMM7 0x57
+
+
+#include "cpu/amd/car/copy_and_run.c"
+#include "cpu/amd/car/post_cache_as_ram.c"
+
+#include "cpu/amd/model_fxx/init_cpus.c"
+
+#include "cpu/amd/model_fxx/fidvid.c"
+#endif
+
+#if ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE == 1)) || ((HAVE_FAILOVER_BOOT==0) && (USE_FALLBACK_IMAGE == 1))
+
+#include "southbridge/amd/amd8111/amd8111_enable_rom.c"
+#include "northbridge/amd/amdk8/early_ht.c"
+
+void failover_process(unsigned long bist, unsigned long cpu_init_detectedx)
+{
+
+ unsigned last_boot_normal_x = last_boot_normal();
+
+ /* Is this a cpu only reset? or Is this a secondary cpu? */
+ if ((cpu_init_detectedx) || (!boot_cpu())) {
+ if (last_boot_normal_x) {
+ goto normal_image;
+ } else {
+ goto fallback_image;
+ }
+ }
+
+ /* Nothing special needs to be done to find bus 0 */
+ /* Allow the HT devices to be found */
+
+ enumerate_ht_chain();
+
+ /* Setup the rom access for 4M */
+ amd8111_enable_rom();
+
+ /* Is this a deliberate reset by the bios */
+ if (bios_reset_detected() && last_boot_normal_x) {
+ goto normal_image;
+ }
+ /* This is the primary cpu how should I boot? */
+ else if (do_normal_boot()) {
+ goto normal_image;
+ }
+ else {
+ goto fallback_image;
+ }
+ normal_image:
+ __asm__ volatile ("jmp __normal_image"
+ : /* outputs */
+ : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
+ );
+
+ fallback_image:
+#if HAVE_FAILOVER_BOOT==1
+ __asm__ volatile ("jmp __fallback_image"
+ : /* outputs */
+ : "a" (bist), "b" (cpu_init_detectedx) /* inputs */
+ )
+#endif
+ ;
+}
+#endif
+
+void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
+
+void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
+{
+#if HAVE_FAILOVER_BOOT==1
+ #if USE_FAILOVER_IMAGE==1
+ failover_process(bist, cpu_init_detectedx);
+ #else
+ real_main(bist, cpu_init_detectedx);
+ #endif
+#else
+ #if USE_FALLBACK_IMAGE == 1
+ failover_process(bist, cpu_init_detectedx);
+ #endif
+ real_main(bist, cpu_init_detectedx);
+#endif
+}
+
+#if USE_FAILOVER_IMAGE==0
+
+void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
+{
+ static const uint16_t spd_addr[] = {
+ //first node
+ DIMM0, DIMM2, 0, 0,
+ DIMM1, DIMM3, 0, 0,
+#if CONFIG_MAX_PHYSICAL_CPUS > 1
+ //second node
+ DIMM4, DIMM6, 0, 0,
+ DIMM5, DIMM7, 0, 0,
+#endif
+
+ };
+
+ struct sys_info *sysinfo = (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE);
+
+ int needs_reset; int i;
+ unsigned bsp_apicid = 0;
+
+ if (bist == 0) {
+ bsp_apicid = init_cpus(cpu_init_detectedx, sysinfo);
+ }
+
+ w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
+ uart_init();
+ console_init();
+
+ /* Halt if there was a built in self test failure */
+ report_bist_failure(bist);
+
+ print_debug("*sysinfo range: ["); print_debug_hex32(sysinfo); print_debug(","); print_debug_hex32((unsigned long)sysinfo+sizeof(struct sys_info)); print_debug(")\r\n");
+
+ setup_mb_resource_map();
+
+ print_debug("bsp_apicid="); print_debug_hex8(bsp_apicid); print_debug("\r\n");
+
+#if MEM_TRAIN_SEQ == 1
+ set_sysinfo_in_ram(0); // in BSP so could hold all ap until sysinfo is in ram
+#endif
+ setup_coherent_ht_domain(); // routing table and start other core0
+
+ wait_all_core0_started();
+#if CONFIG_LOGICAL_CPUS==1
+ // It is said that we should start core1 after all core0 launched
+ /* becase optimize_link_coherent_ht is moved out from setup_coherent_ht_domain,
+ * So here need to make sure last core0 is started, esp for two way system,
+ * (there may be apic id conflicts in that case)
+ */
+ start_other_cores();
+ wait_all_other_cores_started(bsp_apicid);
+#endif
+
+ /* it will set up chains and store link pair for optimization later */
+ ht_setup_chains_x(sysinfo); // it will init sblnk and sbbusn, nodes, sbdn
+
+
+#if K8_SET_FIDVID == 1
+
+ {
+ msr_t msr;
+ msr=rdmsr(0xc0010042);
+ print_debug("begin msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n");
+
+ }
+
+ enable_fid_change();
+
+ enable_fid_change_on_sb(sysinfo->sbbusn, sysinfo->sbdn);
+
+ init_fidvid_bsp(bsp_apicid);
+
+ // show final fid and vid
+ {
+ msr_t msr;
+ msr=rdmsr(0xc0010042);
+ print_debug("end msr fid, vid "); print_debug_hex32( msr.hi ); print_debug_hex32(msr.lo); print_debug("\r\n");
+
+ }
+#endif
+
+ needs_reset = optimize_link_coherent_ht();
+ needs_reset |= optimize_link_incoherent_ht(sysinfo);
+
+ // fidvid change will issue one LDTSTOP and the HT change will be effective too
+ if (needs_reset) {
+ print_info("ht reset -\r\n");
+ soft_reset_x(sysinfo->sbbusn, sysinfo->sbdn);
+ }
+
+ allow_all_aps_stop(bsp_apicid);
+
+ //It's the time to set ctrl in sysinfo now;
+ fill_mem_ctrl(sysinfo->nodes, sysinfo->ctrl, spd_addr);
+
+ enable_smbus();
+
+#if 0
+ dump_smbus_registers();
+#endif
+
+ memreset_setup();
+
+ //do we need apci timer, tsc...., only debug need it for better output
+ /* all ap stopped? */
+ init_timer(); // Need to use TMICT to synconize FID/VID
+ sdram_initialize(sysinfo->nodes, sysinfo->ctrl, sysinfo);
+
+
+#if 0
+ dump_pci_devices();
+#endif
+
+ post_cache_as_ram(); // bsp swtich stack to ram and copy sysinfo ram now
+
+}
+#endif
--- /dev/null
+extern struct chip_operations mainboard_Iwill_dk8_htx_ops;
+
+struct mainboard_Iwill_dk8_htx_config {
+// int fixup_scsi;
+// int fixup_vga;
+};
--- /dev/null
+entries
+
+#start-bit length config config-ID name
+#0 8 r 0 seconds
+#8 8 r 0 alarm_seconds
+#16 8 r 0 minutes
+#24 8 r 0 alarm_minutes
+#32 8 r 0 hours
+#40 8 r 0 alarm_hours
+#48 8 r 0 day_of_week
+#56 8 r 0 day_of_month
+#64 8 r 0 month
+#72 8 r 0 year
+#80 4 r 0 rate_select
+#84 3 r 0 REF_Clock
+#87 1 r 0 UIP
+#88 1 r 0 auto_switch_DST
+#89 1 r 0 24_hour_mode
+#90 1 r 0 binary_values_enable
+#91 1 r 0 square-wave_out_enable
+#92 1 r 0 update_finished_enable
+#93 1 r 0 alarm_interrupt_enable
+#94 1 r 0 periodic_interrupt_enable
+#95 1 r 0 disable_clock_updates
+#96 288 r 0 temporary_filler
+0 384 r 0 reserved_memory
+384 1 e 4 boot_option
+385 1 e 4 last_boot
+386 1 e 1 ECC_memory
+388 4 r 0 reboot_bits
+392 3 e 5 baud_rate
+395 1 e 1 hw_scrubber
+396 1 e 1 interleave_chip_selects
+397 2 e 8 max_mem_clock
+399 1 e 2 dual_core
+400 1 e 1 power_on_after_fail
+412 4 e 6 debug_level
+416 4 e 7 boot_first
+420 4 e 7 boot_second
+424 4 e 7 boot_third
+428 4 h 0 boot_index
+432 8 h 0 boot_countdown
+440 4 e 9 slow_cpu
+444 1 e 1 nmi
+445 1 e 1 iommu
+728 256 h 0 user_data
+984 16 h 0 check_sum
+# Reserve the extended AMD configuration registers
+1000 24 r 0 reserved_memory
+
+
+
+enumerations
+
+#ID value text
+1 0 Disable
+1 1 Enable
+2 0 Enable
+2 1 Disable
+4 0 Fallback
+4 1 Normal
+5 0 115200
+5 1 57600
+5 2 38400
+5 3 19200
+5 4 9600
+5 5 4800
+5 6 2400
+5 7 1200
+6 6 Notice
+6 7 Info
+6 8 Debug
+6 9 Spew
+7 0 Network
+7 1 HDD
+7 2 Floppy
+7 8 Fallback_Network
+7 9 Fallback_HDD
+7 10 Fallback_Floppy
+#7 3 ROM
+8 0 400Mhz
+8 1 333Mhz
+8 2 266Mhz
+8 3 200Mhz
+9 0 off
+9 1 87.5%
+9 2 75.0%
+9 3 62.5%
+9 4 50.0%
+9 5 37.5%
+9 6 25.0%
+9 7 12.5%
+
+checksums
+
+checksum 392 983 984
+
+
--- /dev/null
+/*
+ * Copyright 2005 AMD
+ */
+//AMD8111
+ Name (APIC, Package (0x04)
+ {
+ Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x10},// 0x0004ffff : assusme 8131 is present
+ Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x11},
+ Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x12},
+ Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x13}
+ })
+
+ Name (PICM, Package (0x04)
+ {
+ Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI0.LNKA, 0x00},
+ Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI0.LNKB, 0x00},
+ Package (0x04) { 0x0004FFFF, 0x02, \_SB.PCI0.LNKC, 0x00},
+ Package (0x04) { 0x0004FFFF, 0x03, \_SB.PCI0.LNKD, 0x00}
+ })
+
+ Name (DNCG, Ones)
+
+ Method (_PRT, 0, NotSerialized)
+ {
+ If (LEqual (^DNCG, Ones)) {
+ Store (DADD(\_SB.PCI0.SBDN, 0x0001ffff), Local0)
+ // Update the Device Number according to SBDN
+ Store(Local0, Index (DeRefOf (Index (PICM, 0)), 0))
+ Store(Local0, Index (DeRefOf (Index (PICM, 1)), 0))
+ Store(Local0, Index (DeRefOf (Index (PICM, 2)), 0))
+ Store(Local0, Index (DeRefOf (Index (PICM, 3)), 0))
+
+ Store(Local0, Index (DeRefOf (Index (APIC, 0)), 0))
+ Store(Local0, Index (DeRefOf (Index (APIC, 1)), 0))
+ Store(Local0, Index (DeRefOf (Index (APIC, 2)), 0))
+ Store(Local0, Index (DeRefOf (Index (APIC, 3)), 0))
+
+ Store (0x00, ^DNCG)
+
+ }
+
+ If (LNot (PICF)) {
+ Return (PICM)
+ }
+ Else {
+ Return (APIC)
+ }
+ }
+
+ Device (SBC3)
+ {
+ /* acpi smbus it should be 0x00040003 if 8131 present */
+ Method (_ADR, 0, NotSerialized)
+ {
+ Return (DADD(\_SB.PCI0.SBDN, 0x00010003))
+ }
+ OperationRegion (PIRQ, PCI_Config, 0x56, 0x02)
+ Field (PIRQ, ByteAcc, Lock, Preserve)
+ {
+ PIBA, 8,
+ PIDC, 8
+ }
+/*
+ OperationRegion (TS3_, PCI_Config, 0xC4, 0x02)
+ Field (TS3_, DWordAcc, NoLock, Preserve)
+ {
+ PTS3, 16
+ }
+*/
+ }
+
+ Device (HPET)
+ {
+ Name (HPT, 0x00)
+ Name (_HID, EisaId ("PNP0103"))
+ Name (_UID, 0x00)
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (0x0F)
+ }
+
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (BUF0, ResourceTemplate ()
+ {
+ Memory32Fixed (ReadWrite, 0xFED00000, 0x00000400)
+ })
+ Return (BUF0)
+ }
+ }
+
+ Include ("amd8111_pic.asl")
+
+ Include ("amd8111_isa.asl")
+
+ Device (TP2P)
+ {
+ /* 8111 P2P and it should 0x00030000 when 8131 present*/
+ Method (_ADR, 0, NotSerialized)
+ {
+ Return (DADD(\_SB.PCI0.SBDN, 0x00000000))
+ }
+
+ Method (_PRW, 0, NotSerialized)
+ {
+ If (CondRefOf (\_S3, Local0)) { Return (Package (0x02) { 0x08, 0x03 }) }
+ Else { Return (Package (0x02) { 0x08, 0x01 }) }
+ }
+
+ Device (USB0)
+ {
+ Name (_ADR, 0x00000000)
+ Method (_PRW, 0, NotSerialized)
+ {
+ If (CondRefOf (\_S3, Local0)) { Return (Package (0x02) { 0x0F, 0x03 }) }
+ Else { Return (Package (0x02) { 0x0F, 0x01 }) }
+ }
+ }
+
+ Device (USB1)
+ {
+ Name (_ADR, 0x00000001)
+ Method (_PRW, 0, NotSerialized)
+ {
+ If (CondRefOf (\_S3, Local0)) { Return (Package (0x02) { 0x0F, 0x03 }) }
+ Else { Return (Package (0x02) { 0x0F, 0x01 }) }
+ }
+ }
+
+ Name (APIC, Package (0x0C)
+ {
+ Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x10 }, //USB
+ Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x11 },
+ Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x12 },
+ Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x13 },
+
+ Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x10 }, //Slot 6
+ Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x11 },
+ Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x12 },
+ Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x13 },
+
+ Package (0x04) { 0x0005FFFF, 0x00, 0x00, 0x11 }, //Slot 5
+ Package (0x04) { 0x0005FFFF, 0x01, 0x00, 0x12 },
+ Package (0x04) { 0x0005FFFF, 0x02, 0x00, 0x13 },
+ Package (0x04) { 0x0005FFFF, 0x03, 0x00, 0x10 }
+ })
+
+ Name (PICM, Package (0x0C)
+ {
+ Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 }, //USB
+ Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
+ Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
+ Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 },
+
+ Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 }, //Slot 6
+ Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
+ Package (0x04) { 0x0004FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
+ Package (0x04) { 0x0004FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 },
+
+ Package (0x04) { 0x0005FFFF, 0x00, \_SB.PCI0.LNKB, 0x00 }, //Slot 5
+ Package (0x04) { 0x0005FFFF, 0x01, \_SB.PCI0.LNKC, 0x00 },
+ Package (0x04) { 0x0005FFFF, 0x02, \_SB.PCI0.LNKD, 0x00 },
+ Package (0x04) { 0x0005FFFF, 0x03, \_SB.PCI0.LNKA, 0x00 }
+ })
+
+ Method (_PRT, 0, NotSerialized)
+ {
+ If (LNot (PICF)) { Return (PICM) }
+ Else { Return (APIC) }
+ }
+ }
+
--- /dev/null
+/*
+ * Copyright 2005 AMD
+ */
+//AMD8111 isa
+
+ Device (ISA)
+ {
+ /* lpc 0x00040000 */
+ Method (_ADR, 0, NotSerialized)
+ {
+ Return (DADD(\_SB.PCI0.SBDN, 0x00010000))
+ }
+
+ OperationRegion (PIRY, PCI_Config, 0x51, 0x02) // LPC Decode Registers
+ Field (PIRY, ByteAcc, NoLock, Preserve)
+ {
+ Z000, 2, // Parallel Port Range
+ , 1,
+ ECP, 1, // ECP Enable
+ FDC1, 1, // Floppy Drive Controller 1
+ FDC2, 1, // Floppy Drive Controller 2
+ Offset (0x01),
+ Z001, 3, // Serial Port A Range
+ SAEN, 1, // Serial Post A Enabled
+ Z002, 3, // Serial Port B Range
+ SBEN, 1 // Serial Post B Enabled
+ }
+
+ Device (PIC)
+ {
+ Name (_HID, EisaId ("PNP0000"))
+ Name (_CRS, ResourceTemplate ()
+ {
+ IO (Decode16, 0x0020, 0x0020, 0x01, 0x02)
+ IO (Decode16, 0x00A0, 0x00A0, 0x01, 0x02)
+ IRQ (Edge, ActiveHigh, Exclusive) {2}
+ })
+ }
+
+ Device (DMA1)
+ {
+ Name (_HID, EisaId ("PNP0200"))
+ Name (_CRS, ResourceTemplate ()
+ {
+ IO (Decode16, 0x0000, 0x0000, 0x01, 0x10)
+ IO (Decode16, 0x0080, 0x0080, 0x01, 0x10)
+ IO (Decode16, 0x00C0, 0x00C0, 0x01, 0x20)
+ DMA (Compatibility, NotBusMaster, Transfer16) {4}
+ })
+ }
+
+ Device (TMR)
+ {
+ Name (_HID, EisaId ("PNP0100"))
+ Name (_CRS, ResourceTemplate ()
+ {
+ IO (Decode16, 0x0040, 0x0040, 0x01, 0x04)
+ IRQ (Edge, ActiveHigh, Exclusive) {0}
+ })
+ }
+
+ Device (RTC)
+ {
+ Name (_HID, EisaId ("PNP0B00"))
+ Name (_CRS, ResourceTemplate ()
+ {
+ IO (Decode16, 0x0070, 0x0070, 0x01, 0x06)
+ IRQ (Edge, ActiveHigh, Exclusive) {8}
+ })
+ }
+
+ Device (SPKR)
+ {
+ Name (_HID, EisaId ("PNP0800"))
+ Name (_CRS, ResourceTemplate ()
+ {
+ IO (Decode16, 0x0061, 0x0061, 0x01, 0x01)
+ })
+ }
+
+ Device (COPR)
+ {
+ Name (_HID, EisaId ("PNP0C04"))
+ Name (_CRS, ResourceTemplate ()
+ {
+ IO (Decode16, 0x00F0, 0x00F0, 0x01, 0x10)
+ IRQ (Edge, ActiveHigh, Exclusive) {13}
+ })
+ }
+
+ Device (SYSR)
+ {
+ Name (_HID, EisaId ("PNP0C02"))
+ Name (_UID, 0x00)
+ Name (SYR1, ResourceTemplate ()
+ {
+ IO (Decode16, 0x04D0, 0x04D0, 0x01, 0x02) //wrh092302 - added to report Thor NVRAM
+ IO (Decode16, 0x1100, 0x117F, 0x01, 0x80) //wrh092302 - added to report Thor NVRAM
+ IO (Decode16, 0x1180, 0x11FF, 0x01, 0x80)
+ IO (Decode16, 0x0010, 0x0010, 0x01, 0x10)
+ IO (Decode16, 0x0022, 0x0022, 0x01, 0x1E)
+ IO (Decode16, 0x0044, 0x0044, 0x01, 0x1C)
+ IO (Decode16, 0x0062, 0x0062, 0x01, 0x02)
+ IO (Decode16, 0x0065, 0x0065, 0x01, 0x0B)
+ IO (Decode16, 0x0076, 0x0076, 0x01, 0x0A)
+ IO (Decode16, 0x0090, 0x0090, 0x01, 0x10)
+ IO (Decode16, 0x00A2, 0x00A2, 0x01, 0x1E)
+ IO (Decode16, 0x00E0, 0x00E0, 0x01, 0x10)
+ IO (Decode16, 0x0B78, 0x0B78, 0x01, 0x04) // Added this to remove ACPI Unrepoted IO Error
+ IO (Decode16, 0x0190, 0x0190, 0x01, 0x04) // Added this to remove ACPI Unrepoted IO Error
+ })
+ Method (_CRS, 0, NotSerialized)
+ {
+ Return (SYR1)
+ }
+ }
+
+ Device (MEM)
+ {
+ Name (_HID, EisaId ("PNP0C02"))
+ Name (_UID, 0x01)
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (BUF0, ResourceTemplate ()
+ {
+ Memory32Fixed (ReadWrite, 0x000E0000, 0x00020000) // BIOS E4000-FFFFF
+ Memory32Fixed (ReadWrite, 0x000C0000, 0x00000000) // video BIOS c0000-c8404
+ Memory32Fixed (ReadWrite, 0xFEC00000, 0x00001000) // I/O APIC
+ Memory32Fixed (ReadWrite, 0xFFC00000, 0x00380000) // LPC forwarded, 4 MB w/ROM
+ Memory32Fixed (ReadWrite, 0xFEE00000, 0x00001000) // Local APIC
+ Memory32Fixed (ReadWrite, 0xFFF80000, 0x00080000) // Overlay BIOS
+ Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) // Overlay BIOS
+ Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) // Overlay BIOS
+ Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) //Overlay BIOS
+ Memory32Fixed (ReadWrite, 0x00000000, 0x00000000) //Overlay BIOS
+ })
+ // Read the Video Memory length
+ CreateDWordField (BUF0, 0x14, CLEN)
+ CreateDWordField (BUF0, 0x10, CBAS)
+
+ ShiftLeft (VGA1, 0x09, Local0)
+ Store (Local0, CLEN)
+
+ Return (BUF0)
+ }
+ }
+
+ Device (PS2M)
+ {
+ Name (_HID, EisaId ("PNP0F13"))
+ Name (_CRS, ResourceTemplate ()
+ {
+ IRQNoFlags () {12}
+ })
+ Method (_STA, 0, NotSerialized)
+ {
+ And (FLG0, 0x04, Local0)
+ If (LEqual (Local0, 0x04)) { Return (0x0F) }
+ Else { Return (0x00) }
+ }
+ }
+
+ Device (PS2K)
+ {
+ Name (_HID, EisaId ("PNP0303"))
+ Name (_CRS, ResourceTemplate ()
+ {
+ IO (Decode16, 0x0060, 0x0060, 0x01, 0x01)
+ IO (Decode16, 0x0064, 0x0064, 0x01, 0x01)
+ IRQNoFlags () {1}
+ })
+ }
+ Include ("superio.asl")
+
+ }
+
--- /dev/null
+/*
+ * Copyright 2005 AMD
+ */
+//AMD8111 pic LNKA B C D
+
+ Device (LNKA)
+ {
+ Name (_HID, EisaId ("PNP0C0F"))
+ Name (_UID, 0x01)
+ Method (_STA, 0, NotSerialized)
+ {
+ And (\_SB.PCI0.SBC3.PIBA, 0x0F, Local0)
+ If (LEqual (Local0, 0x00)) { Return (0x09) } //Disabled
+ Else { Return (0x0B) } //Enabled
+ }
+
+ Method (_PRS, 0, NotSerialized)
+ {
+ Name (BUFA, ResourceTemplate ()
+ {
+ IRQ (Level, ActiveLow, Shared) {3,5,10,11}
+ })
+ Return (BUFA)
+ }
+
+ Method (_DIS, 0, NotSerialized)
+ {
+ Store (0x01, Local3)
+ And (\_SB.PCI0.SBC3.PIBA, 0x0F, Local1)
+ Store (Local1, Local2)
+ If (LGreater (Local1, 0x07))
+ {
+ Subtract (Local1, 0x08, Local1)
+ }
+
+ ShiftLeft (Local3, Local1, Local3)
+ Not (Local3, Local3)
+ And (\_SB.PCI0.SBC3.PIBA, 0xF0, \_SB.PCI0.SBC3.PIBA)
+ }
+
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (BUFA, ResourceTemplate ()
+ {
+ IRQ (Level, ActiveLow, Shared) {}
+ })
+ CreateByteField (BUFA, 0x01, IRA1)
+ CreateByteField (BUFA, 0x02, IRA2)
+ Store (0x00, Local3)
+ Store (0x00, Local4)
+ And (\_SB.PCI0.SBC3.PIBA, 0x0F, Local1)
+ If (LNot (LEqual (Local1, 0x00)))
+ { // Routing enable
+ If (LGreater (Local1, 0x07))
+ {
+ Subtract (Local1, 0x08, Local2)
+ ShiftLeft (One, Local2, Local4)
+ }
+ Else
+ {
+ If (LGreater (Local1, 0x00))
+ {
+ ShiftLeft (One, Local1, Local3)
+ }
+ }
+
+ Store (Local3, IRA1)
+ Store (Local4, IRA2)
+ }
+
+ Return (BUFA)
+ }
+
+ Method (_SRS, 1, NotSerialized)
+ {
+ CreateByteField (Arg0, 0x01, IRA1)
+ CreateByteField (Arg0, 0x02, IRA2)
+ ShiftLeft (IRA2, 0x08, Local0)
+ Or (Local0, IRA1, Local0)
+ Store (0x00, Local1)
+ ShiftRight (Local0, 0x01, Local0)
+ While (LGreater (Local0, 0x00))
+ {
+ Increment (Local1)
+ ShiftRight (Local0, 0x01, Local0)
+ }
+
+ And (\_SB.PCI0.SBC3.PIBA, 0xF0, \_SB.PCI0.SBC3.PIBA)
+ Or (\_SB.PCI0.SBC3.PIBA, Local1, \_SB.PCI0.SBC3.PIBA)
+ }
+ }
+
+ Device (LNKB)
+ {
+ Name (_HID, EisaId ("PNP0C0F"))
+ Name (_UID, 0x02)
+ Method (_STA, 0, NotSerialized)
+ {
+ And (\_SB.PCI0.SBC3.PIBA, 0xF0, Local0)
+ If (LEqual (Local0, 0x00)) { Return (0x09) }
+ Else { Return (0x0B) }
+ }
+
+ Method (_PRS, 0, NotSerialized)
+ {
+ Name (BUFB, ResourceTemplate ()
+ {
+ IRQ (Level, ActiveLow, Shared) {3,5,10,11}
+ })
+ Return (BUFB)
+ }
+
+ Method (_DIS, 0, NotSerialized)
+ {
+ Store (0x01, Local3)
+ And (\_SB.PCI0.SBC3.PIBA, 0xF0, Local1)
+ ShiftRight (Local1, 0x04, Local1)
+ Store (Local1, Local2)
+ If (LGreater (Local1, 0x07))
+ {
+ Subtract (Local1, 0x08, Local1)
+ }
+
+ ShiftLeft (Local3, Local1, Local3)
+ Not (Local3, Local3)
+ And (\_SB.PCI0.SBC3.PIBA, 0x0F, \_SB.PCI0.SBC3.PIBA)
+ }
+
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (BUFB, ResourceTemplate ()
+ {
+ IRQ (Level, ActiveLow, Shared) {}
+ })
+ CreateByteField (BUFB, 0x01, IRB1)
+ CreateByteField (BUFB, 0x02, IRB2)
+ Store (0x00, Local3)
+ Store (0x00, Local4)
+ And (\_SB.PCI0.SBC3.PIBA, 0xF0, Local1)
+ ShiftRight (Local1, 0x04, Local1)
+ If (LNot (LEqual (Local1, 0x00)))
+ {
+ If (LGreater (Local1, 0x07))
+ {
+ Subtract (Local1, 0x08, Local2)
+ ShiftLeft (One, Local2, Local4)
+ }
+ Else
+ {
+ If (LGreater (Local1, 0x00))
+ {
+ ShiftLeft (One, Local1, Local3)
+ }
+ }
+
+ Store (Local3, IRB1)
+ Store (Local4, IRB2)
+ }
+
+ Return (BUFB)
+ }
+
+ Method (_SRS, 1, NotSerialized)
+ {
+ CreateByteField (Arg0, 0x01, IRB1)
+ CreateByteField (Arg0, 0x02, IRB2)
+ ShiftLeft (IRB2, 0x08, Local0)
+ Or (Local0, IRB1, Local0)
+ Store (0x00, Local1)
+ ShiftRight (Local0, 0x01, Local0)
+ While (LGreater (Local0, 0x00))
+ {
+ Increment (Local1)
+ ShiftRight (Local0, 0x01, Local0)
+ }
+
+ And (\_SB.PCI0.SBC3.PIBA, 0x0F, \_SB.PCI0.SBC3.PIBA)
+ ShiftLeft (Local1, 0x04, Local1)
+ Or (\_SB.PCI0.SBC3.PIBA, Local1, \_SB.PCI0.SBC3.PIBA)
+ }
+ }
+
+ Device (LNKC)
+ {
+ Name (_HID, EisaId ("PNP0C0F"))
+ Name (_UID, 0x03)
+ Method (_STA, 0, NotSerialized)
+ {
+ And (\_SB.PCI0.SBC3.PIDC, 0x0F, Local0)
+ If (LEqual (Local0, 0x00)) { Return (0x09) }
+ Else { Return (0x0B) }
+ }
+
+ Method (_PRS, 0, NotSerialized)
+ {
+ Name (BUFA, ResourceTemplate ()
+ {
+ IRQ (Level, ActiveLow, Shared) {3,5,10,11}
+ })
+ Return (BUFA)
+ }
+
+ Method (_DIS, 0, NotSerialized)
+ {
+ Store (0x01, Local3)
+ And (\_SB.PCI0.SBC3.PIDC, 0x0F, Local1)
+ Store (Local1, Local2)
+ If (LGreater (Local1, 0x07))
+ {
+ Subtract (Local1, 0x08, Local1)
+ }
+
+ ShiftLeft (Local3, Local1, Local3)
+ Not (Local3, Local3)
+ And (\_SB.PCI0.SBC3.PIDC, 0xF0, \_SB.PCI0.SBC3.PIDC)
+ }
+
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (BUFA, ResourceTemplate ()
+ {
+ IRQ (Level, ActiveLow, Shared) {}
+ })
+ CreateByteField (BUFA, 0x01, IRA1)
+ CreateByteField (BUFA, 0x02, IRA2)
+ Store (0x00, Local3)
+ Store (0x00, Local4)
+ And (\_SB.PCI0.SBC3.PIDC, 0x0F, Local1)
+ If (LNot (LEqual (Local1, 0x00)))
+ {
+ If (LGreater (Local1, 0x07))
+ {
+ Subtract (Local1, 0x08, Local2)
+ ShiftLeft (One, Local2, Local4)
+ }
+ Else
+ {
+ If (LGreater (Local1, 0x00))
+ {
+ ShiftLeft (One, Local1, Local3)
+ }
+ }
+
+ Store (Local3, IRA1)
+ Store (Local4, IRA2)
+ }
+
+ Return (BUFA)
+ }
+
+ Method (_SRS, 1, NotSerialized)
+ {
+ CreateByteField (Arg0, 0x01, IRA1)
+ CreateByteField (Arg0, 0x02, IRA2)
+ ShiftLeft (IRA2, 0x08, Local0)
+ Or (Local0, IRA1, Local0)
+ Store (0x00, Local1)
+ ShiftRight (Local0, 0x01, Local0)
+ While (LGreater (Local0, 0x00))
+ {
+ Increment (Local1)
+ ShiftRight (Local0, 0x01, Local0)
+ }
+
+ And (\_SB.PCI0.SBC3.PIDC, 0xF0, \_SB.PCI0.SBC3.PIDC)
+ Or (\_SB.PCI0.SBC3.PIDC, Local1, \_SB.PCI0.SBC3.PIDC)
+ }
+ }
+
+ Device (LNKD)
+ {
+ Name (_HID, EisaId ("PNP0C0F"))
+ Name (_UID, 0x04)
+ Method (_STA, 0, NotSerialized)
+ {
+ And (\_SB.PCI0.SBC3.PIDC, 0xF0, Local0)
+ If (LEqual (Local0, 0x00)) { Return (0x09) }
+ Else { Return (0x0B) }
+ }
+
+ Method (_PRS, 0, NotSerialized)
+ {
+ Name (BUFB, ResourceTemplate ()
+ {
+ IRQ (Level, ActiveLow, Shared) {3,5,10,11}
+ })
+ Return (BUFB)
+ }
+
+ Method (_DIS, 0, NotSerialized)
+ {
+ Store (0x01, Local3)
+ And (\_SB.PCI0.SBC3.PIDC, 0xF0, Local1)
+ ShiftRight (Local1, 0x04, Local1)
+ Store (Local1, Local2)
+ If (LGreater (Local1, 0x07))
+ {
+ Subtract (Local1, 0x08, Local1)
+ }
+
+ ShiftLeft (Local3, Local1, Local3)
+ Not (Local3, Local3)
+ And (\_SB.PCI0.SBC3.PIDC, 0x0F, \_SB.PCI0.SBC3.PIDC)
+ }
+
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (BUFB, ResourceTemplate ()
+ {
+ IRQ (Level, ActiveLow, Shared) {}
+ })
+ CreateByteField (BUFB, 0x01, IRB1)
+ CreateByteField (BUFB, 0x02, IRB2)
+ Store (0x00, Local3)
+ Store (0x00, Local4)
+ And (\_SB.PCI0.SBC3.PIDC, 0xF0, Local1)
+ ShiftRight (Local1, 0x04, Local1)
+ If (LNot (LEqual (Local1, 0x00)))
+ {
+ If (LGreater (Local1, 0x07))
+ {
+ Subtract (Local1, 0x08, Local2)
+ ShiftLeft (One, Local2, Local4)
+ }
+ Else
+ {
+ If (LGreater (Local1, 0x00))
+ {
+ ShiftLeft (One, Local1, Local3)
+ }
+ }
+
+ Store (Local3, IRB1)
+ Store (Local4, IRB2)
+ }
+
+ Return (BUFB)
+ }
+
+ Method (_SRS, 1, NotSerialized)
+ {
+ CreateByteField (Arg0, 0x01, IRB1)
+ CreateByteField (Arg0, 0x02, IRB2)
+ ShiftLeft (IRB2, 0x08, Local0)
+ Or (Local0, IRB1, Local0)
+ Store (0x00, Local1)
+ ShiftRight (Local0, 0x01, Local0)
+ While (LGreater (Local0, 0x00))
+ {
+ Increment (Local1)
+ ShiftRight (Local0, 0x01, Local0)
+ }
+
+ And (\_SB.PCI0.SBC3.PIDC, 0x0F, \_SB.PCI0.SBC3.PIDC)
+ ShiftLeft (Local1, 0x04, Local1)
+ Or (\_SB.PCI0.SBC3.PIDC, Local1, \_SB.PCI0.SBC3.PIDC)
+ }
+ }
+
+
--- /dev/null
+/*
+ * Copyright 2005 AMD
+ */
+
+ Device (PG0A)
+ {
+ /* 8132 pcix bridge*/
+ Method (_ADR, 0, NotSerialized)
+ {
+ Return (DADD(GHCD(HCIN, 0), 0x00000000))
+ }
+
+ Method (_PRW, 0, NotSerialized)
+ {
+ If (CondRefOf (\_S3, Local0)) { Return (Package (0x02) { 0x29, 0x03 }) }
+ Else { Return (Package (0x02) { 0x29, 0x01 }) }
+ }
+
+ Name (APIC, Package (0x14)
+ {
+ // Slot 3 - PIRQ BCDA ---- verified
+ Package (0x04) { 0x0001FFFF, 0x00, 0x00, 0x19 }, //Slot 3
+ Package (0x04) { 0x0001FFFF, 0x01, 0x00, 0x1A },
+ Package (0x04) { 0x0001FFFF, 0x02, 0x00, 0x1B },
+ Package (0x04) { 0x0001FFFF, 0x03, 0x00, 0x18 },
+
+ //Slot 4 - PIRQ CDAB ---- verified
+ Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x1A }, //?
+ Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x1B },
+ Package (0x04) { 0x0002FFFF, 0x02, 0x00, 0x18 },
+ Package (0x04) { 0x0002FFFF, 0x03, 0x00, 0x19 },
+
+ //Onboard NIC 1 - PIRQ DABC
+ Package (0x04) { 0x0003FFFF, 0x00, 0x00, 0x1B }, //?
+ Package (0x04) { 0x0003FFFF, 0x01, 0x00, 0x18 },
+ Package (0x04) { 0x0003FFFF, 0x02, 0x00, 0x19 },
+ Package (0x04) { 0x0003FFFF, 0x03, 0x00, 0x1A },
+
+ // NIC 2 - PIRQ ABCD -- verified
+ Package (0x04) { 0x0004FFFF, 0x00, 0x00, 0x18 }, //?
+ Package (0x04) { 0x0004FFFF, 0x01, 0x00, 0x19 },
+ Package (0x04) { 0x0004FFFF, 0x02, 0x00, 0x1A },
+ Package (0x04) { 0x0004FFFF, 0x03, 0x00, 0x1B },
+
+ //SERIAL ATA - PIRQ BCDA
+ Package (0x04) { 0x0005FFFF, 0x00, 0x00, 0x19 }, //?
+ Package (0x04) { 0x0005FFFF, 0x01, 0x00, 0x1A },
+ Package (0x04) { 0x0005FFFF, 0x02, 0x00, 0x1B },
+ Package (0x04) { 0x0005FFFF, 0x03, 0x00, 0x18 }
+ })
+ Name (PICM, Package (0x14)
+ {
+ Package (0x04) { 0x0001FFFF, 0x00, \_SB.PCI0.LNKB, 0x00 },//Slot 3
+ Package (0x04) { 0x0001FFFF, 0x01, \_SB.PCI0.LNKC, 0x00 },
+ Package (0x04) { 0x0001FFFF, 0x02, \_SB.PCI0.LNKD, 0x00 },
+ Package (0x04) { 0x0001FFFF, 0x03, \_SB.PCI0.LNKA, 0x00 },
+
+ Package (0x04) { 0x0002FFFF, 0x00, \_SB.PCI0.LNKC, 0x00 },
+ Package (0x04) { 0x0002FFFF, 0x01, \_SB.PCI0.LNKD, 0x00 },
+ Package (0x04) { 0x0002FFFF, 0x02, \_SB.PCI0.LNKA, 0x00 },
+ Package (0x04) { 0x0002FFFF, 0x03, \_SB.PCI0.LNKB, 0x00 },
+
+ Package (0x04) { 0x0003FFFF, 0x00, \_SB.PCI0.LNKD, 0x00 },
+ Package (0x04) { 0x0003FFFF, 0x01, \_SB.PCI0.LNKA, 0x00 },
+ Package (0x04) { 0x0003FFFF, 0x02, \_SB.PCI0.LNKB, 0x00 },
+ Package (0x04) { 0x0003FFFF, 0x03, \_SB.PCI0.LNKC, 0x00 },
+
+ Package (0x04) { 0x0004FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },
+ Package (0x04) { 0x0004FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
+ Package (0x04) { 0x0004FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
+ Package (0x04) { 0x0004FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 },
+
+ Package (0x04) { 0x0005FFFF, 0x00, \_SB.PCI0.LNKB, 0x00 },
+ Package (0x04) { 0x0005FFFF, 0x01, \_SB.PCI0.LNKC, 0x00 },
+ Package (0x04) { 0x0005FFFF, 0x02, \_SB.PCI0.LNKD, 0x00 },
+ Package (0x04) { 0x0005FFFF, 0x03, \_SB.PCI0.LNKA, 0x00 }
+ })
+ Method (_PRT, 0, NotSerialized)
+ {
+ If (LNot (PICF)) { Return (PICM) }
+ Else { Return (APIC) }
+ }
+ }
+
+ Device (PG0B)
+ {
+ /* 8132 pcix bridge 2 */
+ Method (_ADR, 0, NotSerialized)
+ {
+ Return (DADD(GHCD(HCIN, 0), 0x00010000))
+ }
+
+ Method (_PRW, 0, NotSerialized)
+ {
+ If (CondRefOf (\_S3, Local0)) { Return (Package (0x02) { 0x22, 0x03 }) }
+ Else { Return (Package (0x02) { 0x22, 0x01 }) }
+ }
+
+ Name (APIC, Package (0x04)
+ {
+ // Slot A - PIRQ CDAB -- verfied
+ Package (0x04) { 0x0002FFFF, 0x00, 0x00, 0x1E },// Slot 2
+ Package (0x04) { 0x0002FFFF, 0x01, 0x00, 0x1F },
+ Package (0x04) { 0x0002FFFF, 0x02, 0x00, 0x1C },
+ Package (0x04) { 0x0002FFFF, 0x03, 0x00, 0x1D }
+ })
+ Name (PICM, Package (0x04)
+ {
+ Package (0x04) { 0x0002FFFF, 0x00, \_SB.PCI0.LNKC, 0x00 },//Slot 2
+ Package (0x04) { 0x0002FFFF, 0x01, \_SB.PCI0.LNKD, 0x00 },
+ Package (0x04) { 0x0002FFFF, 0x02, \_SB.PCI0.LNKA, 0x00 },
+ Package (0x04) { 0x0002FFFF, 0x03, \_SB.PCI0.LNKB, 0x00 }
+ })
+ Method (_PRT, 0, NotSerialized)
+ {
+ If (LNot (PICF)) { Return (PICM) }
+ Else { Return (APIC) }
+ }
+ }
--- /dev/null
+/*
+ * Copyright 2005 AMD
+ */
+
+ Device (PG0A)
+ {
+ /* 8132 pcix bridge*/
+ Method (_ADR, 0, NotSerialized)
+ {
+ Return (DADD(GHCD(HCIN, 0), 0x00000000))
+ }
+
+ Method (_PRW, 0, NotSerialized)
+ {
+ If (CondRefOf (\_S3, Local0)) { Return (Package (0x02) { 0x29, 0x03 }) }
+ Else { Return (Package (0x02) { 0x29, 0x01 }) }
+ }
+
+ Name (APIC, Package (0x04)
+ {
+ // Slot A - PIRQ BCDA
+ Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x0018 }, //Slot 2
+ Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x0019 },
+ Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x001A },
+ Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x001B },
+
+ })
+ Name (PICM, Package (0x04)
+ {
+ Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },//Slot 2
+ Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
+ Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
+ Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 },
+ })
+
+ Name (DNCG, Ones)
+
+ Method (_PRT, 0, NotSerialized)
+ {
+ If (LEqual (^DNCG, Ones)) {
+ Multiply (HCIN, 0x0008, Local2) // GSI for 8132 is 4 so we get 8
+ Store (0x00, Local1)
+ While (LLess (Local1, 0x04))
+ {
+ // Update the GSI according to HCIN
+ Store(DeRefOf(Index (DeRefOf (Index (APIC, Local1)), 3)), Local0)
+ Add(Local2, Local0, Local0)
+ Store(Local0, Index (DeRefOf (Index (APIC, Local1)), 3))
+ Increment (Local1)
+ }
+
+ Store (0x00, ^DNCG)
+
+ }
+
+ If (LNot (PICF)) { Return (PICM) }
+ Else { Return (APIC) }
+ }
+ }
+
+ Device (PG0B)
+ {
+ /* 8132 pcix bridge 2 */
+ Method (_ADR, 0, NotSerialized)
+ {
+ Return (DADD(GHCD(HCIN, 0), 0x00010000))
+ }
+
+ Method (_PRW, 0, NotSerialized)
+ {
+ If (CondRefOf (\_S3, Local0)) { Return (Package (0x02) { 0x22, 0x03 }) }
+ Else { Return (Package (0x02) { 0x22, 0x01 }) }
+ }
+
+ Name (APIC, Package (0x04)
+ {
+ // Slot A - PIRQ ABCD
+ Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x001F },// Slot 1
+ Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x0020 },
+ Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x0021 },
+ Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x0022 }
+ })
+ Name (PICM, Package (0x04)
+ {
+ Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },//Slot 1
+ Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
+ Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
+ Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 }
+ })
+
+ Name (DNCG, Ones)
+
+ Method (_PRT, 0, NotSerialized)
+ {
+ If (LEqual (^DNCG, Ones)) {
+ Multiply (HCIN, 0x0008, Local2) // GSI for 8132 is 4 so we get 8
+ Store (0x00, Local1)
+ While (LLess (Local1, 0x04))
+ {
+ // Update the GSI according to HCIN
+ Store(DeRefOf(Index (DeRefOf (Index (APIC, Local1)), 3)), Local0)
+ Add(Local2, Local0, Local0)
+ Store(Local0, Index (DeRefOf (Index (APIC, Local1)), 3))
+ Increment (Local1)
+ }
+
+ Store (0x00, ^DNCG)
+
+ }
+
+ If (LNot (PICF)) { Return (PICM) }
+ Else { Return (APIC) }
+ }
+ }
--- /dev/null
+/*
+ * Copyright 2005 AMD
+ */
+
+ Device (PG0A)
+ {
+ /* 8132 pcix bridge*/
+ Method (_ADR, 0, NotSerialized)
+ {
+ Return (DADD(GHCD(HCIN, 0), 0x00000000))
+ }
+
+ Method (_PRW, 0, NotSerialized)
+ {
+ If (CondRefOf (\_S3, Local0)) { Return (Package (0x02) { 0x29, 0x03 }) }
+ Else { Return (Package (0x02) { 0x29, 0x01 }) }
+ }
+
+ Name (APIC, Package (0x04)
+ {
+ // Slot A - PIRQ BCDA
+ Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x0018 }, //Slot 2
+ Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x0019 },
+ Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x001A },
+ Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x001B },
+
+ })
+ Name (PICM, Package (0x04)
+ {
+ Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },//Slot 2
+ Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
+ Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
+ Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 },
+ })
+
+ Name (DNCG, Ones)
+
+ Method (_PRT, 0, NotSerialized)
+ {
+ If (LEqual (^DNCG, Ones)) {
+ Multiply (HCIN, 0x000e, Local2) // GSI for 8132 is 7 so we get 14
+ Store (0x00, Local1)
+ While (LLess (Local1, 0x04))
+ {
+ // Update the GSI according to HCIN
+ Store(DeRefOf(Index (DeRefOf (Index (APIC, Local1)), 3)), Local0)
+ Add(Local2, Local0, Local0)
+ Store(Local0, Index (DeRefOf (Index (APIC, Local1)), 3))
+ Increment (Local1)
+ }
+
+ Store (0x00, ^DNCG)
+
+ }
+
+ If (LNot (PICF)) { Return (PICM) }
+ Else { Return (APIC) }
+ }
+ }
+
+ Device (PG0B)
+ {
+ /* 8132 pcix bridge 2 */
+ Method (_ADR, 0, NotSerialized)
+ {
+ Return (DADD(GHCD(HCIN, 0), 0x00010000))
+ }
+
+ Method (_PRW, 0, NotSerialized)
+ {
+ If (CondRefOf (\_S3, Local0)) { Return (Package (0x02) { 0x22, 0x03 }) }
+ Else { Return (Package (0x02) { 0x22, 0x01 }) }
+ }
+
+ Name (APIC, Package (0x04)
+ {
+ // Slot A - PIRQ ABCD
+ Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x001F },// Slot 1
+ Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x0020 },
+ Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x0021 },
+ Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x0022 }
+ })
+ Name (PICM, Package (0x04)
+ {
+ Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },//Slot 1
+ Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
+ Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
+ Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 }
+ })
+
+ Name (DNCG, Ones)
+
+ Method (_PRT, 0, NotSerialized)
+ {
+ If (LEqual (^DNCG, Ones)) {
+ Multiply (HCIN, 0x000e, Local2) // GSI for 8132 is 7 so we get 14
+ Store (0x00, Local1)
+ While (LLess (Local1, 0x04))
+ {
+ // Update the GSI according to HCIN
+ Store(DeRefOf(Index (DeRefOf (Index (APIC, Local1)), 3)), Local0)
+ Add(Local2, Local0, Local0)
+ Store(Local0, Index (DeRefOf (Index (APIC, Local1)), 3))
+ Increment (Local1)
+ }
+
+ Store (0x00, ^DNCG)
+
+ }
+
+ If (LNot (PICF)) { Return (PICM) }
+ Else { Return (APIC) }
+ }
+ }
--- /dev/null
+// AMD8151
+ Device (AGPB)
+ {
+ Method (_ADR, 0, NotSerialized)
+ {
+ Return (DADD(GHCD(HCIN, 0), 0x00010000))
+ }
+
+ Name (APIC, Package (0x04)
+ {
+ Package (0x04) { 0x0000FFFF, 0x00, 0x00, 0x10 },
+ Package (0x04) { 0x0000FFFF, 0x01, 0x00, 0x11 },
+ Package (0x04) { 0x0000FFFF, 0x02, 0x00, 0x12 },
+ Package (0x04) { 0x0000FFFF, 0x03, 0x00, 0x13 }
+ })
+ Name (PICM, Package (0x04)
+ {
+ Package (0x04) { 0x0000FFFF, 0x00, \_SB.PCI0.LNKA, 0x00 },
+ Package (0x04) { 0x0000FFFF, 0x01, \_SB.PCI0.LNKB, 0x00 },
+ Package (0x04) { 0x0000FFFF, 0x02, \_SB.PCI0.LNKC, 0x00 },
+ Package (0x04) { 0x0000FFFF, 0x03, \_SB.PCI0.LNKD, 0x00 }
+ })
+ Method (_PRT, 0, NotSerialized)
+ {
+ If (LNot (PICF)) { Return (PICM) }
+ Else { Return (APIC) }
+ }
+ }
+
--- /dev/null
+/*
+ * Copyright 2005 AMD
+ */
+
+//AMD k8 util for BUSB and res range
+
+ Scope (\_SB)
+ {
+
+ Name (OSTB, Ones)
+ Method (OSTP, 0, NotSerialized)
+ {
+ If (LEqual (^OSTB, Ones))
+ {
+ Store (0x00, ^OSTB)
+ }
+
+ Return (^OSTB)
+ }
+
+ Method (SEQL, 2, Serialized)
+ {
+ Store (SizeOf (Arg0), Local0)
+ Store (SizeOf (Arg1), Local1)
+ If (LNot (LEqual (Local0, Local1))) { Return (Zero) }
+
+ Name (BUF0, Buffer (Local0) {})
+ Store (Arg0, BUF0)
+ Name (BUF1, Buffer (Local0) {})
+ Store (Arg1, BUF1)
+ Store (Zero, Local2)
+ While (LLess (Local2, Local0))
+ {
+ Store (DerefOf (Index (BUF0, Local2)), Local3)
+ Store (DerefOf (Index (BUF1, Local2)), Local4)
+ If (LNot (LEqual (Local3, Local4))) { Return (Zero) }
+
+ Increment (Local2)
+ }
+
+ Return (One)
+ }
+
+
+ Method (DADD, 2, NotSerialized)
+ {
+ Store( Arg1, Local0)
+ Store( Arg0, Local1)
+ Add( ShiftLeft(Local1,16), Local0, Local0)
+ Return (Local0)
+ }
+
+
+ Method (GHCE, 1, NotSerialized) // check if the HC enabled
+ {
+ Store (DerefOf (Index (\_SB.PCI0.HCLK, Arg0)), Local1)
+ if(LEqual ( And(Local1, 0x01), 0x01)) { Return (0x0F) }
+ Else { Return (0x00) }
+ }
+
+ Method (GHCN, 1, NotSerialized) // get the node num for the HC
+ {
+ Store (0x00, Local0)
+ Store (DerefOf (Index (\_SB.PCI0.HCLK, Arg0)), Local1)
+ Store (ShiftRight( And (Local1, 0xf0), 0x04), Local0)
+ Return (Local0)
+ }
+
+ Method (GHCL, 1, NotSerialized) // get the link num on node for the HC
+ {
+ Store (0x00, Local0)
+ Store (DerefOf (Index (\_SB.PCI0.HCLK, Arg0)), Local1)
+ Store (ShiftRight( And (Local1, 0xf00), 0x08), Local0)
+ Return (Local0)
+ }
+
+ Method (GHCD, 2, NotSerialized) // get the unit id base for the HT device in HC
+ {
+ Store (0x00, Local0)
+ Store (DerefOf (Index (\_SB.PCI0.HCDN, Arg0)), Local1)
+ Store (Arg1, Local2) // Arg1 could be 3, 2, 1, 0
+ Multiply (Local2, 0x08, Local2) // change to 24, 16, 8, 0
+ Store (And (ShiftRight( Local1, Local2), 0xff), Local0)
+ Return (Local0)
+ }
+
+ Method (GBUS, 2, NotSerialized)
+ {
+ Store (0x00, Local0)
+ While (LLess (Local0, 0x04))
+ {
+ Store (DerefOf (Index (\_SB.PCI0.BUSN, Local0)), Local1)
+ If (LEqual (And (Local1, 0x03), 0x03))
+ {
+ If (LEqual (Arg0, ShiftRight (And (Local1, 0x70), 0x04)))
+ {
+ If (LOr (LEqual (Arg1, 0xFF), LEqual (Arg1, ShiftRight (And (Local1, 0x0300), 0x08))))
+ {
+ Return (ShiftRight (And (Local1, 0x00FF0000), 0x10))
+ }
+ }
+ }
+
+ Increment (Local0)
+ }
+
+ Return (0x00)
+ }
+
+ Method (GWBN, 2, NotSerialized)
+ {
+ Name (BUF0, ResourceTemplate ()
+ {
+ WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode,
+ 0x0000, // Address Space Granularity
+ 0x0000, // Address Range Minimum
+ 0x0000, // Address Range Maximum
+ 0x0000, // Address Translation Offset
+ 0x0000,,,)
+ })
+ CreateWordField (BUF0, 0x08, BMIN)
+ CreateWordField (BUF0, 0x0A, BMAX)
+ CreateWordField (BUF0, 0x0E, BLEN)
+ Store (0x00, Local0)
+ While (LLess (Local0, 0x04))
+ {
+ Store (DerefOf (Index (\_SB.PCI0.BUSN, Local0)), Local1)
+ If (LEqual (And (Local1, 0x03), 0x03))
+ {
+ If (LEqual (Arg0, ShiftRight (And (Local1, 0x70), 0x04)))
+ {
+ If (LOr (LEqual (Arg1, 0xFF), LEqual (Arg1, ShiftRight (And (Local1, 0x0300), 0x08))))
+ {
+ Store (ShiftRight (And (Local1, 0x00FF0000), 0x10), BMIN)
+ Store (ShiftRight (Local1, 0x18), BMAX)
+ Subtract (BMAX, BMIN, BLEN)
+ Increment (BLEN)
+ Return (RTAG (BUF0))
+ }
+ }
+ }
+
+ Increment (Local0)
+ }
+
+ Return (RTAG (BUF0))
+ }
+
+ Method (GMEM, 2, NotSerialized)
+ {
+ Name (BUF0, ResourceTemplate ()
+ {
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite,
+ 0x00000000, // Address Space Granularity
+ 0x00000000, // Address Range Minimum
+ 0x00000000, // Address Range Maximum
+ 0x00000000, // Address Translation Offset
+ 0x00000000,,,
+ , AddressRangeMemory, TypeStatic)
+ })
+ CreateDWordField (BUF0, 0x0A, MMIN)
+ CreateDWordField (BUF0, 0x0E, MMAX)
+ CreateDWordField (BUF0, 0x16, MLEN)
+ Store (0x00, Local0)
+ Store (0x00, Local4)
+ Store (0x00, Local3)
+ While (LLess (Local0, 0x10))
+ {
+ Store (DerefOf (Index (\_SB.PCI0.MMIO, Local0)), Local1)
+ Increment (Local0)
+ Store (DerefOf (Index (\_SB.PCI0.MMIO, Local0)), Local2)
+ If (LEqual (And (Local1, 0x03), 0x03))
+ {
+ If (LEqual (Arg0, And (Local2, 0x07)))
+ {
+ If (LOr (LEqual (Arg1, 0xFF), LEqual (Arg1, ShiftRight (And (Local2, 0x30), 0x04))))
+ {
+ Store (ShiftLeft (And (Local1, 0xFFFFFF00), 0x08), MMIN)
+ Store (ShiftLeft (And (Local2, 0xFFFFFF00), 0x08), MMAX)
+ Or (MMAX, 0xFFFF, MMAX)
+ Subtract (MMAX, MMIN, MLEN)
+
+ If (Local4)
+ {
+ Concatenate (RTAG (BUF0), Local3, Local5)
+ Store (Local5, Local3)
+ }
+ Else
+ {
+ If (LOr (LAnd (LEqual (Arg1, 0xFF), LEqual (Arg0, 0x00)), LEqual (Arg1, \_SB.PCI0.SBLK)))
+ {
+ Store (\_SB.PCI0.TOM1, MMIN)
+ Subtract (MMAX, MMIN, MLEN)
+ Increment (MLEN)
+ }
+
+ Store (RTAG (BUF0), Local3)
+ }
+
+ Increment (Local4)
+ }
+ }
+ }
+
+ Increment (Local0)
+ }
+
+ If (LNot (Local4))
+ {
+ Store (BUF0, Local3)
+ }
+
+ Return (Local3)
+ }
+
+ Method (GIOR, 2, NotSerialized)
+ {
+ Name (BUF0, ResourceTemplate ()
+ {
+ DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x00000000, // Address Space Granularity
+ 0x00000000, // Address Range Minimum
+ 0x00000000, // Address Range Maximum
+ 0x00000000, // Address Translation Offset
+ 0x00000000,,,
+ , TypeStatic)
+ })
+ CreateDWordField (BUF0, 0x0A, PMIN)
+ CreateDWordField (BUF0, 0x0E, PMAX)
+ CreateDWordField (BUF0, 0x16, PLEN)
+ Store (0x00, Local0)
+ Store (0x00, Local4)
+ Store (0x00, Local3)
+ While (LLess (Local0, 0x08))
+ {
+ Store (DerefOf (Index (\_SB.PCI0.PCIO, Local0)), Local1)
+ Increment (Local0)
+ Store (DerefOf (Index (\_SB.PCI0.PCIO, Local0)), Local2)
+ If (LEqual (And (Local1, 0x03), 0x03))
+ {
+ If (LEqual (Arg0, And (Local2, 0x07)))
+ {
+ If (LOr (LEqual (Arg1, 0xFF), LEqual (Arg1, ShiftRight (And (Local2, 0x30), 0x04))))
+ {
+ Store (And (Local1, 0x01FFF000), PMIN)
+ Store (And (Local2, 0x01FFF000), PMAX)
+ Or (PMAX, 0x0FFF, PMAX)
+ Subtract (PMAX, PMIN, PLEN)
+ Increment (PLEN)
+
+ If (Local4)
+ {
+ Concatenate (RTAG (BUF0), Local3, Local5)
+ Store (Local5, Local3)
+ }
+ Else
+ {
+ If (LGreater (PMAX, PMIN))
+ {
+ If (LOr (LAnd (LEqual (Arg1, 0xFF), LEqual (Arg0, 0x00)), LEqual (Arg1, \_SB.PCI0.SBLK)))
+ {
+ Store (0x0D00, PMIN)
+ Subtract (PMAX, PMIN, PLEN)
+ Increment (PLEN)
+ }
+
+ Store (RTAG (BUF0), Local3)
+ Increment (Local4)
+ }
+
+ If (And (Local1, 0x10))
+ {
+ Store (0x03B0, PMIN)
+ Store (0x03DF, PMAX)
+ Store (0x30, PLEN)
+ If (Local4)
+ {
+ Concatenate (RTAG (BUF0), Local3, Local5)
+ Store (Local5, Local3)
+ }
+ Else
+ {
+ Store (RTAG (BUF0), Local3)
+ }
+ }
+ }
+
+ Increment (Local4)
+ }
+ }
+ }
+
+ Increment (Local0)
+ }
+
+ If (LNot (Local4))
+ {
+ Store (RTAG (BUF0), Local3)
+ }
+
+ Return (Local3)
+ }
+
+ Method (RTAG, 1, NotSerialized)
+ {
+ Store (Arg0, Local0)
+ Store (SizeOf (Local0), Local1)
+ Subtract (Local1, 0x02, Local1)
+ Multiply (Local1, 0x08, Local1)
+ CreateField (Local0, 0x00, Local1, RETB)
+ Store (RETB, Local2)
+ Return (Local2)
+ }
+ }
+
--- /dev/null
+/*
+ * Copyright 2005 AMD
+ */
+DefinitionBlock ("DSDT.aml", "DSDT", 1, "AMD-K8", "AMDACPI", 100925440)
+{
+ Scope (_PR)
+ {
+ Processor (CPU0, 0x00, 0x0000C010, 0x06) {}
+ Processor (CPU1, 0x01, 0x00000000, 0x00) {}
+ Processor (CPU2, 0x02, 0x00000000, 0x00) {}
+ Processor (CPU3, 0x03, 0x00000000, 0x00) {}
+
+ }
+
+ Method (FWSO, 0, NotSerialized) { }
+
+ Name (_S0, Package (0x04) { 0x00, 0x00, 0x00, 0x00 })
+ Name (_S1, Package (0x04) { 0x01, 0x01, 0x01, 0x01 })
+ Name (_S3, Package (0x04) { 0x05, 0x05, 0x05, 0x05 })
+ Name (_S5, Package (0x04) { 0x07, 0x07, 0x07, 0x07 })
+
+ Scope (_SB)
+ {
+ Device (PCI0)
+ {
+ /* BUS0 root bus */
+
+ External (BUSN)
+ External (MMIO)
+ External (PCIO)
+ External (SBLK)
+ External (TOM1)
+ External (HCLK)
+ External (SBDN)
+ External (HCDN)
+ External (CBST)
+
+
+ Name (_HID, EisaId ("PNP0A03"))
+ Name (_ADR, 0x00180000)
+ Name (_UID, 0x01)
+
+ Name (HCIN, 0x00) // HC1
+
+ Method (_BBN, 0, NotSerialized)
+ {
+ Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
+ }
+
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (BUF0, ResourceTemplate ()
+ {
+ IO (Decode16, 0x0CF8, 0x0CF8, 0x01, 0x08) //CF8-CFFh
+ IO (Decode16, 0xC000, 0xC000, 0x01, 0x80) //8000h
+ IO (Decode16, 0xC080, 0xC080, 0x01, 0x80) //8080h
+
+ WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, // Address Space Granularity
+ 0x8100, // Address Range Minimum
+ 0xFFFF, // Address Range Maximum
+ 0x0000, // Address Translation Offset
+ 0x7F00,,,
+ , TypeStatic) //8100h-FFFFh
+
+ DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite,
+ 0x00000000, // Address Space Granularity
+ 0x000C0000, // Address Range Minimum
+ 0x00000000, // Address Range Maximum
+ 0x00000000, // Address Translation Offset
+ 0x00000000,,,
+ , AddressRangeMemory, TypeStatic) //Video BIOS A0000h-C7FFFh
+
+ Memory32Fixed (ReadWrite, 0x000D8000, 0x00004000)//USB HC D8000-DBFFF
+
+ WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, // Address Space Granularity
+ 0x0000, // Address Range Minimum
+ 0x03AF, // Address Range Maximum
+ 0x0000, // Address Translation Offset
+ 0x03B0,,,
+ , TypeStatic) //0-CF7h
+
+ WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange,
+ 0x0000, // Address Space Granularity
+ 0x03E0, // Address Range Minimum
+ 0x0CF7, // Address Range Maximum
+ 0x0000, // Address Translation Offset
+ 0x0918,,,
+ , TypeStatic) //0-CF7h
+ })
+ \_SB.OSTP ()
+ CreateDWordField (BUF0, 0x3E, VLEN)
+ CreateDWordField (BUF0, 0x36, VMAX)
+ CreateDWordField (BUF0, 0x32, VMIN)
+ ShiftLeft (VGA1, 0x09, Local0)
+ Add (VMIN, Local0, VMAX)
+ Decrement (VMAX)
+ Store (Local0, VLEN)
+ Concatenate (\_SB.GMEM (0x00, \_SB.PCI0.SBLK), BUF0, Local1)
+ Concatenate (\_SB.GIOR (0x00, \_SB.PCI0.SBLK), Local1, Local2)
+ Concatenate (\_SB.GWBN (0x00, \_SB.PCI0.SBLK), Local2, Local3)
+ Return (Local3)
+ }
+
+ Include ("pci0_hc.asl")
+
+ }
+ Device (PCI1)
+ {
+ Name (_HID, "PNP0A03")
+ Name (_ADR, 0x00000000)
+ Name (_UID, 0x02)
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (\_SB.PCI0.CBST)
+ }
+ Name (_BBN, 0x00)
+ }
+
+
+ }
+
+ Scope (_GPE)
+ {
+ Method (_L08, 0, NotSerialized)
+ {
+ Notify (\_SB.PCI0, 0x02) //PME# Wakeup
+ }
+
+ Method (_L0F, 0, NotSerialized)
+ {
+ Notify (\_SB.PCI0.TP2P.USB0, 0x02) //USB Wakeup
+ }
+
+ Method (_L22, 0, NotSerialized) // GPIO18 (LID) - Pogo 0 Bridge B
+ {
+ Notify (\_SB.PCI0.PG0B, 0x02)
+ }
+
+ Method (_L29, 0, NotSerialized) // GPIO25 (Suspend) - Pogo 0 Bridge A
+ {
+ Notify (\_SB.PCI0.PG0A, 0x02)
+ }
+ }
+
+ Method (_PTS, 1, NotSerialized)
+ {
+ Or (Arg0, 0xF0, Local0)
+ Store (Local0, DBG1)
+ }
+/*
+ Method (_WAK, 1, NotSerialized)
+ {
+ Or (Arg0, 0xE0, Local0)
+ Store (Local0, DBG1)
+ }
+*/
+ Name (PICF, 0x00) //Flag Variable for PIC vs. I/O APIC Mode
+ Method (_PIC, 1, NotSerialized) //PIC Flag and Interface Method
+ {
+ Store (Arg0, PICF)
+ }
+
+ OperationRegion (DEBG, SystemIO, 0x80, 0x01)
+ Field (DEBG, ByteAcc, Lock, Preserve)
+ {
+ DBG1, 8
+ }
+
+ OperationRegion (EXTM, SystemMemory, 0x000FF83C, 0x04)
+ Field (EXTM, WordAcc, Lock, Preserve)
+ {
+ AMEM, 32
+ }
+
+ OperationRegion (VGAM, SystemMemory, 0x000C0002, 0x01)
+ Field (VGAM, ByteAcc, Lock, Preserve)
+ {
+ VGA1, 8
+ }
+
+ OperationRegion (GRAM, SystemMemory, 0x0400, 0x0100)
+ Field (GRAM, ByteAcc, Lock, Preserve)
+ {
+ Offset (0x10),
+ FLG0, 8
+ }
+
+ OperationRegion (GSTS, SystemIO, 0xC028, 0x02)
+ Field (GSTS, ByteAcc, NoLock, Preserve)
+ {
+ , 4,
+ IRQR, 1
+ }
+
+ OperationRegion (Z007, SystemIO, 0x21, 0x01)
+ Field (Z007, ByteAcc, NoLock, Preserve)
+ {
+ Z008, 8
+ }
+
+ OperationRegion (Z009, SystemIO, 0xA1, 0x01)
+ Field (Z009, ByteAcc, NoLock, Preserve)
+ {
+ Z00A, 8
+ }
+
+ Include ("amdk8_util.asl")
+
+}
+
--- /dev/null
+ Include ("amd8111.asl") //real SB at first
+ Include ("amd8131.asl")
--- /dev/null
+/*
+ * Copyright 2005 AMD
+ */
+DefinitionBlock ("SSDT2.aml", "SSDT", 1, "AMD-K8", "AMDACPI", 100925440)
+{
+ Scope (_SB)
+ {
+ External (DADD, MethodObj)
+ External (GHCE, MethodObj)
+ External (GHCN, MethodObj)
+ External (GHCL, MethodObj)
+ External (GHCD, MethodObj)
+ External (GNUS, MethodObj)
+ External (GIOR, MethodObj)
+ External (GMEM, MethodObj)
+ External (GWBN, MethodObj)
+ External (GBUS, MethodObj)
+
+ External (PICF)
+
+ External (\_SB.PCI0.LNKA, DeviceObj)
+ External (\_SB.PCI0.LNKB, DeviceObj)
+ External (\_SB.PCI0.LNKC, DeviceObj)
+ External (\_SB.PCI0.LNKD, DeviceObj)
+
+ Device (PCIX)
+ {
+
+ // BUS ? Second HT Chain
+ Name (HCIN, 0xcc) // HC2 0x01
+
+ Name (_UID, 0xdd) // HC 0x03
+
+ Name (_HID, "PNP0A03")
+
+ Method (_ADR, 0, NotSerialized) //Fake bus should be 0
+ {
+ Return (DADD(GHCN(HCIN), 0x00000000))
+ }
+
+ Method (_BBN, 0, NotSerialized)
+ {
+ Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
+ }
+
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (\_SB.GHCE(HCIN))
+ }
+
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (BUF0, ResourceTemplate () { })
+ Store( GHCN(HCIN), Local4)
+ Store( GHCL(HCIN), Local5)
+
+ Concatenate (\_SB.GIOR (Local4, Local5), BUF0, Local1)
+ Concatenate (\_SB.GMEM (Local4, Local5), Local1, Local2)
+ Concatenate (\_SB.GWBN (Local4, Local5), Local2, Local3)
+ Return (Local3)
+ }
+
+ Include ("pci2_hc.asl")
+ }
+ }
+
+}
+
--- /dev/null
+ Include ("amd8132_2.asl")
--- /dev/null
+/*
+ * Copyright 2005 AMD
+ */
+DefinitionBlock ("SSDT3.aml", "SSDT", 1, "AMD-K8", "AMDACPI", 100925440)
+{
+ Scope (_SB)
+ {
+ External (DADD, MethodObj)
+ External (GHCE, MethodObj)
+ External (GHCN, MethodObj)
+ External (GHCL, MethodObj)
+ External (GHCD, MethodObj)
+ External (GNUS, MethodObj)
+ External (GIOR, MethodObj)
+ External (GMEM, MethodObj)
+ External (GWBN, MethodObj)
+ External (GBUS, MethodObj)
+
+ External (PICF)
+
+ External (\_SB.PCI0.LNKA, DeviceObj)
+ External (\_SB.PCI0.LNKB, DeviceObj)
+ External (\_SB.PCI0.LNKC, DeviceObj)
+ External (\_SB.PCI0.LNKD, DeviceObj)
+
+ Device (PCIX)
+ {
+
+ // BUS ? Second HT Chain
+ Name (HCIN, 0xcc) // HC2 0x01
+
+ Name (_UID, 0xdd) // HC 0x03
+
+ Name (_HID, "PNP0A03")
+
+ Method (_ADR, 0, NotSerialized) //Fake bus should be 0
+ {
+ Return (DADD(GHCN(HCIN), 0x00000000))
+ }
+
+ Method (_BBN, 0, NotSerialized)
+ {
+ Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
+ }
+
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (\_SB.GHCE(HCIN))
+ }
+
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (BUF0, ResourceTemplate () { })
+ Store( GHCN(HCIN), Local4)
+ Store( GHCL(HCIN), Local5)
+
+ Concatenate (\_SB.GIOR (Local4, Local5), BUF0, Local1)
+ Concatenate (\_SB.GMEM (Local4, Local5), Local1, Local2)
+ Concatenate (\_SB.GWBN (Local4, Local5), Local2, Local3)
+ Return (Local3)
+ }
+
+ Include ("pci3_hc.asl")
+ }
+ }
+
+}
+
--- /dev/null
+ Include ("amd8151.asl")
--- /dev/null
+/*
+ * Copyright 2005 AMD
+ */
+DefinitionBlock ("SSDT4.aml", "SSDT", 1, "AMD-K8", "AMDACPI", 100925440)
+{
+ Scope (_SB)
+ {
+ External (DADD, MethodObj)
+ External (GHCE, MethodObj)
+ External (GHCN, MethodObj)
+ External (GHCL, MethodObj)
+ External (GHCD, MethodObj)
+ External (GNUS, MethodObj)
+ External (GIOR, MethodObj)
+ External (GMEM, MethodObj)
+ External (GWBN, MethodObj)
+ External (GBUS, MethodObj)
+
+ External (PICF)
+
+ External (\_SB.PCI0.LNKA, DeviceObj)
+ External (\_SB.PCI0.LNKB, DeviceObj)
+ External (\_SB.PCI0.LNKC, DeviceObj)
+ External (\_SB.PCI0.LNKD, DeviceObj)
+
+ Device (PCIX)
+ {
+
+ // BUS ? Second HT Chain
+ Name (HCIN, 0xcc) // HC2 0x01
+
+ Name (_UID, 0xdd) // HC 0x03
+
+ Name (_HID, "PNP0A03")
+
+ Method (_ADR, 0, NotSerialized) //Fake bus should be 0
+ {
+ Return (DADD(GHCN(HCIN), 0x00000000))
+ }
+
+ Method (_BBN, 0, NotSerialized)
+ {
+ Return (GBUS (GHCN(HCIN), GHCL(HCIN)))
+ }
+
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (\_SB.GHCE(HCIN))
+ }
+
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (BUF0, ResourceTemplate () { })
+ Store( GHCN(HCIN), Local4)
+ Store( GHCL(HCIN), Local5)
+
+ Concatenate (\_SB.GIOR (Local4, Local5), BUF0, Local1)
+ Concatenate (\_SB.GMEM (Local4, Local5), Local1, Local2)
+ Concatenate (\_SB.GWBN (Local4, Local5), Local2, Local3)
+ Return (Local3)
+ }
+
+ Include ("pci4_hc.asl")
+ }
+ }
+
+}
+
--- /dev/null
+ Include ("amd8131_2.asl")
--- /dev/null
+// Include ("w83627hf.asl")
--- /dev/null
+/*
+ * ACPI - create the Fixed ACPI Description Tables (FADT)
+ * (C) Copyright 2005 Stefan Reinauer <stepan@openbios.org>
+ */
+
+#include <string.h>
+#include <console/console.h>
+#include <arch/acpi.h>
+
+extern unsigned pm_base; /* pm_base should be set in sb acpi */
+
+void acpi_create_fadt(acpi_fadt_t *fadt,acpi_facs_t *facs,void *dsdt){
+
+ acpi_header_t *header=&(fadt->header);
+
+ printk_debug("pm_base: 0x%04x\n", pm_base);
+
+ /* Prepare the header */
+ memset((void *)fadt,0,sizeof(acpi_fadt_t));
+ memcpy(header->signature,"FACP",4);
+ header->length = 244;
+ header->revision = 1;
+ memcpy(header->oem_id,OEM_ID,6);
+ memcpy(header->oem_table_id,"LXBACPI ",8);
+ memcpy(header->asl_compiler_id,ASLC,4);
+ header->asl_compiler_revision=0;
+
+ fadt->firmware_ctrl=(u32)facs;
+ fadt->dsdt= (u32)dsdt;
+ fadt->res1=0x0;
+ // 3=Workstation,4=Enterprise Server, 7=Performance Server
+ fadt->preferred_pm_profile=0x03;
+ fadt->sci_int=9;
+ // disable system management mode by setting to 0:
+ fadt->smi_cmd = 0;//pm_base+0x2f;
+ fadt->acpi_enable = 0xf0;
+ fadt->acpi_disable = 0xf1;
+ fadt->s4bios_req = 0x0;
+ fadt->pstate_cnt = 0xe2;
+
+ fadt->pm1a_evt_blk = pm_base;
+ fadt->pm1b_evt_blk = 0x0000;
+ fadt->pm1a_cnt_blk = pm_base+0x04;
+ fadt->pm1b_cnt_blk = 0x0000;
+ fadt->pm2_cnt_blk = 0x0000;
+ fadt->pm_tmr_blk = pm_base+0x08;
+ fadt->gpe0_blk = pm_base+0x20;
+ fadt->gpe1_blk = pm_base+0xb0;
+
+ fadt->pm1_evt_len = 4;
+ fadt->pm1_cnt_len = 2;
+ fadt->pm2_cnt_len = 0;
+ fadt->pm_tmr_len = 4;
+ fadt->gpe0_blk_len = 4;
+ fadt->gpe1_blk_len = 8;
+ fadt->gpe1_base = 16;
+
+ fadt->cst_cnt = 0xe3;
+ fadt->p_lvl2_lat = 101;
+ fadt->p_lvl3_lat = 1001;
+ fadt->flush_size = 0;
+ fadt->flush_stride = 0;
+ fadt->duty_offset = 1;
+ fadt->duty_width = 3;
+ fadt->day_alrm = 0; // 0x7d these have to be
+ fadt->mon_alrm = 0; // 0x7e added to cmos.layout
+ fadt->century = 0; // 0x7f to make rtc alrm work
+ fadt->iapc_boot_arch = 0x3; // See table 5-11
+ fadt->flags = 0x25;
+
+ fadt->res2 = 0;
+
+ fadt->reset_reg.space_id = 1;
+ fadt->reset_reg.bit_width = 8;
+ fadt->reset_reg.bit_offset = 0;
+ fadt->reset_reg.resv = 0;
+ fadt->reset_reg.addrl = 0xcf9;
+ fadt->reset_reg.addrh = 0x0;
+
+ fadt->reset_value = 6;
+ fadt->x_firmware_ctl_l = (u32)facs;
+ fadt->x_firmware_ctl_h = 0;
+ fadt->x_dsdt_l = (u32)dsdt;
+ fadt->x_dsdt_h = 0;
+
+ fadt->x_pm1a_evt_blk.space_id = 1;
+ fadt->x_pm1a_evt_blk.bit_width = 32;
+ fadt->x_pm1a_evt_blk.bit_offset = 0;
+ fadt->x_pm1a_evt_blk.resv = 0;
+ fadt->x_pm1a_evt_blk.addrl = pm_base;
+ fadt->x_pm1a_evt_blk.addrh = 0x0;
+
+ fadt->x_pm1b_evt_blk.space_id = 1;
+ fadt->x_pm1b_evt_blk.bit_width = 4;
+ fadt->x_pm1b_evt_blk.bit_offset = 0;
+ fadt->x_pm1b_evt_blk.resv = 0;
+ fadt->x_pm1b_evt_blk.addrl = 0x0;
+ fadt->x_pm1b_evt_blk.addrh = 0x0;
+
+
+ fadt->x_pm1a_cnt_blk.space_id = 1;
+ fadt->x_pm1a_cnt_blk.bit_width = 16;
+ fadt->x_pm1a_cnt_blk.bit_offset = 0;
+ fadt->x_pm1a_cnt_blk.resv = 0;
+ fadt->x_pm1a_cnt_blk.addrl = pm_base+4;
+ fadt->x_pm1a_cnt_blk.addrh = 0x0;
+
+ fadt->x_pm1b_cnt_blk.space_id = 1;
+ fadt->x_pm1b_cnt_blk.bit_width = 2;
+ fadt->x_pm1b_cnt_blk.bit_offset = 0;
+ fadt->x_pm1b_cnt_blk.resv = 0;
+ fadt->x_pm1b_cnt_blk.addrl = 0x0;
+ fadt->x_pm1b_cnt_blk.addrh = 0x0;
+
+
+ fadt->x_pm2_cnt_blk.space_id = 1;
+ fadt->x_pm2_cnt_blk.bit_width = 0;
+ fadt->x_pm2_cnt_blk.bit_offset = 0;
+ fadt->x_pm2_cnt_blk.resv = 0;
+ fadt->x_pm2_cnt_blk.addrl = 0x0;
+ fadt->x_pm2_cnt_blk.addrh = 0x0;
+
+
+ fadt->x_pm_tmr_blk.space_id = 1;
+ fadt->x_pm_tmr_blk.bit_width = 32;
+ fadt->x_pm_tmr_blk.bit_offset = 0;
+ fadt->x_pm_tmr_blk.resv = 0;
+ fadt->x_pm_tmr_blk.addrl = pm_base+0x08;
+ fadt->x_pm_tmr_blk.addrh = 0x0;
+
+
+ fadt->x_gpe0_blk.space_id = 1;
+ fadt->x_gpe0_blk.bit_width = 32;
+ fadt->x_gpe0_blk.bit_offset = 0;
+ fadt->x_gpe0_blk.resv = 0;
+ fadt->x_gpe0_blk.addrl = pm_base+0x20;
+ fadt->x_gpe0_blk.addrh = 0x0;
+
+
+ fadt->x_gpe1_blk.space_id = 1;
+ fadt->x_gpe1_blk.bit_width = 64;
+ fadt->x_gpe1_blk.bit_offset = 16;
+ fadt->x_gpe1_blk.resv = 0;
+ fadt->x_gpe1_blk.addrl = pm_base+0xb0;
+ fadt->x_gpe1_blk.addrh = 0x0;
+
+ header->checksum = acpi_checksum((void *)fadt, sizeof(acpi_fadt_t));
+
+}
--- /dev/null
+#include <console/console.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <string.h>
+#include <stdint.h>
+#if CONFIG_LOGICAL_CPUS==1
+#include <cpu/amd/dualcore.h>
+#endif
+
+#include <cpu/amd/amdk8_sysconf.h>
+
+#include "mb_sysconf.h"
+
+// Global variables for MB layouts and these will be shared by irqtable mptable and acpi_tables
+struct mb_sysconf_t mb_sysconf;
+
+static unsigned pci1234x[] =
+{ //Here you only need to set value in pci1234 for HT-IO that could be installed or not
+ //You may need to preset pci1234 for HTIO board, please refer to src/northbridge/amd/amdk8/get_sblk_pci1234.c for detail
+ 0x0000ff0, // SB chain m
+ 0x0000000, // HTX
+ 0x0000100, // co processor on socket 1
+// 0x0000ff0,
+// 0x0000ff0,
+// 0x0000ff0,
+// 0x0000ff0,
+// 0x0000ff0
+};
+static unsigned hcdnx[] =
+{ //HT Chain device num, actually it is unit id base of every ht device in chain, assume every chain only have 4 ht device at most
+ 0x20202020,
+ 0x20202020,
+ 0x20202020,
+// 0x20202020,
+// 0x20202020,
+// 0x20202020,
+// 0x20202020,
+// 0x20202020,
+};
+
+extern void get_sblk_pci1234(void);
+
+static unsigned get_bus_conf_done = 0;
+
+static unsigned get_hcid(unsigned i)
+{
+ unsigned id = 0;
+
+ unsigned busn = (sysconf.pci1234[i] >> 16) & 0xff;
+
+ unsigned devn = sysconf.hcdn[i] & 0xff;
+
+ device_t dev;
+
+ dev = dev_find_slot(busn, PCI_DEVFN(devn,0));
+
+ switch (dev->device) {
+ case 0x7458: //8132
+ id = 1;
+ break;
+ case 0x7454: //8151
+ id = 2;
+ break;
+ case 0x7450: //8131
+ id = 3;
+ break;
+ }
+
+ // we may need more way to find out hcid: subsystem id? GPIO read ?
+
+ // we need use id for 1. bus num, 2. mptable, 3. acpi table
+
+ return id;
+}
+
+void get_bus_conf(void)
+{
+
+ unsigned apicid_base;
+
+ device_t dev;
+ int i, j;
+ struct mb_sysconf_t *m;
+
+ if(get_bus_conf_done == 1) return; //do it only once
+
+ get_bus_conf_done = 1;
+
+ sysconf.mb = &mb_sysconf;
+
+ m = sysconf.mb;
+
+ sysconf.hc_possible_num = sizeof(pci1234x)/sizeof(pci1234x[0]);
+ for(i=0;i<sysconf.hc_possible_num; i++) {
+ sysconf.pci1234[i] = pci1234x[i];
+ sysconf.hcdn[i] = hcdnx[i];
+ }
+
+ get_sblk_pci1234();
+
+ sysconf.sbdn = (sysconf.hcdn[0] >> 8) & 0xff;
+ m->sbdn3 = sysconf.hcdn[0] & 0xff;
+
+ m->bus_8132_0 = (sysconf.pci1234[0] >> 16) & 0xff;
+ m->bus_8111_0 = m->bus_8132_0;
+
+ /* 8111 */
+ dev = dev_find_slot(m->bus_8111_0, PCI_DEVFN(sysconf.sbdn,0));
+ if (dev) {
+ m->bus_8111_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
+#if HT_CHAIN_END_UNITID_BASE >= HT_CHAIN_UNITID_BASE
+ m->bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
+ m->bus_isa++;
+// printk_debug("bus_isa=%d\n",bus_isa);
+#endif
+ }
+ else {
+ printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_8111_0, sysconf.sbdn);
+ }
+
+ /* 8132-1 */
+ dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3,0));
+ if (dev) {
+ m->bus_8132_1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
+ }
+ else {
+ printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_8132_0, m->sbdn3);
+ }
+
+ /* 8132-2 */
+ dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3+1,0));
+ if (dev) {
+ m->bus_8132_2 = pci_read_config8(dev, PCI_SECONDARY_BUS);
+#if HT_CHAIN_END_UNITID_BASE < HT_CHAIN_UNITID_BASE
+ m->bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
+ m->bus_isa++;
+// printk_debug("bus_isa=%d\n",bus_isa);
+#endif
+ }
+ else {
+ printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_8132_0, m->sbdn3+1);
+ }
+
+ /* HT chain 1 */
+ j=0;
+ for(i=1; i< sysconf.hc_possible_num; i++) {
+ if(!(sysconf.pci1234[i] & 0x1) ) continue;
+
+ // check hcid type here
+ sysconf.hcid[i] = get_hcid(i);
+
+ switch(sysconf.hcid[i]) {
+
+ case 1: //8132
+ case 3: //8131
+
+ m->bus_8132a[j][0] = (sysconf.pci1234[i] >> 16) & 0xff;
+
+ m->sbdn3a[j] = sysconf.hcdn[i] & 0xff;
+
+ /* 8132-1 */
+ dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j],0));
+ if (dev) {
+ m->bus_8132a[j][1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
+ }
+ else {
+ printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_8132a[j][0], m->sbdn3a[j]);
+ }
+
+ /* 8132-2 */
+ dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1,0));
+ if (dev) {
+ m->bus_8132a[j][2] = pci_read_config8(dev, PCI_SECONDARY_BUS);
+ m->bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
+ m->bus_isa++;
+ // printk_debug("bus_isa=%d\n",bus_isa);
+ }
+ else {
+ printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_8132a[j][0], m->sbdn3a[j]+1);
+ }
+
+ break;
+
+ case 2: //8151
+
+ m->bus_8151[j][0] = (sysconf.pci1234[i] >> 16) & 0xff;
+ m->sbdn5[j] = sysconf.hcdn[i] & 0xff;
+ /* 8151 */
+ dev = dev_find_slot(m->bus_8151[j][0], PCI_DEVFN(m->sbdn5[j]+1, 0));
+
+ if (dev) {
+ m->bus_8151[j][1] = pci_read_config8(dev, PCI_SECONDARY_BUS);
+ // printk_debug("bus_8151_1=%d\n",bus_8151[j][1]);
+ m->bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
+ m->bus_isa++;
+ }
+ else {
+ printk_debug("ERROR - could not find PCI %02x:%02x.0, using defaults\n", m->bus_8151[j][0], m->sbdn5[j]+1);
+ }
+
+ break;
+ }
+
+ j++;
+ }
+
+
+/*I/O APICs: APIC ID Version State Address*/
+#if CONFIG_LOGICAL_CPUS==1
+ apicid_base = get_apicid_base(3);
+#else
+ apicid_base = CONFIG_MAX_PHYSICAL_CPUS;
+#endif
+ m->apicid_8111 = apicid_base+0;
+ m->apicid_8132_1 = apicid_base+1;
+ m->apicid_8132_2 = apicid_base+2;
+ for(i=0;i<j;i++) {
+ m->apicid_8132a[i][0] = apicid_base + 3 + i*2;
+ m->apicid_8132a[i][1] = apicid_base + 3 + i*2 + 1;
+ }
+
+}
--- /dev/null
+/* This file was generated by getpir.c, do not modify!
+ (but if you do, please run checkpir on it to verify)
+ Contains the IRQ Routing Table dumped directly from your memory , wich BIOS sets up
+
+ Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM
+*/
+#include <console/console.h>
+#include <device/pci.h>
+#include <string.h>
+#include <stdint.h>
+#include <arch/pirq_routing.h>
+#include <cpu/amd/amdk8_sysconf.h>
+
+#include "mb_sysconf.h"
+
+static void write_pirq_info(struct irq_info *pirq_info, uint8_t bus, uint8_t devfn, uint8_t link0, uint16_t bitmap0,
+ uint8_t link1, uint16_t bitmap1, uint8_t link2, uint16_t bitmap2,uint8_t link3, uint16_t bitmap3,
+ uint8_t slot, uint8_t rfu)
+{
+ pirq_info->bus = bus;
+ pirq_info->devfn = devfn;
+
+ pirq_info->irq[0].link = link0;
+ pirq_info->irq[0].bitmap = bitmap0;
+ pirq_info->irq[1].link = link1;
+ pirq_info->irq[1].bitmap = bitmap1;
+ pirq_info->irq[2].link = link2;
+ pirq_info->irq[2].bitmap = bitmap2;
+ pirq_info->irq[3].link = link3;
+ pirq_info->irq[3].bitmap = bitmap3;
+
+ pirq_info->slot = slot;
+ pirq_info->rfu = rfu;
+}
+
+
+extern void get_bus_conf(void);
+
+unsigned long write_pirq_routing_table(unsigned long addr)
+{
+
+ struct irq_routing_table *pirq;
+ struct irq_info *pirq_info;
+ unsigned slot_num;
+ uint8_t *v;
+
+ uint8_t sum=0;
+ int i;
+
+ struct mb_sysconf_t *m;
+
+ get_bus_conf(); // it will find out all bus num and apic that share with mptable.c and mptable.c and acpi_tables.c
+
+ m = sysconf.mb;
+
+ /* Align the table to be 16 byte aligned. */
+ addr += 15;
+ addr &= ~15;
+
+ /* This table must be betweeen 0xf0000 & 0x100000 */
+ printk_info("Writing IRQ routing tables to 0x%x...", addr);
+
+ pirq = (void *)(addr);
+ v = (uint8_t *)(addr);
+
+ pirq->signature = PIRQ_SIGNATURE;
+ pirq->version = PIRQ_VERSION;
+
+ pirq->rtr_bus = m->bus_8111_0;
+ pirq->rtr_devfn = ((sysconf.sbdn+1)<<3)|0;
+
+ pirq->exclusive_irqs = 0;
+
+ pirq->rtr_vendor = 0x1022;
+ pirq->rtr_device = 0x746b;
+
+ pirq->miniport_data = 0;
+
+ memset(pirq->rfu, 0, sizeof(pirq->rfu));
+
+ pirq_info = (void *) ( &pirq->checksum + 1);
+ slot_num = 0;
+
+ {
+ device_t dev;
+ dev = dev_find_slot(m->bus_8111_0, PCI_DEVFN(sysconf.sbdn+1,3));
+ if (dev) {
+ /* initialize PCI interupts - these assignments depend
+ on the PCB routing of PINTA-D
+
+ PINTA = IRQ3
+ PINTB = IRQ5
+ PINTC = IRQ10
+ PINTD = IRQ11
+ */
+ pci_write_config16(dev, 0x56, 0xba53);
+ }
+ }
+
+//pci bridge
+ printk_debug("setting Onboard AMD Southbridge \n");
+ static const unsigned char slotIrqs_1_4[4] = { 3, 5, 10, 11 };
+ pci_assign_irqs(m->bus_8111_0, sysconf.sbdn+1, slotIrqs_1_4);
+ write_pirq_info(pirq_info, m->bus_8111_0, ((sysconf.sbdn+1)<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
+ pirq_info++; slot_num++;
+
+ printk_debug("setting Onboard AMD USB \n");
+ static const unsigned char slotIrqs_8111_1_0[4] = { 0, 0, 0, 11};
+ pci_assign_irqs(m->bus_8111_1, 0, slotIrqs_8111_1_0);
+ write_pirq_info(pirq_info, m->bus_8111_1,0, 0, 0, 0, 0, 0, 0, 0x4, 0xdef8, 0, 0);
+ pirq_info++; slot_num++;
+
+//pcix bridge
+// write_pirq_info(pirq_info, m->bus_8132_0, (sbdn3<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
+// pirq_info++; slot_num++;
+
+ int j = 0;
+
+ for(i=1; i< sysconf.hc_possible_num; i++) {
+ if(!(sysconf.pci1234[i] & 0x1) ) continue;
+ unsigned busn = (sysconf.pci1234[i] >> 16) & 0xff;
+ unsigned devn = sysconf.hcdn[i] & 0xff;
+
+ write_pirq_info(pirq_info, busn, (devn<<3)|0, 0x1, 0xdef8, 0x2, 0xdef8, 0x3, 0xdef8, 0x4, 0xdef8, 0, 0);
+ pirq_info++; slot_num++;
+ j++;
+
+ }
+
+ pirq->size = 32 + 16 * slot_num;
+
+ for (i = 0; i < pirq->size; i++)
+ sum += v[i];
+
+ sum = pirq->checksum - sum;
+
+ if (sum != pirq->checksum) {
+ pirq->checksum = sum;
+ }
+
+ printk_info("done.\n");
+
+ return (unsigned long) pirq_info;
+
+}
--- /dev/null
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include "chip.h"
+
+#if CONFIG_CHIP_NAME == 1
+struct chip_operations mainboard_Iwill_dk8_htx_ops = {
+ CHIP_NAME("Iwill DK8-HTX mainboard")
+};
+#endif
--- /dev/null
+#ifndef MB_SYSCONF_H
+
+#define MB_SYSCONF_H
+
+struct mb_sysconf_t {
+ unsigned char bus_isa;
+ unsigned char bus_8132_0;
+ unsigned char bus_8132_1;
+ unsigned char bus_8132_2;
+ unsigned char bus_8111_0;
+ unsigned char bus_8111_1;
+
+ unsigned char bus_8132a[7][3];
+
+ unsigned char bus_8151[7][2];
+
+ unsigned apicid_8111;
+ unsigned apicid_8132_1;
+ unsigned apicid_8132_2;
+ unsigned apicid_8132a[7][2];
+
+ unsigned sbdn3;
+ unsigned sbdn3a[7];
+ unsigned sbdn5[7];
+
+};
+
+#endif
+
--- /dev/null
+#include <console/console.h>
+#include <arch/smp/mpspec.h>
+#include <device/pci.h>
+#include <string.h>
+#include <stdint.h>
+#if CONFIG_LOGICAL_CPUS==1
+#include <cpu/amd/dualcore.h>
+#endif
+
+#include <cpu/amd/amdk8_sysconf.h>
+#include "mb_sysconf.h"
+
+extern void get_bus_conf(void);
+
+void *smp_write_config_table(void *v)
+{
+ static const char sig[4] = "PCMP";
+ static const char oem[8] = "IWILL ";
+ static const char productid[12] = "DK8-HTX ";
+ struct mp_config_table *mc;
+
+ unsigned char bus_num;
+ int i, j;
+ struct mb_sysconf_t *m;
+
+ mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
+ memset(mc, 0, sizeof(*mc));
+
+ memcpy(mc->mpc_signature, sig, sizeof(sig));
+ mc->mpc_length = sizeof(*mc); /* initially just the header */
+ mc->mpc_spec = 0x04;
+ mc->mpc_checksum = 0; /* not yet computed */
+ memcpy(mc->mpc_oem, oem, sizeof(oem));
+ memcpy(mc->mpc_productid, productid, sizeof(productid));
+ mc->mpc_oemptr = 0;
+ mc->mpc_oemsize = 0;
+ mc->mpc_entry_count = 0; /* No entries yet... */
+ mc->mpc_lapic = LAPIC_ADDR;
+ mc->mpe_length = 0;
+ mc->mpe_checksum = 0;
+ mc->reserved = 0;
+
+ smp_write_processors(mc);
+
+ get_bus_conf();
+
+ m = sysconf.mb;
+
+/*Bus: Bus ID Type*/
+ /* define bus and isa numbers */
+ for(bus_num = 0; bus_num < m->bus_isa; bus_num++) {
+ smp_write_bus(mc, bus_num, "PCI ");
+ }
+ smp_write_bus(mc, m->bus_isa, "ISA ");
+
+/*I/O APICs: APIC ID Version State Address*/
+ smp_write_ioapic(mc, m->apicid_8111, 0x11, 0xfec00000); //8111
+ {
+ device_t dev;
+ struct resource *res;
+ dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3, 1));
+ if (dev) {
+ res = find_resource(dev, PCI_BASE_ADDRESS_0);
+ if (res) {
+ smp_write_ioapic(mc, m->apicid_8132_1, 0x11, res->base);
+ }
+ }
+ dev = dev_find_slot(m->bus_8132_0, PCI_DEVFN(m->sbdn3+1, 1));
+ if (dev) {
+ res = find_resource(dev, PCI_BASE_ADDRESS_0);
+ if (res) {
+ smp_write_ioapic(mc, m->apicid_8132_2, 0x11, res->base);
+ }
+ }
+
+ j = 0;
+
+ for(i=1; i< sysconf.hc_possible_num; i++) {
+ if(!(sysconf.pci1234[i] & 0x1) ) continue;
+
+ switch(sysconf.hcid[i]) {
+ case 1: // 8132
+ case 3: // 8131
+ dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j], 1));
+ if (dev) {
+ res = find_resource(dev, PCI_BASE_ADDRESS_0);
+ if (res) {
+ smp_write_ioapic(mc, m->apicid_8132a[j][0], 0x11, res->base);
+ }
+ }
+ dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1, 1));
+ if (dev) {
+ res = find_resource(dev, PCI_BASE_ADDRESS_0);
+ if (res) {
+ smp_write_ioapic(mc, m->apicid_8132a[j][1], 0x11, res->base);
+ }
+ }
+ break;
+ }
+ j++;
+ }
+
+ }
+
+/*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN# */
+ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, m->apicid_8111, 0x0);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x1, m->apicid_8111, 0x1);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, m->apicid_8111, 0x2);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x3, m->apicid_8111, 0x3);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x4, m->apicid_8111, 0x4);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x5, m->apicid_8111, 0x5);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x6, m->apicid_8111, 0x6);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x7, m->apicid_8111, 0x7);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x8, m->apicid_8111, 0x8);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x9, m->apicid_8111, 0x9);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0xc, m->apicid_8111, 0xc);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0xd, m->apicid_8111, 0xd);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0xe, m->apicid_8111, 0xe);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0xf, m->apicid_8111, 0xf);
+//??? What
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_0, ((sysconf.sbdn+1)<<2)|3, m->apicid_8111, 0x13);
+
+// Onboard AMD USB
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (0<<2)|3, m->apicid_8111, 0x13);
+
+// Onboard VGA
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (6<<2)|0, m->apicid_8111, 0x12);
+
+//Slot 5 PCI 32
+ for(i=0;i<4;i++) {
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (5<<2)|i, m->apicid_8111, 0x10 + (1+i)%4); //16
+ }
+
+//Slot 6 PCI 32
+ for(i=0;i<4;i++) {
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8111_1, (4<<2)|i, m->apicid_8111, 0x10 + (0+i)%4); //16
+ }
+//Slot 1: HTX
+
+//Slot 2 PCI-X 133/100/66
+ for(i=0;i<4;i++) {
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_2, (2<<2)|i, m->apicid_8132_2, (2+i)%4); //30
+ }
+
+//Slot 3 PCI-X 133/100/66
+ for(i=0;i<4;i++) {
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (1<<2)|i, m->apicid_8132_1, (1+i)%4); //25
+ }
+
+//Slot 4 PCI-X 133/100/66
+ for(i=0;i<4;i++) {
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (2<<2)|i, m->apicid_8132_1, (2+i)%4); //26
+ }
+
+//Onboard NICS
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (3<<2)|0, m->apicid_8132_1, 3); //27
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (4<<2)|0, m->apicid_8132_1, 0); //24
+
+//Onboard SATA
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132_1, (5<<2)|0, m->apicid_8132_1, 1); //25
+
+ j = 0;
+
+ for(i=1; i< sysconf.hc_possible_num; i++) {
+ if(!(sysconf.pci1234[i] & 0x1) ) continue;
+ int ii;
+ device_t dev;
+ struct resource *res;
+ switch(sysconf.hcid[i]) {
+ case 1:
+ case 3:
+ dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j], 1));
+ if (dev) {
+ res = find_resource(dev, PCI_BASE_ADDRESS_0);
+ if (res) {
+ //Slot 1 PCI-X 133/100/66
+ for(ii=0;ii<4;ii++) {
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][1], (0<<2)|ii, m->apicid_8132a[j][0], (0+ii)%4); //
+ }
+ }
+ }
+
+ dev = dev_find_slot(m->bus_8132a[j][0], PCI_DEVFN(m->sbdn3a[j]+1, 1));
+ if (dev) {
+ res = find_resource(dev, PCI_BASE_ADDRESS_0);
+ if (res) {
+ //Slot 2 PCI-X 133/100/66
+ for(ii=0;ii<4;ii++) {
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8132a[j][2], (0<<2)|ii, m->apicid_8132a[j][1], (0+ii)%4); //25
+ }
+ }
+ }
+
+ break;
+ case 2:
+
+ // Slot AGP
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, m->bus_8151[j][1], 0x0, m->apicid_8111, 0x11);
+ break;
+ }
+
+ j++;
+ }
+
+
+
+/*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
+ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x0);
+ smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE|MP_IRQ_POLARITY_HIGH, m->bus_isa, 0x0, MP_APIC_ALL, 0x1);
+ /* There is no extension information... */
+
+ /* Compute the checksums */
+ mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
+ mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
+ printk_debug("Wrote the mp table end at: %p - %p\n",
+ mc, smp_next_mpe_entry(mc));
+ return smp_next_mpe_entry(mc);
+}
+
+unsigned long write_smp_table(unsigned long addr)
+{
+ void *v;
+ v = smp_write_floating_table(addr);
+ return (unsigned long)smp_write_config_table(v);
+}
--- /dev/null
+/*
+ *
+ */
+
+static void setup_mb_resource_map(void)
+{
+ static const unsigned int register_values[] = {
+ /* Careful set limit registers before base registers which contain the enables */
+ /* DRAM Limit i Registers
+ * F1:0x44 i = 0
+ * F1:0x4C i = 1
+ * F1:0x54 i = 2
+ * F1:0x5C i = 3
+ * F1:0x64 i = 4
+ * F1:0x6C i = 5
+ * F1:0x74 i = 6
+ * F1:0x7C i = 7
+ * [ 2: 0] Destination Node ID
+ * 000 = Node 0
+ * 001 = Node 1
+ * 010 = Node 2
+ * 011 = Node 3
+ * 100 = Node 4
+ * 101 = Node 5
+ * 110 = Node 6
+ * 111 = Node 7
+ * [ 7: 3] Reserved
+ * [10: 8] Interleave select
+ * specifies the values of A[14:12] to use with interleave enable.
+ * [15:11] Reserved
+ * [31:16] DRAM Limit Address i Bits 39-24
+ * This field defines the upper address bits of a 40 bit address
+ * that define the end of the DRAM region.
+ */
+ PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001,
+ PCI_ADDR(0, 0x18, 1, 0x54), 0x0000f8f8, 0x00000002,
+ PCI_ADDR(0, 0x18, 1, 0x5C), 0x0000f8f8, 0x00000003,
+ PCI_ADDR(0, 0x18, 1, 0x64), 0x0000f8f8, 0x00000004,
+ PCI_ADDR(0, 0x18, 1, 0x6C), 0x0000f8f8, 0x00000005,
+ PCI_ADDR(0, 0x18, 1, 0x74), 0x0000f8f8, 0x00000006,
+ PCI_ADDR(0, 0x18, 1, 0x7C), 0x0000f8f8, 0x00000007,
+ /* DRAM Base i Registers
+ * F1:0x40 i = 0
+ * F1:0x48 i = 1
+ * F1:0x50 i = 2
+ * F1:0x58 i = 3
+ * F1:0x60 i = 4
+ * F1:0x68 i = 5
+ * F1:0x70 i = 6
+ * F1:0x78 i = 7
+ * [ 0: 0] Read Enable
+ * 0 = Reads Disabled
+ * 1 = Reads Enabled
+ * [ 1: 1] Write Enable
+ * 0 = Writes Disabled
+ * 1 = Writes Enabled
+ * [ 7: 2] Reserved
+ * [10: 8] Interleave Enable
+ * 000 = No interleave
+ * 001 = Interleave on A[12] (2 nodes)
+ * 010 = reserved
+ * 011 = Interleave on A[12] and A[14] (4 nodes)
+ * 100 = reserved
+ * 101 = reserved
+ * 110 = reserved
+ * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
+ * [15:11] Reserved
+ * [13:16] DRAM Base Address i Bits 39-24
+ * This field defines the upper address bits of a 40-bit address
+ * that define the start of the DRAM region.
+ */
+ PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00000000,
+
+ /* Memory-Mapped I/O Limit i Registers
+ * F1:0x84 i = 0
+ * F1:0x8C i = 1
+ * F1:0x94 i = 2
+ * F1:0x9C i = 3
+ * F1:0xA4 i = 4
+ * F1:0xAC i = 5
+ * F1:0xB4 i = 6
+ * F1:0xBC i = 7
+ * [ 2: 0] Destination Node ID
+ * 000 = Node 0
+ * 001 = Node 1
+ * 010 = Node 2
+ * 011 = Node 3
+ * 100 = Node 4
+ * 101 = Node 5
+ * 110 = Node 6
+ * 111 = Node 7
+ * [ 3: 3] Reserved
+ * [ 5: 4] Destination Link ID
+ * 00 = Link 0
+ * 01 = Link 1
+ * 10 = Link 2
+ * 11 = Reserved
+ * [ 6: 6] Reserved
+ * [ 7: 7] Non-Posted
+ * 0 = CPU writes may be posted
+ * 1 = CPU writes must be non-posted
+ * [31: 8] Memory-Mapped I/O Limit Address i (39-16)
+ * This field defines the upp adddress bits of a 40-bit address that
+ * defines the end of a memory-mapped I/O region n
+ */
+ PCI_ADDR(0, 0x18, 1, 0x84), 0x00000048, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0x8C), 0x00000048, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0x94), 0x00000048, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0x9C), 0x00000048, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0xA4), 0x00000048, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0xB4), 0x00000048, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00ffff20,
+
+ /* Memory-Mapped I/O Base i Registers
+ * F1:0x80 i = 0
+ * F1:0x88 i = 1
+ * F1:0x90 i = 2
+ * F1:0x98 i = 3
+ * F1:0xA0 i = 4
+ * F1:0xA8 i = 5
+ * F1:0xB0 i = 6
+ * F1:0xB8 i = 7
+ * [ 0: 0] Read Enable
+ * 0 = Reads disabled
+ * 1 = Reads Enabled
+ * [ 1: 1] Write Enable
+ * 0 = Writes disabled
+ * 1 = Writes Enabled
+ * [ 2: 2] Cpu Disable
+ * 0 = Cpu can use this I/O range
+ * 1 = Cpu requests do not use this I/O range
+ * [ 3: 3] Lock
+ * 0 = base/limit registers i are read/write
+ * 1 = base/limit registers i are read-only
+ * [ 7: 4] Reserved
+ * [31: 8] Memory-Mapped I/O Base Address i (39-16)
+ * This field defines the upper address bits of a 40bit address
+ * that defines the start of memory-mapped I/O region i
+ */
+ PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0x88), 0x000000f0, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0x90), 0x000000f0, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0x98), 0x000000f0, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0xA0), 0x000000f0, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00fc0003,
+
+ /* PCI I/O Limit i Registers
+ * F1:0xC4 i = 0
+ * F1:0xCC i = 1
+ * F1:0xD4 i = 2
+ * F1:0xDC i = 3
+ * [ 2: 0] Destination Node ID
+ * 000 = Node 0
+ * 001 = Node 1
+ * 010 = Node 2
+ * 011 = Node 3
+ * 100 = Node 4
+ * 101 = Node 5
+ * 110 = Node 6
+ * 111 = Node 7
+ * [ 3: 3] Reserved
+ * [ 5: 4] Destination Link ID
+ * 00 = Link 0
+ * 01 = Link 1
+ * 10 = Link 2
+ * 11 = reserved
+ * [11: 6] Reserved
+ * [24:12] PCI I/O Limit Address i
+ * This field defines the end of PCI I/O region n
+ * [31:25] Reserved
+ */
+ PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x01fff020,
+ PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000,
+
+ /* PCI I/O Base i Registers
+ * F1:0xC0 i = 0
+ * F1:0xC8 i = 1
+ * F1:0xD0 i = 2
+ * F1:0xD8 i = 3
+ * [ 0: 0] Read Enable
+ * 0 = Reads Disabled
+ * 1 = Reads Enabled
+ * [ 1: 1] Write Enable
+ * 0 = Writes Disabled
+ * 1 = Writes Enabled
+ * [ 3: 2] Reserved
+ * [ 4: 4] VGA Enable
+ * 0 = VGA matches Disabled
+ * 1 = matches all address < 64K and where A[9:0] is in the
+ * range 3B0-3BB or 3C0-3DF independen of the base & limit registers
+ * [ 5: 5] ISA Enable
+ * 0 = ISA matches Disabled
+ * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block
+ * from matching agains this base/limit pair
+ * [11: 6] Reserved
+ * [24:12] PCI I/O Base i
+ * This field defines the start of PCI I/O region n
+ * [31:25] Reserved
+ */
+ PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x00000003,
+ PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000,
+
+ /* Config Base and Limit i Registers
+ * F1:0xE0 i = 0
+ * F1:0xE4 i = 1
+ * F1:0xE8 i = 2
+ * F1:0xEC i = 3
+ * [ 0: 0] Read Enable
+ * 0 = Reads Disabled
+ * 1 = Reads Enabled
+ * [ 1: 1] Write Enable
+ * 0 = Writes Disabled
+ * 1 = Writes Enabled
+ * [ 2: 2] Device Number Compare Enable
+ * 0 = The ranges are based on bus number
+ * 1 = The ranges are ranges of devices on bus 0
+ * [ 3: 3] Reserved
+ * [ 6: 4] Destination Node
+ * 000 = Node 0
+ * 001 = Node 1
+ * 010 = Node 2
+ * 011 = Node 3
+ * 100 = Node 4
+ * 101 = Node 5
+ * 110 = Node 6
+ * 111 = Node 7
+ * [ 7: 7] Reserved
+ * [ 9: 8] Destination Link
+ * 00 = Link 0
+ * 01 = Link 1
+ * 10 = Link 2
+ * 11 - Reserved
+ * [15:10] Reserved
+ * [23:16] Bus Number Base i
+ * This field defines the lowest bus number in configuration region i
+ * [31:24] Bus Number Limit i
+ * This field defines the highest bus number in configuration regin i
+ */
+ PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0x06000203, // AMD 8111 on link0 of CPU 0
+ PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
+ PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
+ };
+
+ int max;
+ max = sizeof(register_values)/sizeof(register_values[0]);
+ setup_resource_map(register_values, max);
+}
+
+++ /dev/null
-
-target dk8_htx
-mainboard Iwill/dk8_htx
-
-# serengeti_leopard
-romimage "normal"
-# 48K for SCSI FW
-# option ROM_SIZE = 475136
-# 48K for SCSI FW and 48K for ATI ROM
-# option ROM_SIZE = 425984
-# 64K for Etherboot
-# option ROM_SIZE = 458752
- option USE_FAILOVER_IMAGE=0
- option USE_FALLBACK_IMAGE=0
-# option ROM_IMAGE_SIZE=0x13800
-# option ROM_IMAGE_SIZE=0x17800
-# option ROM_IMAGE_SIZE=0x15800
- option ROM_IMAGE_SIZE=0x20000
- option XIP_ROM_SIZE=0x20000
- option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
-# payload ../../../payloads/tg3--ide_disk.zelf
-# payload ../../../payloads/filo.elf
-# payload ../../../payloads/filo_mem.elf
-# payload ../../../payloads/filo.zelf
-# payload ../../../payloads/tg3--filo_hda2.zelf
-# payload ../../../payloads/tg3.zelf
-# payload ../../../payloads/tg3_vga.zelf
-# payload ../../../../payloads/tg3--filo_hda2_vga.zelf
- payload ../../../../payloads/tg3--filo_hda2_vga_5_4.zelf
-# payload ../../../../payloads/e1000--filo.zelf
-# payload ../../../payloads/tg3_com2.zelf
-# payload ../../../payloads/tg3--e1000--filo.zelf
-# payload ../../../payloads/tg3--eepro100--e1000--filo_hda2.zelf
-# payload ../../../payloads/tg3--eepro100--e1000--filo_hda2_5.3.zelf
-# payload ../../../payloads/tg3--eepro100--e1000--filo_hda2_com2.zelf
-end
-
-romimage "fallback"
- option USE_FAILOVER_IMAGE=0
- option USE_FALLBACK_IMAGE=1
-# option ROM_IMAGE_SIZE=0x13800
-# option ROM_IMAGE_SIZE=0x17800
-# option ROM_IMAGE_SIZE=0x15800
- option ROM_IMAGE_SIZE=0x20000
- option XIP_ROM_SIZE=0x20000
- option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
-# payload ../../../payloads/tg3--ide_disk.zelf
-# payload ../../../payloads/filo.elf
-# payload ../../../payloads/filo_mem.elf
-# payload ../../../payloads/filo.zelf
-# payload ../../../payloads/tg3--filo_hda2.zelf
-# payload ../../../payloads/tg3.zelf
-# payload ../../../payloads/tg3_vga.zelf
-# payload ../../../../payloads/memtest
-# payload ../../../../payloads/tg3--filo_hda2_vga.zelf
- payload ../../../../payloads/tg3--filo_hda2_vga_5_4.zelf
-# payload ../../../payloads/tg3_com2.zelf
-# payload ../../../../payloads/e1000--filo.zelf
-# payload ../../../payloads/tg3--e1000--filo.zelf
-# payload ../../../payloads/tg3--eepro100--e1000--filo_hda2.zelf
-# payload ../../../payloads/tg3--eepro100--e1000--filo_hda2_5.3.zelf
-# payload ../../../payloads/tg3--eepro100--e1000--filo_hda2_com2.zelf
-end
-
-romimage "failover"
- option USE_FAILOVER_IMAGE=1
- option USE_FALLBACK_IMAGE=0
- option ROM_IMAGE_SIZE=FAILOVER_SIZE
- option XIP_ROM_SIZE=FAILOVER_SIZE
- option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover"
-end
-
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" "failover"
-#buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"
+++ /dev/null
-# Sample config file for
-# the Iwill DK8S2
-# This will make a target directory of ./dk8s2
-
-target dk8s2
-
-mainboard Iwill/DK8S2
-
-option HAVE_HARD_RESET=1
-
-option HAVE_OPTION_TABLE=1
-option HAVE_MP_TABLE=1
-option ROM_SIZE=1024*1024
-
-option HAVE_FALLBACK_BOOT=1
-
-#option CONFIG_LSI_SCSI_FW_FIXUP=1
-
-
-#
-###
-### Build code to export a programmable irq routing table
-###
-option HAVE_PIRQ_TABLE=1
-option IRQ_SLOT_COUNT=12
-#
-###
-### Build code for SMP support
-### Only worry about 2 micro processors
-###
-option CONFIG_SMP=1
-option CONFIG_MAX_CPUS=2
-#option CONFIG_LOGICAL_CPUS=2
-option CONFIG_MAX_PHYSICAL_CPUS=2
-#
-###
-### Build code to setup a generic IOAPIC
-###
-option CONFIG_IOAPIC=1
-#
-###
-### MEMORY_HOLE instructs earlymtrr.inc to
-### enable caching from 0-640KB and to disable
-### caching from 640KB-1MB using fixed MTRRs
-###
-### Enabling this option breaks SMP because secondary
-### CPU identification depends on only variable MTRRs
-### being enabled.
-###
-#option MEMORY_HOLE=0
-#
-###
-### Clean up the motherboard id strings
-###
-option MAINBOARD_PART_NUMBER="DK8S2"
-option MAINBOARD_VENDOR="Iwill"
-#
-###
-### Compute the location and size of where this firmware image
-### (linuxBIOS plus bootloader) will live in the boot rom chip.
-###
-#option FALLBACK_SIZE=524288
-#option FALLBACK_SIZE=98304
-option FALLBACK_SIZE=131072
-
-## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
-option ROM_IMAGE_SIZE=65536
-
-
-###
-### Compute where this copy of linuxBIOS will start in the boot rom
-###
-#
-###
-
-## We do use compressed image
-#option CONFIG_COMPRESS=1
-
-option CONFIG_CONSOLE_SERIAL8250=1
-option TTYS0_BAUD=115200
-
-##
-### Select the linuxBIOS loglevel
-##
-## EMERG 1 system is unusable
-## ALERT 2 action must be taken immediately
-## CRIT 3 critical conditions
-## ERR 4 error conditions
-## WARNING 5 warning conditions
-## NOTICE 6 normal but significant condition
-## INFO 7 informational
-## DEBUG 8 debug-level messages
-## SPEW 9 Way too many details
-
-## Request this level of debugging output
-option DEFAULT_CONSOLE_LOGLEVEL=7
-## At a maximum only compile in this level of debugging
-option MAXIMUM_CONSOLE_LOGLEVEL=7
-
-#option DEBUG=1
-
-#
-
-## LinuxBIOS C code runs at this location in RAM
-option _RAMBASE=0x004000
-
-##
-## Use a 32K stack
-##
-option STACK_SIZE=0x8000
-
-##
-## Use a 56K heap
-##
-option HEAP_SIZE=0xe000
-
-#
-###
-### Compute the start location and size size of
-### The linuxBIOS bootloader.
-###
-option CONFIG_ROM_STREAM = 1
-
-#
-#
-romimage "normal"
-# 48K for SCSI FW
-# option ROM_SIZE = 512*1024-48*1024
-# 48K for SCSI FW and 48K for ATI ROM
-# option ROM_SIZE = 512*1024-48*1024-48*1024
- option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
- option USE_FALLBACK_IMAGE=0
- option ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE)
- option ROM_SECTION_OFFSET= 0
-
- option PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE)
- option CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
- option _ROMBASE = (CONFIG_ROM_STREAM_START + PAYLOAD_SIZE)
-
-# option XIP_ROM_SIZE = FALLBACK_SIZE
- option XIP_ROM_SIZE = 65536
-
- option XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE)
-
- payload /usr/src/filo-0.4.1_btext/filo.elf
-# payload /usr/src/filo-0.4.2/filo.elf
-end
-
-romimage "fallback"
- option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
- option USE_FALLBACK_IMAGE=1
- option ROM_SECTION_SIZE = FALLBACK_SIZE
- option ROM_SECTION_OFFSET= (ROM_SIZE - FALLBACK_SIZE)
-
- option PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE)
- option CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
- option _ROMBASE = (CONFIG_ROM_STREAM_START + PAYLOAD_SIZE)
-
-# option XIP_ROM_SIZE = FALLBACK_SIZE
- option XIP_ROM_SIZE = 65536
- option XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE)
-
- payload ../../../payloads/filo.elf
-# payload /usr/src/filo-0.4.2/filo.elf
-end
-
-buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"
--- /dev/null
+
+target dk8_htx
+mainboard Iwill/dk8_htx
+
+# serengeti_leopard
+romimage "normal"
+# 48K for SCSI FW
+# option ROM_SIZE = 475136
+# 48K for SCSI FW and 48K for ATI ROM
+# option ROM_SIZE = 425984
+# 64K for Etherboot
+# option ROM_SIZE = 458752
+ option USE_FAILOVER_IMAGE=0
+ option USE_FALLBACK_IMAGE=0
+# option ROM_IMAGE_SIZE=0x13800
+# option ROM_IMAGE_SIZE=0x17800
+# option ROM_IMAGE_SIZE=0x15800
+ option ROM_IMAGE_SIZE=0x20000
+ option XIP_ROM_SIZE=0x20000
+ option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
+# payload ../../../payloads/tg3--ide_disk.zelf
+# payload ../../../payloads/filo.elf
+# payload ../../../payloads/filo_mem.elf
+# payload ../../../payloads/filo.zelf
+# payload ../../../payloads/tg3--filo_hda2.zelf
+# payload ../../../payloads/tg3.zelf
+# payload ../../../payloads/tg3_vga.zelf
+# payload ../../../../payloads/tg3--filo_hda2_vga.zelf
+ payload ../../../../payloads/tg3--filo_hda2_vga_5_4.zelf
+# payload ../../../../payloads/e1000--filo.zelf
+# payload ../../../payloads/tg3_com2.zelf
+# payload ../../../payloads/tg3--e1000--filo.zelf
+# payload ../../../payloads/tg3--eepro100--e1000--filo_hda2.zelf
+# payload ../../../payloads/tg3--eepro100--e1000--filo_hda2_5.3.zelf
+# payload ../../../payloads/tg3--eepro100--e1000--filo_hda2_com2.zelf
+end
+
+romimage "fallback"
+ option USE_FAILOVER_IMAGE=0
+ option USE_FALLBACK_IMAGE=1
+# option ROM_IMAGE_SIZE=0x13800
+# option ROM_IMAGE_SIZE=0x17800
+# option ROM_IMAGE_SIZE=0x15800
+ option ROM_IMAGE_SIZE=0x20000
+ option XIP_ROM_SIZE=0x20000
+ option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
+# payload ../../../payloads/tg3--ide_disk.zelf
+# payload ../../../payloads/filo.elf
+# payload ../../../payloads/filo_mem.elf
+# payload ../../../payloads/filo.zelf
+# payload ../../../payloads/tg3--filo_hda2.zelf
+# payload ../../../payloads/tg3.zelf
+# payload ../../../payloads/tg3_vga.zelf
+# payload ../../../../payloads/memtest
+# payload ../../../../payloads/tg3--filo_hda2_vga.zelf
+ payload ../../../../payloads/tg3--filo_hda2_vga_5_4.zelf
+# payload ../../../payloads/tg3_com2.zelf
+# payload ../../../../payloads/e1000--filo.zelf
+# payload ../../../payloads/tg3--e1000--filo.zelf
+# payload ../../../payloads/tg3--eepro100--e1000--filo_hda2.zelf
+# payload ../../../payloads/tg3--eepro100--e1000--filo_hda2_5.3.zelf
+# payload ../../../payloads/tg3--eepro100--e1000--filo_hda2_com2.zelf
+end
+
+romimage "failover"
+ option USE_FAILOVER_IMAGE=1
+ option USE_FALLBACK_IMAGE=0
+ option ROM_IMAGE_SIZE=FAILOVER_SIZE
+ option XIP_ROM_SIZE=FAILOVER_SIZE
+ option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Failover"
+end
+
+buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback" "failover"
+#buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"
--- /dev/null
+# Sample config file for
+# the Iwill DK8S2
+# This will make a target directory of ./dk8s2
+
+target dk8s2
+
+mainboard Iwill/DK8S2
+
+option HAVE_HARD_RESET=1
+
+option HAVE_OPTION_TABLE=1
+option HAVE_MP_TABLE=1
+option ROM_SIZE=1024*1024
+
+option HAVE_FALLBACK_BOOT=1
+
+#option CONFIG_LSI_SCSI_FW_FIXUP=1
+
+
+#
+###
+### Build code to export a programmable irq routing table
+###
+option HAVE_PIRQ_TABLE=1
+option IRQ_SLOT_COUNT=12
+#
+###
+### Build code for SMP support
+### Only worry about 2 micro processors
+###
+option CONFIG_SMP=1
+option CONFIG_MAX_CPUS=2
+#option CONFIG_LOGICAL_CPUS=2
+option CONFIG_MAX_PHYSICAL_CPUS=2
+#
+###
+### Build code to setup a generic IOAPIC
+###
+option CONFIG_IOAPIC=1
+#
+###
+### MEMORY_HOLE instructs earlymtrr.inc to
+### enable caching from 0-640KB and to disable
+### caching from 640KB-1MB using fixed MTRRs
+###
+### Enabling this option breaks SMP because secondary
+### CPU identification depends on only variable MTRRs
+### being enabled.
+###
+#option MEMORY_HOLE=0
+#
+###
+### Clean up the motherboard id strings
+###
+option MAINBOARD_PART_NUMBER="DK8S2"
+option MAINBOARD_VENDOR="Iwill"
+#
+###
+### Compute the location and size of where this firmware image
+### (linuxBIOS plus bootloader) will live in the boot rom chip.
+###
+#option FALLBACK_SIZE=524288
+#option FALLBACK_SIZE=98304
+option FALLBACK_SIZE=131072
+
+## ROM_IMAGE_SIZE is the amount of space to allow linuxBIOS to occupy.
+option ROM_IMAGE_SIZE=65536
+
+
+###
+### Compute where this copy of linuxBIOS will start in the boot rom
+###
+#
+###
+
+## We do use compressed image
+#option CONFIG_COMPRESS=1
+
+option CONFIG_CONSOLE_SERIAL8250=1
+option TTYS0_BAUD=115200
+
+##
+### Select the linuxBIOS loglevel
+##
+## EMERG 1 system is unusable
+## ALERT 2 action must be taken immediately
+## CRIT 3 critical conditions
+## ERR 4 error conditions
+## WARNING 5 warning conditions
+## NOTICE 6 normal but significant condition
+## INFO 7 informational
+## DEBUG 8 debug-level messages
+## SPEW 9 Way too many details
+
+## Request this level of debugging output
+option DEFAULT_CONSOLE_LOGLEVEL=7
+## At a maximum only compile in this level of debugging
+option MAXIMUM_CONSOLE_LOGLEVEL=7
+
+#option DEBUG=1
+
+#
+
+## LinuxBIOS C code runs at this location in RAM
+option _RAMBASE=0x004000
+
+##
+## Use a 32K stack
+##
+option STACK_SIZE=0x8000
+
+##
+## Use a 56K heap
+##
+option HEAP_SIZE=0xe000
+
+#
+###
+### Compute the start location and size size of
+### The linuxBIOS bootloader.
+###
+option CONFIG_ROM_STREAM = 1
+
+#
+#
+romimage "normal"
+# 48K for SCSI FW
+# option ROM_SIZE = 512*1024-48*1024
+# 48K for SCSI FW and 48K for ATI ROM
+# option ROM_SIZE = 512*1024-48*1024-48*1024
+ option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Normal"
+ option USE_FALLBACK_IMAGE=0
+ option ROM_SECTION_SIZE = (ROM_SIZE - FALLBACK_SIZE)
+ option ROM_SECTION_OFFSET= 0
+
+ option PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE)
+ option CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
+ option _ROMBASE = (CONFIG_ROM_STREAM_START + PAYLOAD_SIZE)
+
+# option XIP_ROM_SIZE = FALLBACK_SIZE
+ option XIP_ROM_SIZE = 65536
+
+ option XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE)
+
+ payload /usr/src/filo-0.4.1_btext/filo.elf
+# payload /usr/src/filo-0.4.2/filo.elf
+end
+
+romimage "fallback"
+ option LINUXBIOS_EXTRA_VERSION="$(shell cat ../../VERSION)_Fallback"
+ option USE_FALLBACK_IMAGE=1
+ option ROM_SECTION_SIZE = FALLBACK_SIZE
+ option ROM_SECTION_OFFSET= (ROM_SIZE - FALLBACK_SIZE)
+
+ option PAYLOAD_SIZE = (ROM_SECTION_SIZE - ROM_IMAGE_SIZE)
+ option CONFIG_ROM_STREAM_START = (0xffffffff - ROM_SIZE + ROM_SECTION_OFFSET + 1)
+ option _ROMBASE = (CONFIG_ROM_STREAM_START + PAYLOAD_SIZE)
+
+# option XIP_ROM_SIZE = FALLBACK_SIZE
+ option XIP_ROM_SIZE = 65536
+ option XIP_ROM_BASE = (_ROMBASE + ROM_IMAGE_SIZE - XIP_ROM_SIZE)
+
+ payload ../../../payloads/filo.elf
+# payload /usr/src/filo-0.4.2/filo.elf
+end
+
+buildrom ./linuxbios.rom ROM_SIZE "normal" "fallback"
projects / coreboot.git / commitdiff