cosmetic comment changes.

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5572 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

diff --git a/src/include/cpu/x86/cache.h b/src/include/cpu/x86/cache.h
index ae61b55b3dbea6704293c5bf015c28aa09b79a55..65979fff772c5152c2dda88b166c1f2829701413 100644 (file)
--- a/src/include/cpu/x86/cache.h
+++ b/src/include/cpu/x86/cache.h
@@ -20,18 +20,17 @@
 #ifndef CPU_X86_CACHE
 #define CPU_X86_CACHE
 
-/* the memory clobber prevents the GCC from reordering the read/write order
-   of CR0 */
-
-#if defined(__GNUC__)
-
 /*
-Need this because ROMCC fails here with:
+ * Need two versions because ROMCC chokes on certain clobbers:
+ * cache.h:29.71: cache.h:60.24: earlymtrr.c:117.23: romstage.c:144.33: 
+ * 0x1559920 asm        Internal compiler error: lhs 1 regcm == 0
+ */
 
-cache.h:29.71: cache.h:60.24: earlymtrr.c:117.23: romstage.c:144.33: 
-0x1559920 asm        Internal compiler error: lhs 1 regcm == 0
-*/
+#if defined(__GNUC__)
 
+/* The memory clobber prevents the GCC from reordering the read/write order
+ * of CR0
+ */
 static inline unsigned long read_cr0(void)
 {
        unsigned long cr0;