--- /dev/null
+config chip.h
+object bga956.o
+dir /cpu/intel/model_1067x
--- /dev/null
+#include <device/device.h>
+#include "chip.h"
+
+
+struct chip_operations cpu_intel_bga956_ops = {
+ CHIP_NAME("BGA956 CPU")
+};
--- /dev/null
+extern struct chip_operations cpu_intel_bga956_ops;
+
+struct cpu_intel_bga956_config {
+};
--- /dev/null
+uses CONFIG_HAVE_MOVNTI
+default CONFIG_HAVE_MOVNTI=1
+
+dir /cpu/x86/tsc
+dir /cpu/x86/mtrr
+dir /cpu/x86/fpu
+dir /cpu/x86/mmx
+dir /cpu/x86/sse
+dir /cpu/x86/lapic
+dir /cpu/x86/cache
+dir /cpu/x86/smm
+dir /cpu/intel/microcode
+dir /cpu/intel/hyperthreading
+driver model_1067x_init.o
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2009 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <string.h>
+#include <cpu/cpu.h>
+#include <cpu/x86/mtrr.h>
+#include <cpu/x86/msr.h>
+#include <cpu/x86/lapic.h>
+#include <cpu/intel/microcode.h>
+#include <cpu/intel/hyperthreading.h>
+#include <cpu/x86/cache.h>
+#include <cpu/x86/mtrr.h>
+
+static const uint32_t microcode_updates[] = {
+ /* Dummy terminator */
+ 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0,
+ 0x0, 0x0, 0x0, 0x0,
+};
+
+static inline void strcpy(char *dst, char *src)
+{
+ while (*src) *dst++ = *src++;
+}
+
+static void init_timer(void)
+{
+ /* Set the apic timer to no interrupts and periodic mode */
+ lapic_write(LAPIC_LVTT, (1 << 17)|(1<< 16)|(0 << 12)|(0 << 0));
+
+ /* Set the divider to 1, no divider */
+ lapic_write(LAPIC_TDCR, LAPIC_TDR_DIV_1);
+
+ /* Set the initial counter to 0xffffffff */
+ lapic_write(LAPIC_TMICT, 0xffffffff);
+}
+
+static void fill_processor_name(char *processor_name)
+{
+ struct cpuid_result regs;
+ char temp_processor_name[49];
+ char *processor_name_start;
+ unsigned int *name_as_ints = (unsigned int *)temp_processor_name;
+ int i;
+
+ for (i=0; i<3; i++) {
+ regs = cpuid(0x80000002 + i);
+ name_as_ints[i*4 + 0] = regs.eax;
+ name_as_ints[i*4 + 1] = regs.ebx;
+ name_as_ints[i*4 + 2] = regs.ecx;
+ name_as_ints[i*4 + 3] = regs.edx;
+ }
+
+ temp_processor_name[48] = 0;
+
+ /* Skip leading spaces */
+ processor_name_start = temp_processor_name;
+ while (*processor_name_start == ' ')
+ processor_name_start++;
+
+ memset(processor_name, 0, 49);
+ strcpy(processor_name, processor_name_start);
+}
+
+#define IA32_FEATURE_CONTROL 0x003a
+
+#define CPUID_VMX (1 << 5)
+#define CPUID_SMX (1 << 6)
+static void enable_vmx(void)
+{
+ struct cpuid_result regs;
+ msr_t msr;
+
+ msr = rdmsr(IA32_FEATURE_CONTROL);
+
+ if (msr.lo & (1 << 0)) {
+ /* VMX locked. If we set it again we get an illegal
+ * instruction
+ */
+ return;
+ }
+
+ regs = cpuid(1);
+ if (regs.ecx & CPUID_VMX) {
+ msr.lo |= (1 << 2);
+ if (regs.ecx & CPUID_SMX)
+ msr.lo |= (1 << 1);
+ }
+
+ wrmsr(IA32_FEATURE_CONTROL, msr);
+
+ msr.lo |= (1 << 0); /* Set lock bit */
+
+ wrmsr(IA32_FEATURE_CONTROL, msr);
+}
+
+#define PMG_CST_CONFIG_CONTROL 0xe2
+#define PMG_IO_BASE_ADDR 0xe3
+#define PMG_IO_CAPTURE_ADDR 0xe4
+
+#define PMB0_BASE 0x580
+#define PMB1_BASE 0x800
+#define CST_RANGE 2
+static void configure_c_states(void)
+{
+ msr_t msr;
+
+ msr = rdmsr(PMG_CST_CONFIG_CONTROL);
+
+ msr.lo |= (1 << 15); // config lock until next reset
+ msr.lo |= (1 << 14); // Deeper Sleep
+ msr.lo |= (1 << 10); // Enable IO MWAIT redirection
+ msr.lo &= ~(1 << 9); // Issue a single stop grant cycle upon stpclk
+ msr.lo |= (1 << 3); // Dynamic L2
+
+ wrmsr(PMG_CST_CONFIG_CONTROL, msr);
+
+ /* Set Processor MWAIT IO BASE */
+ msr.hi = 0;
+ msr.lo = ((PMB0_BASE + 4) & 0xffff) | (((PMB1_BASE + 9) & 0xffff) << 16);
+ wrmsr(PMG_IO_BASE_ADDR, msr);
+
+ /* Set IO Capture Address */
+ msr.hi = 0;
+ msr.lo = ((PMB0_BASE + 4) & 0xffff) | (( CST_RANGE & 0xffff) << 16);
+ wrmsr(PMG_IO_CAPTURE_ADDR, msr);
+}
+
+#define IA32_MISC_ENABLE 0x1a0
+static void configure_misc(void)
+{
+ msr_t msr;
+
+ msr = rdmsr(IA32_MISC_ENABLE);
+ msr.lo |= (1 << 3); /* TM1 enable */
+ msr.lo |= (1 << 13); /* TM2 enable */
+ msr.lo |= (1 << 17); /* Bidirectional PROCHOT# */
+
+ msr.lo |= (1 << 10); /* FERR# multiplexing */
+
+ // TODO: Only if IA32_PLATFORM_ID[17] = 0 and IA32_PLATFORM_ID[50] = 1
+ msr.lo |= (1 << 16); /* Enhanced SpeedStep Enable */
+
+ /* Enable C2E */
+ msr.lo |= (1 << 26);
+
+ /* Enable C4E */
+ /* TODO This should only be done on mobile CPUs, see cpuid 5 */
+ msr.hi |= (1 << (32 - 32)); // C4E
+ msr.hi |= (1 << (33 - 32)); // Hard C4E
+
+ /* Enable EMTTM. */
+ /* NOTE: We leave the EMTTM_CR_TABLE0-5 at their default values */
+ msr.hi |= (1 << (36 - 32));
+
+ wrmsr(IA32_MISC_ENABLE, msr);
+
+ msr.lo |= (1 << 20); /* Lock Enhanced SpeedStep Enable */
+ wrmsr(IA32_MISC_ENABLE, msr);
+}
+
+#define PIC_SENS_CFG 0x1aa
+static void configure_pic_thermal_sensors(void)
+{
+ msr_t msr;
+
+ msr = rdmsr(PIC_SENS_CFG);
+
+ msr.lo |= (1 << 21); // inter-core lock TM1
+ msr.lo |= (1 << 4); // Enable bypass filter
+
+ wrmsr(PIC_SENS_CFG, msr);
+}
+
+#if CONFIG_USBDEBUG_DIRECT
+static unsigned ehci_debug_addr;
+#endif
+
+static void model_1067x_init(device_t cpu)
+{
+ char processor_name[49];
+
+ /* Turn on caching if we haven't already */
+ x86_enable_cache();
+
+ /* Update the microcode */
+ intel_update_microcode(microcode_updates);
+
+ /* Print processor name */
+ fill_processor_name(processor_name);
+ printk_info("CPU: %s.\n", processor_name);
+
+#if CONFIG_USBDEBUG_DIRECT
+ // Is this caution really needed?
+ if(!ehci_debug_addr)
+ ehci_debug_addr = get_ehci_debug();
+ set_ehci_debug(0);
+#endif
+
+ /* Setup MTRRs */
+ x86_setup_mtrrs(36);
+ x86_mtrr_check();
+
+#if CONFIG_USBDEBUG_DIRECT
+ set_ehci_debug(ehci_debug_addr);
+#endif
+
+ /* Enable the local cpu apics */
+ setup_lapic();
+
+ /* Initialize the APIC timer */
+ init_timer();
+
+ /* Enable virtualization */
+ enable_vmx();
+
+ /* Configure C States */
+ configure_c_states();
+
+ /* Configure Enhanced SpeedStep and Thermal Sensors */
+ configure_misc();
+
+ /* PIC thermal sensor control */
+ configure_pic_thermal_sensors();
+
+ /* Start up my cpu siblings */
+ intel_sibling_init(cpu);
+}
+
+static struct device_operations cpu_dev_ops = {
+ .init = model_1067x_init,
+};
+
+static struct cpu_device_id cpu_table[] = {
+ { X86_VENDOR_INTEL, 0x10676 }, /* Intel Core 2 Solo/Core Duo */
+ { 0, 0 },
+};
+
+static const struct cpu_driver driver __cpu_driver = {
+ .ops = &cpu_dev_ops,
+ .id_table = cpu_table,
+};
+
#define PCI_DEVICE_ID_INTEL_3100_MC 0x35b0
#define PCI_DEVICE_ID_INTEL_3100_PCIE_PA0 0x35b6
#define PCI_DEVICE_ID_INTEL_3100_PCIE_PA1 0x35b7
+#define PCI_DEVICE_ID_INTEL_3100_PCIE_PB0 0x2690
+#define PCI_DEVICE_ID_INTEL_3100_PCIE_PB1 0x2692
+#define PCI_DEVICE_ID_INTEL_3100_PCIE_PB2 0x2694
+#define PCI_DEVICE_ID_INTEL_3100_PCIE_PB3 0x2696
/* Intel EP80579 */
#define PCI_DEVICE_ID_INTEL_EP80579_LPC 0x5031
--- /dev/null
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2009 Thomas Jourdan <thomas.jourdan@gmail.com>
+##
+## This program is free software; you can redistribute it and/or
+## modify it under the terms of the GNU General Public License as
+## published by the Free Software Foundation; version 2 of
+## the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+## MA 02110-1301 USA
+##
+
+##
+## This mainboard requires DCACHE_AS_RAM enabled. It won't work without.
+##
+
+##
+## Only use the option table in a normal image
+##
+default CONFIG_USE_OPTION_TABLE = !CONFIG_USE_FALLBACK_IMAGE
+
+## CONFIG_XIP_ROM_SIZE must be a power of 2.
+default CONFIG_XIP_ROM_SIZE = 64 * 1024
+include /config/nofailovercalculation.lb
+
+##
+## Set all of the defaults for an x86 architecture
+##
+
+arch i386 end
+
+##
+## Build the objects we have code for in this directory.
+##
+
+driver mainboard.o
+if CONFIG_HAVE_MP_TABLE object mptable.o end
+if CONFIG_HAVE_PIRQ_TABLE object irq_tables.o end
+
+if CONFIG_HAVE_ACPI_TABLES
+ object fadt.o
+ object acpi_tables.o
+ makerule dsdt.c
+ depends "$(CONFIG_MAINBOARD)/dsdt.dsl"
+ action "iasl -p dsdt -tc $(CONFIG_MAINBOARD)/dsdt.dsl"
+ action "mv $(CURDIR)/dsdt.hex dsdt.c"
+ end
+ object ./dsdt.o
+end
+
+object reset.o
+
+if CONFIG_USE_INIT
+
+makerule ./auto.o
+ depends "$(CONFIG_MAINBOARD)/auto.c option_table.h"
+ action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) -I$(TOP)/src -I. -c $(CONFIG_MAINBOARD)/auto.c -o $@"
+end
+
+else
+
+makerule ./auto.inc
+ depends "$(CONFIG_MAINBOARD)/auto.c option_table.h"
+ action "$(CC) $(DISTRO_CFLAGS) $(CFLAGS) $(CPPFLAGS) $(DEBUG_CFLAGS) -I$(TOP)/src -I. -c -S $(CONFIG_MAINBOARD)/auto.c -o $@"
+ action "perl -e 's/\.rodata/.rom.data/g' -pi $@"
+ action "perl -e 's/\.text/.section .rom.text/g' -pi $@"
+end
+
+end
+
+##
+## Build our 16 bit and 32 bit coreboot entry code
+##
+mainboardinit cpu/x86/16bit/entry16.inc
+mainboardinit cpu/x86/32bit/entry32.inc
+ldscript /cpu/x86/16bit/entry16.lds
+if CONFIG_USE_INIT
+ ldscript /cpu/x86/32bit/entry32.lds
+ ldscript /cpu/x86/car/cache_as_ram.lds
+end
+
+##
+## Build our reset vector (This is where coreboot is entered)
+##
+if CONFIG_USE_FALLBACK_IMAGE
+ mainboardinit cpu/x86/16bit/reset16.inc
+ ldscript /cpu/x86/16bit/reset16.lds
+else
+ mainboardinit cpu/x86/32bit/reset32.inc
+ ldscript /cpu/x86/32bit/reset32.lds
+end
+
+
+##
+## Include an id string (For safe flashing)
+##
+mainboardinit arch/i386/lib/id.inc
+ldscript /arch/i386/lib/id.lds
+
+##
+## Setup Cache-As-Ram
+##
+mainboardinit cpu/intel/model_6fx/cache_as_ram.inc
+
+###
+### This is the early phase of coreboot startup
+### Things are delicate and we test to see if we should
+### failover to another image.
+###
+if CONFIG_USE_FALLBACK_IMAGE
+ ldscript /arch/i386/lib/failover.lds
+end
+
+###
+### O.k. We aren't just an intermediary anymore!
+###
+
+if CONFIG_USE_INIT
+initobject auto.o
+else
+mainboardinit ./auto.inc
+end
+
+##
+## Include the secondary Configuration files
+##
+dir /pc80
+config chip.h
+
+chip northbridge/intel/i3100
+ device pci_domain 0 on
+ device pci 00.0 on end # IMCH
+ device pci 00.1 on end # IMCH error status
+ device pci 01.0 on end # IMCH EDMA engine
+ device pci 02.0 on end # PCIe port A/A0
+ device pci 03.0 on end # PCIe port A1
+ chip southbridge/intel/i3100
+ # PIRQ line -> legacy IRQ mappings
+ register "pirq_a_d" = "0x8b808a8a"
+ register "pirq_e_h" = "0x85808080"
+
+ device pci 1c.0 on end # PCIe port B0
+ device pci 1c.1 off end # PCIe port B1
+ device pci 1c.2 off end # PCIe port B2
+ device pci 1c.3 off end # PCIe port B3
+ device pci 1d.0 on end # USB (UHCI) 1
+ device pci 1d.1 on end # USB (UHCI) 2
+ device pci 1d.7 on end # USB (EHCI)
+ device pci 1e.0 on end # PCI bridge
+ device pci 1f.0 on # LPC bridge
+ chip superio/intel/i3100
+ device pnp 4e.4 on # Com1
+ io 0x60 = 0x3f8
+ irq 0x70 = 4
+ end
+ device pnp 4e.5 on # Com2
+ io 0x60 = 0x2f8
+ irq 0x70 = 3
+ end
+ end
+ chip superio/smsc/smscsuperio
+ device pnp 2e.0 off # Floppy
+ io 0x60 = 0x3f0
+ irq 0x70 = 6
+ drq 0x74 = 2
+ end
+ device pnp 2e.2 off # Serial Port 4
+ io 0x60 = 0x2e8
+ irq 0x70 = 3
+ end
+ device pnp 2e.3 on # Parallel Port
+ io 0x60 = 0x378
+ irq 0x70 = 7
+ drq 0x74 = 2
+ end
+ device pnp 2e.4 off # Serial Port 3
+ io 0x60 = 0x3e8
+ irq 0x70 = 4
+ end
+ device pnp 2e.7 on # PS/2 Keyboard / Mouse
+ io 0x60 = 0x60
+ io 0x62 = 0x64
+ irq 0x70 = 1 # PS/2 keyboard interrupt
+ irq 0x72 = 12 # PS/2 mouse interrupt
+ end
+ device pnp 2e.a off # Runtime registers
+ io 0x60 = 0x600
+ end
+ end
+ end
+ device pci 1f.2 on end # SATA
+ device pci 1f.3 on end # SMBus
+ device pci 1f.4 on end # Performance counters
+ end
+ end
+ device apic_cluster 0 on
+ chip cpu/intel/bga956
+ device apic 0 on end
+ end
+ end
+end
+
--- /dev/null
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2007-2008 coresystems GmbH
+##
+## This program is free software; you can redistribute it and/or
+## modify it under the terms of the GNU General Public License as
+## published by the Free Software Foundation; version 2 of
+## the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+## MA 02110-1301 USA
+##
+
+# Tables
+uses CONFIG_HAVE_MP_TABLE
+uses CONFIG_HAVE_PIRQ_TABLE
+uses CONFIG_IRQ_SLOT_COUNT
+uses CONFIG_HAVE_OPTION_TABLE
+uses CONFIG_USE_OPTION_TABLE
+uses CONFIG_LB_CKS_RANGE_START
+uses CONFIG_LB_CKS_RANGE_END
+uses CONFIG_LB_CKS_LOC
+uses CONFIG_HAVE_ACPI_TABLES
+uses CONFIG_HAVE_MAINBOARD_RESOURCES
+# SMP
+uses CONFIG_SMP
+uses CONFIG_LOGICAL_CPUS
+uses CONFIG_AP_IN_SIPI_WAIT
+uses CONFIG_MAX_CPUS
+uses CONFIG_MAX_PHYSICAL_CPUS
+uses CONFIG_IOAPIC
+# Image Size
+uses CONFIG_USE_FALLBACK_IMAGE
+uses CONFIG_HAVE_FALLBACK_BOOT
+uses CONFIG_FALLBACK_SIZE
+uses CONFIG_ROM_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_IMAGE_SIZE
+uses CONFIG_ROM_SECTION_SIZE
+uses CONFIG_ROM_SECTION_OFFSET
+# Payload
+uses CONFIG_ROM_PAYLOAD
+uses CONFIG_ROM_PAYLOAD_START
+uses CONFIG_COMPRESSED_PAYLOAD_LZMA
+uses CONFIG_COMPRESSED_PAYLOAD_NRV2B
+uses CONFIG_PRECOMPRESSED_PAYLOAD
+uses CONFIG_PAYLOAD_SIZE
+# Build Internals
+uses CONFIG_RAMBASE
+uses CONFIG_ROMBASE
+uses CONFIG_STACK_SIZE
+uses CONFIG_HEAP_SIZE
+uses CONFIG_USE_DCACHE_RAM
+uses CONFIG_DCACHE_RAM_BASE
+uses CONFIG_DCACHE_RAM_SIZE
+uses CONFIG_USE_INIT
+uses CONFIG_USE_PRINTK_IN_CAR
+uses CONFIG_XIP_ROM_BASE
+uses CONFIG_XIP_ROM_SIZE
+uses CONFIG_HAVE_HARD_RESET
+uses CONFIG_HAVE_SMI_HANDLER
+uses CONFIG_PCIE_CONFIGSPACE_HOLE
+uses CONFIG_MMCONF_SUPPORT
+uses CONFIG_MMCONF_BASE_ADDRESS
+uses CONFIG_CBFS
+#
+uses CONFIG_MAINBOARD
+uses CONFIG_MAINBOARD_PART_NUMBER
+uses CONFIG_MAINBOARD_VENDOR
+uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID
+uses CONFIG_MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID
+# Timers
+uses CONFIG_UDELAY_TSC
+uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
+# Console
+uses CONFIG_CONSOLE_SERIAL8250
+uses CONFIG_TTYS0_BAUD
+uses CONFIG_TTYS0_BASE
+uses CONFIG_TTYS0_LCS
+uses CONFIG_DEFAULT_CONSOLE_LOGLEVEL
+uses CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
+uses CONFIG_CONSOLE_VGA
+uses CONFIG_VGA_ROM_RUN
+uses CONFIG_PCI_ROM_RUN
+uses CONFIG_DEBUG
+uses CONFIG_VGA
+uses CONFIG_PCI_OPTION_ROM_RUN_YABEL
+# Toolchain
+uses CC
+uses HOSTCC
+uses CONFIG_CROSS_COMPILE
+uses CONFIG_OBJCOPY
+# Tweaks
+uses CONFIG_GDB_STUB
+uses CONFIG_MAX_REBOOT_CNT
+uses CONFIG_USE_WATCHDOG_ON_BOOT
+uses COREBOOT_EXTRA_VERSION
+uses CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
+
+###
+### Build options
+###
+
+##
+##
+default CONFIG_MAX_REBOOT_CNT=3
+
+##
+## Use the watchdog to break out of a lockup condition
+##
+default CONFIG_USE_WATCHDOG_ON_BOOT=0
+
+##
+## ROM_SIZE is the size of boot ROM that this board will use.
+##
+default CONFIG_ROM_SIZE=1024*1024
+
+
+##
+## Build code for the fallback boot
+##
+default CONFIG_HAVE_FALLBACK_BOOT=1
+
+##
+## Delay timer options
+## Use timer2
+##
+default CONFIG_UDELAY_TSC=1
+default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1
+
+##
+## Build code to reset the motherboard from coreboot
+##
+default CONFIG_HAVE_HARD_RESET=1
+
+##
+## Build SMI handler
+##
+default CONFIG_HAVE_SMI_HANDLER=0
+
+##
+## Leave a hole for mmapped PCIe config space
+##
+default CONFIG_PCIE_CONFIGSPACE_HOLE=1
+default CONFIG_MMCONF_SUPPORT=1
+default CONFIG_MMCONF_BASE_ADDRESS=0xE0000000
+
+##
+## Build code to export a programmable irq routing table
+##
+default CONFIG_HAVE_PIRQ_TABLE=1
+default CONFIG_IRQ_SLOT_COUNT=18
+
+##
+## Build code to export an x86 MP table
+## Useful for specifying IRQ routing values
+##
+default CONFIG_HAVE_MP_TABLE=1
+
+##
+## Build code to provide ACPI support
+##
+default CONFIG_HAVE_ACPI_TABLES=1
+default CONFIG_HAVE_MAINBOARD_RESOURCES=1
+
+##
+## Build code to export a CMOS option table
+##
+default CONFIG_HAVE_OPTION_TABLE=1
+
+##
+## Move the default coreboot cmos range off of AMD RTC registers
+##
+default CONFIG_LB_CKS_RANGE_START=49
+default CONFIG_LB_CKS_RANGE_END=122
+default CONFIG_LB_CKS_LOC=123
+
+#VGA Console
+default CONFIG_CONSOLE_VGA=0
+# There are some network option roms that don't work with
+# coreboot's x86emu. Thus, we only execute the VGA option rom
+# for now:
+default CONFIG_VGA_ROM_RUN=0
+default CONFIG_PCI_ROM_RUN=0
+default CONFIG_DEBUG=0
+
+#default CONFIG_VGA=0
+#default CONFIG_PCI_OPTION_ROM_RUN_YABEL=0
+
+##
+## Build code for SMP support
+## Only worry about 2 micro processors
+##
+default CONFIG_SMP=1
+default CONFIG_MAX_CPUS=4
+default CONFIG_MAX_PHYSICAL_CPUS=2
+default CONFIG_LOGICAL_CPUS=1
+default CONFIG_AP_IN_SIPI_WAIT=1
+
+##
+## enable CACHE_AS_RAM specifics
+##
+default CONFIG_USE_DCACHE_RAM=1
+default CONFIG_DCACHE_RAM_SIZE=0x8000
+default CONFIG_DCACHE_RAM_BASE=( 0xfff00000 - CONFIG_DCACHE_RAM_SIZE - 1024*1024)
+default CONFIG_USE_PRINTK_IN_CAR=1
+
+##
+## Build code to setup a generic IOAPIC
+##
+default CONFIG_IOAPIC=1
+
+##
+## Clean up the motherboard id strings
+##
+default CONFIG_MAINBOARD_PART_NUMBER="EagleHeights"
+default CONFIG_MAINBOARD_VENDOR= "Intel"
+
+###
+### coreboot layout values
+###
+
+## ROM_IMAGE_SIZE is the amount of space to allow coreboot to occupy.
+default CONFIG_ROM_IMAGE_SIZE = 65536
+
+##
+## Use a small 8K stack
+##
+default CONFIG_STACK_SIZE=0x2000
+
+##
+## Use a small 32K heap
+##
+default CONFIG_HEAP_SIZE=0x8000
+
+
+###
+### Compute the location and size of where this firmware image
+### (coreboot plus bootloader) will live in the boot rom chip.
+###
+default CONFIG_FALLBACK_SIZE=CONFIG_ROM_IMAGE_SIZE
+
+##
+## coreboot C code runs at this location in RAM
+##
+default CONFIG_RAMBASE=0x00100000
+
+##
+## Load the payload from the ROM
+##
+default CONFIG_ROM_PAYLOAD=1
+default CONFIG_PRECOMPRESSED_PAYLOAD=1
+default CONFIG_COMPRESSED_PAYLOAD_LZMA=1
+#default CONFIG_COMPRESSED_PAYLOAD_NRV2B=0
+
+###
+### Defaults of options that you may want to override in the target config file
+###
+
+##
+## The default compiler
+##
+default CC="$(CROSS_COMPILE)gcc -m32"
+default HOSTCC="gcc"
+
+##
+## Disable the gdb stub by default
+##
+default CONFIG_GDB_STUB=0
+
+##
+## The Serial Console
+##
+
+# To Enable the Serial Console
+default CONFIG_CONSOLE_SERIAL8250=1
+
+## Select the serial console baud rate
+default CONFIG_TTYS0_BAUD=115200
+#default CONFIG_TTYS0_BAUD=57600
+#default CONFIG_TTYS0_BAUD=38400
+#default CONFIG_TTYS0_BAUD=19200
+#default CONFIG_TTYS0_BAUD=9600
+#default CONFIG_TTYS0_BAUD=4800
+#default CONFIG_TTYS0_BAUD=2400
+#default CONFIG_TTYS0_BAUD=1200
+
+# Select the serial console base port
+default CONFIG_TTYS0_BASE=0x3f8
+
+# Select the serial protocol
+# This defaults to 8 data bits, 1 stop bit, and no parity
+default CONFIG_TTYS0_LCS=0x3
+
+##
+### Select the coreboot loglevel
+##
+## EMERG 1 system is unusable
+## ALERT 2 action must be taken immediately
+## CRIT 3 critical conditions
+## ERR 4 error conditions
+## WARNING 5 warning conditions
+## NOTICE 6 normal but significant condition
+## INFO 7 informational
+## DEBUG 8 debug-level messages
+## SPEW 9 Way too many details
+
+## Request this level of debugging output
+default CONFIG_DEFAULT_CONSOLE_LOGLEVEL=7
+## At a maximum only compile in this level of debugging
+default CONFIG_MAXIMUM_CONSOLE_LOGLEVEL=9
+
+##
+## Select power on after power fail setting
+default CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"
+
+#
+# CBFS
+#
+default CONFIG_CBFS=1
+
+### End Options.lb
+end
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2008 coresystems GmbH
+ * Copyright (C) 2009 Thomas Jourdan <thomas.jourdan@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <string.h>
+#include <console/console.h>
+#include <arch/acpi.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include "ioapic.h"
+
+extern unsigned char AmlCode[];
+
+unsigned long acpi_fill_mcfg(unsigned long current)
+{
+ device_t dev;
+ u64 mmcfg;
+
+ dev = dev_find_device(0x8086, 0x35B0, 0); // 0:0x13.0
+ if (!dev)
+ return current;
+
+ // MMCFG not supported or not enabled.
+ mmcfg = ((u64) pci_read_config16(dev, 0xce)) << 16;
+ if (!mmcfg)
+ return current;
+
+ current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *) current,
+ mmcfg, 0x0, 0x0, 0xff);
+
+ return current;
+}
+
+void acpi_create_intel_hpet(acpi_hpet_t * hpet)
+{
+#define HPET_ADDR 0xfed00000ULL
+ acpi_header_t *header = &(hpet->header);
+ acpi_addr_t *addr = &(hpet->addr);
+
+ memset((void *) hpet, 0, sizeof(acpi_hpet_t));
+
+ /* fill out header fields */
+ memcpy(header->signature, HPET_NAME, 4);
+ memcpy(header->oem_id, OEM_ID, 6);
+ memcpy(header->oem_table_id, "IC ", 8);
+ memcpy(header->asl_compiler_id, ASLC, 4);
+
+ header->length = sizeof(acpi_hpet_t);
+ header->revision = 1;
+
+ /* fill out HPET address */
+ // XXX factory bios just puts an address here -- who's right?
+ addr->space_id = 0; /* Memory */
+ addr->bit_width = 64;
+ addr->bit_offset = 0;
+ addr->addrl = HPET_ADDR & 0xffffffff;
+ addr->addrh = HPET_ADDR >> 32;
+
+ hpet->id = 0x80861234;
+ hpet->number = 0x00;
+ hpet->min_tick = 0x0090;
+
+ header->checksum = acpi_checksum((void *) hpet, sizeof(acpi_hpet_t));
+}
+
+#define IO_APIC0 2
+#define IO_APIC1 3
+#define IO_APIC0_ADDR 0xfec00000UL
+#define IO_APIC1_ADDR 0xfec10000UL
+
+unsigned long acpi_fill_madt(unsigned long current)
+{
+ unsigned int irq_start = 0;
+ device_t dev = 0;
+ struct resource* res = NULL;
+ unsigned char bus_isa;
+
+ /* Local Apic */
+ current += acpi_create_madt_lapic((acpi_madt_lapic_t *) current, 1, 0);
+ // This one is for the second core... Will it hurt?
+ current += acpi_create_madt_lapic((acpi_madt_lapic_t *) current, 2, 1);
+
+ /* IOAPIC */
+ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, IO_APIC0, IO_APIC0_ADDR, irq_start);
+ irq_start += INTEL_IOAPIC_NUM_INTERRUPTS;
+ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current, IO_APIC1, IO_APIC1_ADDR, irq_start);
+ irq_start += INTEL_IOAPIC_NUM_INTERRUPTS;
+
+ dev = dev_find_slot(0, PCI_DEVFN(0x1e,0));
+
+ if (dev) {
+ bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
+ bus_isa++;
+ } else {
+ printk_debug("ERROR - could not find PCI 0:1e.0, using defaults\n");
+ bus_isa = 7;
+ }
+
+ /* Map ISA IRQ 0 to IRQ 2 */
+ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, bus_isa, 0, 2, 0);
+
+ /* IRQ9 differs from ISA standard - ours is active high, level-triggered */
+ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *) current, 0, 9, 9, 0x000d);
+
+ return current;
+}
+
+unsigned long acpi_fill_slit(unsigned long current)
+{
+ // Not implemented
+ return current;
+}
+
+unsigned long acpi_fill_srat(unsigned long current)
+{
+ /* No NUMA, no SRAT */
+ return current;
+}
+
+
+#define ALIGN_CURRENT current = ((current + 0x0f) & -0x10)
+unsigned long write_acpi_tables(unsigned long start)
+{
+ unsigned long current;
+ int i;
+ acpi_rsdp_t *rsdp;
+ acpi_rsdt_t *rsdt;
+ acpi_hpet_t *hpet;
+ acpi_madt_t *madt;
+ acpi_mcfg_t *mcfg;
+ acpi_fadt_t *fadt;
+ acpi_facs_t *facs;
+ acpi_header_t *dsdt;
+
+ current = start;
+
+ /* Align ACPI tables to 16byte */
+ ALIGN_CURRENT;
+
+ printk_info("ACPI: Writing ACPI tables at %lx.\n", current);
+
+ /* We need at least an RSDP and an RSDT Table */
+ rsdp = (acpi_rsdp_t *) current;
+ current += sizeof(acpi_rsdp_t);
+ ALIGN_CURRENT;
+ rsdt = (acpi_rsdt_t *) current;
+ current += sizeof(acpi_rsdt_t);
+ ALIGN_CURRENT;
+
+ /* clear all table memory */
+ memset((void *) start, 0, current - start);
+
+ acpi_write_rsdp(rsdp, rsdt);
+ acpi_write_rsdt(rsdt);
+
+ /*
+ * We explicitly add these tables later on:
+ */
+ printk_debug("ACPI: * HPET\n");
+
+ hpet = (acpi_hpet_t *) current;
+ current += sizeof(acpi_hpet_t);
+ ALIGN_CURRENT;
+ acpi_create_intel_hpet(hpet);
+ acpi_add_table(rsdt, hpet);
+
+ /* If we want to use HPET Timers Linux wants an MADT */
+ printk_debug("ACPI: * MADT\n");
+
+ madt = (acpi_madt_t *) current;
+ acpi_create_madt(madt);
+ current += madt->header.length;
+ ALIGN_CURRENT;
+ acpi_add_table(rsdt, madt);
+
+ printk_debug("ACPI: * MCFG\n");
+ mcfg = (acpi_mcfg_t *) current;
+ acpi_create_mcfg(mcfg);
+ current += mcfg->header.length;
+ ALIGN_CURRENT;
+ acpi_add_table(rsdt, mcfg);
+
+ printk_debug("ACPI: * FACS\n");
+ facs = (acpi_facs_t *) current;
+ current += sizeof(acpi_facs_t);
+ ALIGN_CURRENT;
+ acpi_create_facs(facs);
+
+ dsdt = (acpi_header_t *) current;
+ current += ((acpi_header_t *) AmlCode)->length;
+ ALIGN_CURRENT;
+ memcpy((void *) dsdt, (void *) AmlCode,
+ ((acpi_header_t *) AmlCode)->length);
+
+ printk_debug("ACPI: * DSDT @ %p Length %x\n", dsdt,
+ dsdt->length);
+
+ printk_debug("ACPI: * FADT\n");
+ fadt = (acpi_fadt_t *) current;
+ current += sizeof(acpi_fadt_t);
+ ALIGN_CURRENT;
+
+ acpi_create_fadt(fadt, facs, dsdt);
+ acpi_add_table(rsdt, fadt);
+
+ printk_info("ACPI: done.\n");
+ return current;
+}
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2008 coresystems GmbH
+ * Copyright (C) 2009 Thomas Jourdan <thomas.jourdan@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#define __ROMCC__
+
+#include <delay.h>
+
+#include <stdint.h>
+#include <arch/io.h>
+#include <arch/romcc_io.h>
+#include <device/pci_def.h>
+#include <device/pnp_def.h>
+#include <cpu/x86/lapic.h>
+
+#include "option_table.h"
+#include "pc80/mc146818rtc_early.c"
+
+#include "pc80/serial.c"
+#include "arch/i386/lib/console.c"
+#include <cpu/x86/bist.h>
+
+#include "ram/ramtest.c"
+#include "southbridge/intel/i3100/i3100_early_smbus.c"
+#include "southbridge/intel/i3100/i3100_early_lpc.c"
+#include "reset.c"
+#include "superio/intel/i3100/i3100_early_serial.c"
+#include "superio/smsc/smscsuperio/smscsuperio_early_serial.c"
+
+/* Data */
+#define UART_RBR 0x00
+#define UART_TBR 0x00
+
+/* Control */
+#define UART_IER 0x01
+#define UART_IIR 0x02
+#define UART_FCR 0x02
+#define UART_LCR 0x03
+#define UART_MCR 0x04
+#define UART_DLL 0x00
+#define UART_DLM 0x01
+
+/* Status */
+#define UART_LSR 0x05
+#define UART_MSR 0x06
+#define UART_SCR 0x07
+
+#define SIO_GPIO_BASE 0x680
+#define SIO_XBUS_BASE 0x4880
+
+#define DEVPRES_CONFIG (DEVPRES_D1F0 | DEVPRES_D2F0 | DEVPRES_D3F0)
+#define DEVPRES1_CONFIG (DEVPRES1_D0F1 | DEVPRES1_D8F0)
+
+#define IA32_PERF_STS 0x198
+#define IA32_PERF_CTL 0x199
+#define MSR_THERM2_CTL 0x19D
+#define IA32_MISC_ENABLES 0x1A0
+
+/* SATA */
+#define SATA_MAP 0x90
+
+#define SATA_MODE_IDE 0x00
+#define SATA_MODE_AHCI 0x01
+
+/* RCBA registers */
+#define RCBA 0xF0
+#define DEFAULT_RCBA 0xFEA00000
+
+#define RCBA_RPC 0x0224 /* 32 bit */
+
+#define RCBA_TCTL 0x3000 /* 8 bit */
+
+#define RCBA_D31IP 0x3100 /* 32 bit */
+#define RCBA_D30IP 0x3104 /* 32 bit */
+#define RCBA_D29IP 0x3108 /* 32 bit */
+#define RCBA_D28IP 0x310C /* 32 bit */
+#define RCBA_D31IR 0x3140 /* 16 bit */
+#define RCBA_D30IR 0x3142 /* 16 bit */
+#define RCBA_D29IR 0x3144 /* 16 bit */
+#define RCBA_D28IR 0x3146 /* 16 bit */
+
+#define RCBA_RTC 0x3400 /* 32 bit */
+#define RCBA_HPTC 0x3404 /* 32 bit */
+#define RCBA_GCS 0x3410 /* 32 bit */
+#define RCBA_BUC 0x3414 /* 8 bit */
+#define RCBA_FD 0x3418 /* 32 bit */
+#define RCBA_PRC 0x341C /* 32 bit */
+
+static inline void activate_spd_rom(const struct mem_controller *ctrl)
+{
+ /* nothing to do */
+}
+static inline int spd_read_byte(u16 device, u8 address)
+{
+ return smbus_read_byte(device, address);
+}
+
+#include "northbridge/intel/i3100/raminit.h"
+#include "cpu/x86/mtrr/earlymtrr.c"
+#include "northbridge/intel/i3100/memory_initialized.c"
+#include "northbridge/intel/i3100/raminit.c"
+#include "sdram/generic_sdram.c"
+#include "northbridge/intel/i3100/reset_test.c"
+#include "debug.c"
+
+#if CONFIG_USE_FALLBACK_IMAGE == 1
+#include "southbridge/intel/i3100/cmos_failover.c"
+#endif
+
+void early_config(void) {
+ device_t dev;
+ u32 gcs, rpc, fd;
+
+ /* Enable RCBA */
+ pci_write_config32(PCI_DEV(0, 0x1F, 0), RCBA, DEFAULT_RCBA | 1);
+
+ /* Disable watchdog */
+ gcs = readl(DEFAULT_RCBA + RCBA_GCS);
+ gcs |= (1 << 5); /* No reset */
+ writel(gcs, DEFAULT_RCBA + RCBA_GCS);
+
+ /* Configure PCIe port B as 4x */
+ rpc = readl(DEFAULT_RCBA + RCBA_RPC);
+ rpc |= (3 << 0);
+ writel(rpc, DEFAULT_RCBA + RCBA_RPC);
+
+ /* Disable Modem, Audio, PCIe ports 2/3/4 */
+ fd = readl(DEFAULT_RCBA + RCBA_FD);
+ fd |= (1 << 19) | (1 << 18) | (1 << 17) | (1 << 6) | (1 << 5);
+ writel(fd, DEFAULT_RCBA + RCBA_FD);
+
+ /* Enable HPET */
+ writel((1 << 7), DEFAULT_RCBA + RCBA_HPTC);
+
+ /* Improve interrupt routing
+ * D31:F2 SATA INTB# -> PIRQD
+ * D31:F3 SMBUS INTB# -> PIRQD
+ * D31:F4 CHAP INTD# -> PIRQA
+ * D29:F0 USB1#1 INTA# -> PIRQH
+ * D29:F1 USB1#2 INTB# -> PIRQD
+ * D29:F7 USB2 INTA# -> PIRQH
+ * D28:F0 PCIe Port 1 INTA# -> PIRQE
+ */
+
+ writew(0x0230, DEFAULT_RCBA + RCBA_D31IR);
+ writew(0x3210, DEFAULT_RCBA + RCBA_D30IR);
+ writew(0x3237, DEFAULT_RCBA + RCBA_D29IR);
+ writew(0x3214, DEFAULT_RCBA + RCBA_D28IR);
+
+ /* Setup sata mode */
+ pci_write_config8(PCI_DEV(0, 0x1F, 2), SATA_MAP, (SATA_MODE_AHCI << 6) | (0 << 0));
+}
+
+void real_main(unsigned long bist)
+{
+ /* int boot_mode = 0; */
+
+ static const struct mem_controller mch[] = {
+ {
+ .node_id = 0,
+ .f0 = PCI_DEV(0, 0x00, 0),
+ .f1 = PCI_DEV(0, 0x00, 1),
+ .f2 = PCI_DEV(0, 0x00, 2),
+ .f3 = PCI_DEV(0, 0x00, 3),
+ .channel0 = { (0xa<<3)|3, (0xa<<3)|2, (0xa<<3)|1, (0xa<<3)|0 },
+ .channel1 = { (0xa<<3)|7, (0xa<<3)|6, (0xa<<3)|5, (0xa<<3)|4 },
+ }
+ };
+
+ if (bist == 0) {
+ enable_lapic();
+ }
+
+ /* Setup the console */
+ i3100_enable_superio();
+ i3100_enable_serial(0x4E, I3100_SP1, CONFIG_TTYS0_BASE);
+ uart_init();
+ console_init();
+
+ /* Halt if there was a built in self test failure */
+ report_bist_failure(bist);
+
+ /* Perform early board specific init */
+ early_config();
+
+ /* Prevent the TCO timer from rebooting us */
+ i3100_halt_tco_timer();
+
+ /* Enable SPD ROMs and DDR-II DRAM */
+ enable_smbus();
+
+ /* Enable SpeedStep and automatic thermal throttling */
+ {
+ msr_t msr;
+ u16 perf;
+
+ msr = rdmsr(IA32_MISC_ENABLES);
+ msr.lo |= (1 << 3) | (1 << 16);
+ wrmsr(IA32_MISC_ENABLES, msr);
+
+ /* Set CPU frequency/voltage to maximum */
+
+ /* Read performance status register and keep
+ * bits 47:32, where BUS_RATIO_MAX and VID_MAX
+ * are encoded
+ */
+ msr = rdmsr(IA32_PERF_STS);
+ perf = msr.hi & 0x0000ffff;
+
+ /* Write VID_MAX & BUS_RATIO_MAX to
+ * performance control register
+ */
+ msr = rdmsr(IA32_PERF_CTL);
+ msr.lo &= 0xffff0000;
+ msr.lo |= perf;
+ wrmsr(IA32_PERF_CTL, msr);
+ }
+
+ /* Initialize memory */
+ sdram_initialize(ARRAY_SIZE(mch), mch);
+}
+
+#include "cpu/intel/model_6fx/cache_as_ram_disable.c"
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2008 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+extern struct chip_operations mainboard_ops;
+
+struct mainboard_config {
+ int nothing;
+};
--- /dev/null
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2007-2008 coresystems GmbH
+#
+# This program is free software; you can redistribute it and/or
+# modify it under the terms of the GNU General Public License as
+# published by the Free Software Foundation; version 2 of
+# the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+# MA 02110-1301 USA
+#
+
+# -----------------------------------------------------------------
+entries
+
+#start-bit length config config-ID name
+#0 8 r 0 seconds
+#8 8 r 0 alarm_seconds
+#16 8 r 0 minutes
+#24 8 r 0 alarm_minutes
+#32 8 r 0 hours
+#40 8 r 0 alarm_hours
+#48 8 r 0 day_of_week
+#56 8 r 0 day_of_month
+#64 8 r 0 month
+#72 8 r 0 year
+# -----------------------------------------------------------------
+# Status Register A
+#80 4 r 0 rate_select
+#84 3 r 0 REF_Clock
+#87 1 r 0 UIP
+# -----------------------------------------------------------------
+# Status Register B
+#88 1 r 0 auto_switch_DST
+#89 1 r 0 24_hour_mode
+#90 1 r 0 binary_values_enable
+#91 1 r 0 square-wave_out_enable
+#92 1 r 0 update_finished_enable
+#93 1 r 0 alarm_interrupt_enable
+#94 1 r 0 periodic_interrupt_enable
+#95 1 r 0 disable_clock_updates
+# -----------------------------------------------------------------
+# Status Register C
+#96 4 r 0 status_c_rsvd
+#100 1 r 0 uf_flag
+#101 1 r 0 af_flag
+#102 1 r 0 pf_flag
+#103 1 r 0 irqf_flag
+# -----------------------------------------------------------------
+# Status Register D
+#104 7 r 0 status_d_rsvd
+#111 1 r 0 valid_cmos_ram
+# -----------------------------------------------------------------
+# Diagnostic Status Register
+#112 8 r 0 diag_rsvd1
+
+# -----------------------------------------------------------------
+0 120 r 0 reserved_memory
+#120 264 r 0 unused
+
+# -----------------------------------------------------------------
+# RTC_BOOT_BYTE (coreboot hardcoded)
+384 1 e 4 boot_option
+385 1 e 4 last_boot
+388 4 r 0 reboot_bits
+#390 2 r 0 unused?
+
+# -----------------------------------------------------------------
+# coreboot config options: console
+392 3 e 5 baud_rate
+395 4 e 6 debug_level
+#399 1 r 0 unused
+
+# coreboot config options: cpu
+400 1 e 2 hyper_threading
+#401 7 r 0 unused
+
+# coreboot config options: southbridge
+408 1 e 1 nmi
+409 1 e 1 power_on_after_fail
+#410 6 r 0 unused
+
+# coreboot config options: bootloader
+416 512 s 0 boot_devices
+#928 80 r 0 unused
+
+# coreboot config options: check sums
+984 16 h 0 check_sum
+#1000 24 r 0 amd_reserved
+
+# -----------------------------------------------------------------
+
+enumerations
+
+#ID value text
+1 0 Disable
+1 1 Enable
+2 0 Enable
+2 1 Disable
+4 0 Fallback
+4 1 Normal
+5 0 115200
+5 1 57600
+5 2 38400
+5 3 19200
+5 4 9600
+5 5 4800
+5 6 2400
+5 7 1200
+6 1 Emergency
+6 2 Alert
+6 3 Critical
+6 4 Error
+6 5 Warning
+6 6 Notice
+6 7 Info
+6 8 Debug
+6 9 Spew
+
+# -----------------------------------------------------------------
+checksums
+
+checksum 392 983 984
+
+
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2008 coresystems GmbH
+ * Copyright (C) 2009 Thomas Jourdan <thomas.jourdan@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#define SMBUS_MEM_DEVICE_START 0x50
+#define SMBUS_MEM_DEVICE_END 0x57
+#define SMBUS_MEM_DEVICE_INC 1
+
+static void print_reg(unsigned char index)
+{
+ unsigned char data;
+
+ outb(index, 0x2e);
+ data = inb(0x2f);
+ print_debug("0x");
+ print_debug_hex8(index);
+ print_debug(": 0x");
+ print_debug_hex8(data);
+ print_debug("\r\n");
+ return;
+}
+
+static void xbus_en(void)
+{
+ /* select the XBUS function in the SIO */
+ outb(0x07, 0x2e);
+ outb(0x0f, 0x2f);
+ outb(0x30, 0x2e);
+ outb(0x01, 0x2f);
+ return;
+}
+
+static void setup_func(unsigned char func)
+{
+ /* select the function in the SIO */
+ outb(0x07, 0x2e);
+ outb(func, 0x2f);
+ /* print out the regs */
+ print_reg(0x30);
+ print_reg(0x60);
+ print_reg(0x61);
+ print_reg(0x62);
+ print_reg(0x63);
+ print_reg(0x70);
+ print_reg(0x71);
+ print_reg(0x74);
+ print_reg(0x75);
+ return;
+}
+
+static void siodump(void)
+{
+ int i;
+ unsigned char data;
+
+ print_debug("\r\n*** SERVER I/O REGISTERS ***\r\n");
+ for (i=0x10; i<=0x2d; i++) {
+ print_reg((unsigned char)i);
+ }
+#if 0
+ print_debug("\r\n*** XBUS REGISTERS ***\r\n");
+ setup_func(0x0f);
+ for (i=0xf0; i<=0xff; i++) {
+ print_reg((unsigned char)i);
+ }
+
+ print_debug("\r\n*** SERIAL 1 CONFIG REGISTERS ***\r\n");
+ setup_func(0x03);
+ print_reg(0xf0);
+
+ print_debug("\r\n*** SERIAL 2 CONFIG REGISTERS ***\r\n");
+ setup_func(0x02);
+ print_reg(0xf0);
+
+#endif
+ print_debug("\r\n*** GPIO REGISTERS ***\r\n");
+ setup_func(0x07);
+ for (i=0xf0; i<=0xf8; i++) {
+ print_reg((unsigned char)i);
+ }
+ print_debug("\r\n*** GPIO VALUES ***\r\n");
+ data = inb(0x68a);
+ print_debug("\r\nGPDO 4: 0x");
+ print_debug_hex8(data);
+ data = inb(0x68b);
+ print_debug("\r\nGPDI 4: 0x");
+ print_debug_hex8(data);
+ print_debug("\r\n");
+
+#if 0
+
+ print_debug("\r\n*** WATCHDOG TIMER REGISTERS ***\r\n");
+ setup_func(0x0a);
+ print_reg(0xf0);
+
+ print_debug("\r\n*** FAN CONTROL REGISTERS ***\r\n");
+ setup_func(0x09);
+ print_reg(0xf0);
+ print_reg(0xf1);
+
+ print_debug("\r\n*** RTC REGISTERS ***\r\n");
+ setup_func(0x10);
+ print_reg(0xf0);
+ print_reg(0xf1);
+ print_reg(0xf3);
+ print_reg(0xf6);
+ print_reg(0xf7);
+ print_reg(0xfe);
+ print_reg(0xff);
+
+ print_debug("\r\n*** HEALTH MONITORING & CONTROL REGISTERS ***\r\n");
+ setup_func(0x14);
+ print_reg(0xf0);
+#endif
+ return;
+}
+
+static void print_debug_pci_dev(unsigned dev)
+{
+ print_debug("PCI: ");
+ print_debug_hex8((dev >> 16) & 0xff);
+ print_debug_char(':');
+ print_debug_hex8((dev >> 11) & 0x1f);
+ print_debug_char('.');
+ print_debug_hex8((dev >> 8) & 7);
+}
+
+static void print_pci_devices(void)
+{
+ device_t dev;
+ for(dev = PCI_DEV(0, 0, 0);
+ dev <= PCI_DEV(0, 0x1f, 0x7);
+ dev += PCI_DEV(0,0,1)) {
+ uint32_t id;
+ id = pci_read_config32(dev, PCI_VENDOR_ID);
+ if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
+ (((id >> 16) & 0xffff) == 0xffff) ||
+ (((id >> 16) & 0xffff) == 0x0000)) {
+ continue;
+ }
+ print_debug_pci_dev(dev);
+ print_debug("\r\n");
+ }
+}
+
+static void dump_pci_device(unsigned dev)
+{
+ int i;
+ print_debug_pci_dev(dev);
+ print_debug("\r\n");
+
+ for(i = 0; i <= 255; i++) {
+ unsigned char val;
+ if ((i & 0x0f) == 0) {
+ print_debug_hex8(i);
+ print_debug_char(':');
+ }
+ val = pci_read_config8(dev, i);
+ print_debug_char(' ');
+ print_debug_hex8(val);
+ if ((i & 0x0f) == 0x0f) {
+ print_debug("\r\n");
+ }
+ }
+}
+
+static void dump_bar14(unsigned dev)
+{
+ int i;
+ unsigned long bar;
+
+ print_debug("BAR 14 Dump\r\n");
+
+ bar = pci_read_config32(dev, 0x14);
+ for(i = 0; i <= 0x300; i+=4) {
+#if 0
+ unsigned char val;
+ if ((i & 0x0f) == 0) {
+ print_debug_hex8(i);
+ print_debug_char(':');
+ }
+ val = pci_read_config8(dev, i);
+#endif
+ if((i%4)==0) {
+ print_debug("\r\n");
+ print_debug_hex16(i);
+ print_debug_char(' ');
+ }
+ print_debug_hex32(read32(bar + i));
+ print_debug_char(' ');
+ }
+ print_debug("\r\n");
+}
+
+static void dump_pci_devices(void)
+{
+ device_t dev;
+ for(dev = PCI_DEV(0, 0, 0);
+ dev <= PCI_DEV(0, 0x1f, 0x7);
+ dev += PCI_DEV(0,0,1)) {
+ uint32_t id;
+ id = pci_read_config32(dev, PCI_VENDOR_ID);
+ if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
+ (((id >> 16) & 0xffff) == 0xffff) ||
+ (((id >> 16) & 0xffff) == 0x0000)) {
+ continue;
+ }
+ dump_pci_device(dev);
+ }
+}
+
+#if 0
+static void dump_spd_registers(const struct mem_controller *ctrl)
+{
+ int i;
+ print_debug("\r\n");
+ for(i = 0; i < 4; i++) {
+ unsigned device;
+ device = ctrl->channel0[i];
+ if (device) {
+ int j;
+ print_debug("dimm: ");
+ print_debug_hex8(i);
+ print_debug(".0: ");
+ print_debug_hex8(device);
+ for(j = 0; j < 256; j++) {
+ int status;
+ unsigned char byte;
+ if ((j & 0xf) == 0) {
+ print_debug("\r\n");
+ print_debug_hex8(j);
+ print_debug(": ");
+ }
+ status = smbus_read_byte(device, j);
+ if (status < 0) {
+ print_debug("bad device\r\n");
+ break;
+ }
+ byte = status & 0xff;
+ print_debug_hex8(byte);
+ print_debug_char(' ');
+ }
+ print_debug("\r\n");
+ }
+ device = ctrl->channel1[i];
+ if (device) {
+ int j;
+ print_debug("dimm: ");
+ print_debug_hex8(i);
+ print_debug(".1: ");
+ print_debug_hex8(device);
+ for(j = 0; j < 256; j++) {
+ int status;
+ unsigned char byte;
+ if ((j & 0xf) == 0) {
+ print_debug("\r\n");
+ print_debug_hex8(j);
+ print_debug(": ");
+ }
+ status = smbus_read_byte(device, j);
+ if (status < 0) {
+ print_debug("bad device\r\n");
+ break;
+ }
+ byte = status & 0xff;
+ print_debug_hex8(byte);
+ print_debug_char(' ');
+ }
+ print_debug("\r\n");
+ }
+ }
+}
+#endif
+
+void dump_spd_registers(void)
+{
+ unsigned device;
+ device = SMBUS_MEM_DEVICE_START;
+ while(device <= SMBUS_MEM_DEVICE_END) {
+ int status = 0;
+ int i;
+ print_debug("\r\n");
+ print_debug("dimm ");
+ print_debug_hex8(device);
+
+ for(i = 0; (i < 256) ; i++) {
+ if ((i % 16) == 0) {
+ print_debug("\r\n");
+ print_debug_hex8(i);
+ print_debug(": ");
+ }
+ status = smbus_read_byte(device, i);
+ if (status < 0) {
+ print_debug("bad device: ");
+ print_debug_hex8(-status);
+ print_debug("\r\n");
+ break;
+ }
+ print_debug_hex8(status);
+ print_debug_char(' ');
+ }
+ device += SMBUS_MEM_DEVICE_INC;
+ print_debug("\n");
+ }
+}
+
+void dump_ipmi_registers(void)
+{
+ unsigned device;
+ device = 0x42;
+ while(device <= 0x42) {
+ int status = 0;
+ int i;
+ print_debug("\r\n");
+ print_debug("ipmi ");
+ print_debug_hex8(device);
+
+ for(i = 0; (i < 8) ; i++) {
+ status = smbus_read_byte(device, 2);
+ if (status < 0) {
+ print_debug("bad device: ");
+ print_debug_hex8(-status);
+ print_debug("\r\n");
+ break;
+ }
+ print_debug_hex8(status);
+ print_debug_char(' ');
+ }
+ device += SMBUS_MEM_DEVICE_INC;
+ print_debug("\n");
+ }
+}
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2009 Thomas Jourdan <thomas.jourdan@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+DefinitionBlock ("DSDT", "DSDT", 1, "EAGLE", "COREBOOT", 0x0000001)
+{
+ Scope (\_PR)
+ {
+ Processor (CPU1, 0x01, 0x00000810, 0x06)
+ {
+ OperationRegion (STBL, SystemMemory, 0xFFFF0000, 0xFFFF)
+ Name (NCPU, 0x80)
+ Name (TYPE, 0x80000000)
+ Name (HNDL, 0x80000000)
+ Name (CFGD, 0x80000000)
+ Name (TBLD, 0x80)
+ Method (_PDC, 1, NotSerialized)
+ {
+ }
+ }
+ }
+
+ Scope (\_PR)
+ {
+ Processor (CPU2, 0x02, 0x00000000, 0x00)
+ {
+ OperationRegion (STBL, SystemMemory, 0xFFFF0000, 0xFFFF)
+ Name (NCPU, 0x80)
+ Name (TYPE, 0x80000000)
+ Name (HNDL, 0x80000000)
+ Name (CFGD, 0x80000000)
+ Name (TBLD, 0x80)
+ Method (_PDC, 1, NotSerialized)
+ {
+ }
+ }
+ }
+
+ /* For now only define 2 power states:
+ * - S0 which is fully on
+ * - S5 which is soft off
+ * Any others would involve declaring the wake up methods.
+ */
+ Name (\_S0, Package () { 0x00, 0x00, 0x00, 0x00 })
+ Name (\_S5, Package () { 0x02, 0x02, 0x00, 0x00 })
+
+ Name (PICM, 0x00)
+ Method (_PIC, 1, NotSerialized)
+ {
+ Store (Arg0, PICM)
+ }
+
+ /* System bus */
+ Scope (\_SB)
+ {
+ /* Routing PCI0 */
+ Name (PR00, Package (0x0E)
+ {
+ Package (0x04){0x0001FFFF,0x00,LNKA,0x00}, /* EDMA INTA# */
+ Package (0x04){0x0002FFFF,0x00,LNKA,0x00}, /* PCIe port A */
+ Package (0x04){0x0002FFFF,0x01,LNKB,0x00},
+ Package (0x04){0x0002FFFF,0x02,LNKC,0x00},
+ Package (0x04){0x0002FFFF,0x03,LNKD,0x00},
+ Package (0x04){0x0003FFFF,0x00,LNKA,0x00}, /* PCIe port A1 */
+ Package (0x04){0x0003FFFF,0x01,LNKB,0x00},
+ Package (0x04){0x0003FFFF,0x02,LNKC,0x00},
+ Package (0x04){0x0003FFFF,0x03,LNKD,0x00},
+ Package (0x04){0x001CFFFF,0x00,LNKE,0x00}, /* PCIe port B */
+ Package (0x04){0x001DFFFF,0x00,LNKH,0x00}, /* UHCI/EHCI INTA# */
+ Package (0x04){0x001DFFFF,0x01,LNKD,0x00}, /* UHCI INTB# */
+ Package (0x04){0x001FFFFF,0x01,LNKD,0x00}, /* SATA/SMBUS INTB# */
+ Package (0x04){0x001FFFFF,0x03,LNKA,0x00} /* CHAP INTD# */
+ })
+ Name (AR00, Package (0x0E)
+ {
+ Package (0x04){0x0001FFFF,0x00,0x00,0x10}, /* EDMA INTA# */
+ Package (0x04){0x0002FFFF,0x00,0x00,0x10}, /* PCIe port A0 */
+ Package (0x04){0x0002FFFF,0x01,0x00,0x11},
+ Package (0x04){0x0002FFFF,0x02,0x00,0x12},
+ Package (0x04){0x0002FFFF,0x03,0x00,0x13},
+ Package (0x04){0x0003FFFF,0x00,0x00,0x10}, /* PCIe port A1 */
+ Package (0x04){0x0003FFFF,0x01,0x00,0x11},
+ Package (0x04){0x0003FFFF,0x02,0x00,0x12},
+ Package (0x04){0x0003FFFF,0x03,0x00,0x13},
+ Package (0x04){0x001CFFFF,0x00,0x00,0x14}, /* PCIe port B */
+ Package (0x04){0x001DFFFF,0x00,0x00,0x17}, /* UHCI/EHCI INTA# */
+ Package (0x04){0x001DFFFF,0x01,0x00,0x13}, /* UHCI INTB# */
+ Package (0x04){0x001FFFFF,0x01,0x00,0x13}, /* SATA/SMBUS INTB# */
+ Package (0x04){0x001FFFFF,0x0D,0x00,0x10} /* CHAP INTD# */
+ })
+ /* Routing PCIe Port A */
+ Name (PR0A, Package (0x04)
+ {
+ Package (0x04){0xFFFF,0x00,LNKA,0x00},
+ Package (0x04){0xFFFF,0x01,LNKB,0x00},
+ Package (0x04){0xFFFF,0x02,LNKC,0x00},
+ Package (0x04){0xFFFF,0x03,LNKD,0x00}
+ })
+ Name (AR0A, Package (0x04)
+ {
+ Package (0x04){0xFFFF,0x00,0x00,0x10},
+ Package (0x04){0xFFFF,0x01,0x00,0x11},
+ Package (0x04){0xFFFF,0x02,0x00,0x12},
+ Package (0x04){0xFFFF,0x03,0x00,0x13}
+ })
+ /* Routing PCIe Port B */
+ Name (PR0B, Package (0x04)
+ {
+ Package (0x04){0xFFFF,0x00,LNKA,0x00},
+ Package (0x04){0xFFFF,0x01,LNKB,0x00},
+ Package (0x04){0xFFFF,0x02,LNKC,0x00},
+ Package (0x04){0xFFFF,0x03,LNKD,0x00}
+ })
+ Name (AR0B, Package (0x04)
+ {
+ Package (0x04){0xFFFF,0x00,0x00,0x10},
+ Package (0x04){0xFFFF,0x01,0x00,0x11},
+ Package (0x04){0xFFFF,0x02,0x00,0x12},
+ Package (0x04){0xFFFF,0x03,0x00,0x13}
+ })
+ /* Routing Bus PCI */
+ Name (PR01, Package (0x04)
+ {
+ Package (0x04){0x0000FFFF,0x00,LNKA,0x00},
+ Package (0x04){0x0000FFFF,0x01,LNKB,0x00},
+ Package (0x04){0x0000FFFF,0x02,LNKC,0x00},
+ Package (0x04){0x0000FFFF,0x03,LNKD,0x00},
+ })
+ Name (AR01, Package (0x04)
+ {
+ Package (0x04){0x0000FFFF,0x00,0x00,0x10},
+ Package (0x04){0x0000FFFF,0x01,0x00,0x11},
+ Package (0x04){0x0000FFFF,0x02,0x00,0x12},
+ Package (0x04){0x0000FFFF,0x03,0x00,0x13},
+ })
+
+ Name (PRSA, ResourceTemplate ()
+ {
+ IRQ (Level, ActiveLow, Shared, )
+ {3,4,5,6,7,10,11,12,14,15}
+ })
+ Alias (PRSA, PRSB)
+ Alias (PRSA, PRSC)
+ Alias (PRSA, PRSD)
+ Alias (PRSA, PRSE)
+ Alias (PRSA, PRSF)
+ Alias (PRSA, PRSG)
+ Alias (PRSA, PRSH)
+
+ Device (PCI0)
+ {
+ Name (_HID, EisaId ("PNP0A08"))
+ Name (_CID, EisaId ("PNP0A03"))
+ Name (_ADR, 0x00)
+ Name (_SEG, 0x00)
+ Name (_UID, 0x00)
+ Name (_BBN, 0x00)
+
+ Name (SUPP, 0) /* PCI _OSC Support Field Value */
+ Name (CTRL, 0) /* PCI _OSC Control Field Value */
+
+ Method (_OSC, 4)
+ {
+ /* Check for proper GUID */
+ If (LEqual (Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766")))
+ {
+ /* Create DWORD-adressable field from the Capabilities Buffer */
+ CreateDWordField (Arg3, 0, CDW1)
+ CreateDWordField (Arg3, 4, CDW2)
+ CreateDWordField (Arg3, 8, CDW3)
+
+ /* Save Capabilities DWord 2 & 3 */
+ Store (CDW2, SUPP)
+ Store (CDW3, CTRL)
+
+ /* Don't care of OS capabilites */
+ /* We support nothing (maybe we should add PCIe Capability Structure Control) */
+ And (CTRL, 0x00, CTRL)
+
+ /* Query flag clear ? */
+ If (Not (And (CDW1, 1)))
+ {
+ /* Nothing to do */
+ }
+
+ /* Unknown revision ? */
+ If (LNotEqual (Arg1, One))
+ {
+ Or (CDW1, 0x08, CDW1)
+ }
+
+ /* Capabilities bits masked ? */
+ If (LNotEqual (CDW3, CTRL))
+ {
+ Or (CDW1, 0x10, CDW1)
+ }
+
+ /* Update DWORD3 in the buffer */
+ Store (CTRL, CDW3)
+
+ Return (Arg3)
+ }
+ Else
+ {
+ /* Unrecognized UUID */
+ Or (CDW1, 4, CDW1)
+ Return (Arg3)
+ }
+ } /* End _OSC */
+
+ Method (_PRT, 0, NotSerialized)
+ {
+ If (PICM)
+ {
+ Return (AR00)
+ }
+
+ Return (PR00)
+ }
+
+ /* PCI Express Port A */
+ Device (EPA0)
+ {
+ Name (_ADR, 0x00020000)
+ Method (_PRT, 0, NotSerialized)
+ {
+ If (PICM)
+ {
+ Return (AR0A)
+ }
+
+ Return (PR0A)
+ }
+ }
+
+ /* PCI Express Port A1 */
+ Device (EPA1)
+ {
+ Name (_ADR, 0x00030000)
+ Method (_PRT, 0, NotSerialized)
+ {
+ If (PICM)
+ {
+ Return (AR0A)
+ }
+
+ Return (PR0A)
+ }
+ }
+
+ /* PCI Express Port B0 */
+ Device (EPB0)
+ {
+ Name (_ADR, 0x001C0000)
+ Method (_PRT, 0, NotSerialized)
+ {
+ If (PICM)
+ {
+ Return (AR0B)
+ }
+
+ Return (PR0B)
+ }
+ }
+
+ /* PCI Bridge */
+ Device (P0P1)
+ {
+ Name (_ADR, 0x001E0000)
+
+ Method (_PRT, 0, NotSerialized)
+ {
+ If (PICM)
+ {
+ Return (AR01)
+ }
+
+ Return (PR01)
+ }
+ }
+
+ /* LPC I/F Bridge */
+ Device (ISA) {
+ Name (_ADR, 0x001F0000)
+
+ /* MMCONF */
+ Device (^PCIE)
+ {
+ Name (_HID, EisaId ("PNP0C02"))
+ Name (_UID, 0x11)
+ Name (CRS, ResourceTemplate ()
+ {
+ Memory32Fixed (ReadOnly,
+ 0xE0000000, // Address Base
+ 0x10000000, // Address Length
+ _Y10)
+ })
+ Method (_CRS, 0, NotSerialized)
+ {
+ CreateDWordField (CRS, \_SB.PCI0.PCIE._Y10._BAS, BAS1)
+ CreateDWordField (CRS, \_SB.PCI0.PCIE._Y10._LEN, LEN1)
+ Store (0xE0000000, BAS1)
+ Store (0x10000000, LEN1)
+ Return (CRS)
+ }
+ }
+
+ /* PIC */
+ Device (PIC)
+ {
+ Name (_HID, EisaId ("PNP0000"))
+ Name (_CRS, ResourceTemplate()
+ {
+ IO (Decode16,
+ 0x0020,
+ 0x0020,
+ 0x00,
+ 0x02,
+ )
+ IO (Decode16,
+ 0x00A0,
+ 0x00A0,
+ 0x00,
+ 0x02,
+ )
+ IRQNoFlags ()
+ {2}
+ })
+ }
+
+ /* Real time clock */
+ Device (RTC0)
+ {
+ Name (_HID, EisaId ("PNP0B00"))
+ Name (_CRS, ResourceTemplate ()
+ {
+ IO (Decode16,
+ 0x0070,
+ 0x0070,
+ 0x00,
+ 0x02)
+ IRQNoFlags ()
+ {8}
+ })
+ }
+
+ Device (UAR1)
+ {
+ Name (_UID, 0x01)
+ Name (_HID, EisaId ("PNP0501"))
+
+ Method (_PRS, 0, NotSerialized)
+ {
+ Return (CMPR)
+ }
+
+ Name (CMPR, ResourceTemplate ()
+ {
+ StartDependentFn (0x00, 0x00)
+ {
+ IO (Decode16,0x03F8,0x03F8,0x01,0x08)
+ IRQNoFlags () {4}
+ DMA (Compatibility, NotBusMaster, Transfer8) {}
+ }
+ StartDependentFnNoPri ()
+ {
+ IO (Decode16,0x03F8,0x03F8,0x01,0x08)
+ IRQNoFlags () {3,4,5,6,7,10,11,12}
+ DMA (Compatibility, NotBusMaster, Transfer8) {}
+ }
+ StartDependentFnNoPri ()
+ {
+ IO (Decode16,0x02F8,0x02F8,0x01,0x08)
+ IRQNoFlags () {3,4,5,6,7,10,11,12}
+ DMA (Compatibility, NotBusMaster, Transfer8) {}
+ }
+ StartDependentFnNoPri ()
+ {
+ IO (Decode16,0x03E8,0x03E8,0x01,0x08)
+ IRQNoFlags () {3,4,5,6,7,10,11,12}
+ DMA (Compatibility, NotBusMaster, Transfer8) {}
+ }
+ StartDependentFnNoPri ()
+ {
+ IO (Decode16,0x02E8,0x02E8,0x01,0x08)
+ IRQNoFlags () {3,4,5,6,7,10,11,12}
+ DMA (Compatibility, NotBusMaster, Transfer8) {}
+ }
+ EndDependentFn ()
+ })
+ }
+
+ /* PS/2 keyboard (seems to be important for WinXP install) */
+ Device (KBD)
+ {
+ Name (_HID, EisaId ("PNP0303"))
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (0x0f)
+ }
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (TMP, ResourceTemplate () {
+ IO (Decode16, 0x0060, 0x0060, 0x01, 0x01)
+ IO (Decode16, 0x0064, 0x0064, 0x01, 0x01)
+ IRQNoFlags () {1}
+ })
+ Return (TMP)
+ }
+ }
+
+ /* PS/2 mouse */
+ Device (MOU)
+ {
+ Name (_HID, EisaId ("PNP0F13"))
+ Method (_STA, 0, NotSerialized)
+ {
+ Return (0x0f)
+ }
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (TMP, ResourceTemplate () {
+ IRQNoFlags () {12}
+ })
+ Return (TMP)
+ }
+ }
+
+ /* COM ports of SIO */
+ Device(SIO) {
+ OperationRegion (PT4E, SystemIO, 0x4E, 0x02)
+ Field (PT4E, ByteAcc, NoLock, Preserve)
+ {
+ PO4E, 8,
+ PO4F, 8
+ }
+
+ IndexField (PO4E, PO4F, ByteAcc, NoLock, Preserve)
+ {
+ Offset (0x07),
+ ILDN, 8,
+ Offset (0x28),
+ SIUI, 8,
+ SIUC, 8,
+ Offset (0x30),
+ IACT, 8,
+ Offset (0x60),
+ IIOH, 8,
+ IIOL, 8,
+ Offset (0x70),
+ IINT, 8
+ }
+
+ Method (IENF, 0, NotSerialized)
+ {
+ Store (0x80, PO4E)
+ Store (0x86, PO4E)
+ }
+
+ Method (IEXF, 0, NotSerialized)
+ {
+ Store (0x68, PO4E)
+ Store (0x08, PO4E)
+ }
+
+ Device (COM1)
+ {
+ Name (_UID, 0x03)
+ Name (_HID, EisaId ("PNP0501"))
+ Method (_STA, 0, NotSerialized)
+ {
+ IENF ()
+ Store (0x04, ILDN)
+ Store (IACT, Local0)
+ IEXF ()
+ If (LEqual (Local0, 0xFF))
+ {
+ Return (0x00)
+ }
+
+ If (LEqual (Local0, One))
+ {
+ Return (0x0F)
+ }
+ Else
+ {
+ Return (0x0D)
+ }
+ }
+
+ Method (_DIS, 0, NotSerialized)
+ {
+ IENF ()
+ Store (0x04, ILDN)
+ Store (Zero, IACT)
+ IEXF ()
+ }
+
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (BFU1, ResourceTemplate ()
+ {
+ IO (Decode16,
+ 0x03F8, // Range Minimum
+ 0x03F8, // Range Maximum
+ 0x08, // Alignment
+ 0x08, // Length
+ _Y03)
+ IRQNoFlags (_Y04)
+ {5}
+ })
+ CreateWordField (BFU1, \_SB.PCI0.ISA.SIO.COM1._CRS._Y03._MIN, IMIN)
+ CreateWordField (BFU1, \_SB.PCI0.ISA.SIO.COM1._CRS._Y03._MAX, IMAX)
+ CreateWordField (BFU1, \_SB.PCI0.ISA.SIO.COM1._CRS._Y04._INT, IRQ0)
+ IENF ()
+ Store (0x04, ILDN)
+ Store (IIOH, Local0)
+ ShiftLeft (Local0, 0x08, Local1)
+ Store (IIOL, Local0)
+ Add (Local1, Local0, Local0)
+ Store (Local0, IMIN)
+ Store (Local0, IMAX)
+ Store (IINT, Local0)
+ IEXF ()
+ Store (0x01, Local1)
+ ShiftLeft (Local1, Local0, IRQ0)
+ Return (BFU1)
+ }
+
+ Name (_PRS, ResourceTemplate ()
+ {
+ StartDependentFnNoPri ()
+ {
+ IO (Decode16,
+ 0x03F8, // Range Minimum
+ 0x03F8, // Range Maximum
+ 0x08, // Alignment
+ 0x08, // Length
+ )
+ IRQNoFlags ()
+ {5}
+ }
+ StartDependentFnNoPri ()
+ {
+ IO (Decode16,
+ 0x02F8, // Range Minimum
+ 0x02F8, // Range Maximum
+ 0x08, // Alignment
+ 0x08, // Length
+ )
+ IRQNoFlags ()
+ {9}
+ }
+ EndDependentFn ()
+ })
+ Method (_SRS, 1, NotSerialized)
+ {
+ CreateByteField (Arg0, 0x02, IOLO)
+ CreateByteField (Arg0, 0x03, IOHI)
+ CreateWordField (Arg0, 0x09, IRQ0)
+ IENF ()
+ Store (0x04, ILDN)
+ Store (Zero, IACT)
+ Store (IOLO, IIOL)
+ Store (IOHI, IIOH)
+ FindSetRightBit (IRQ0, Local0)
+ If (LGreater (Local0, 0x00))
+ {
+ Decrement (Local0)
+ }
+
+ Store (Local0, IINT)
+ Store (One, IACT)
+ IEXF ()
+ }
+ } /* COM1 */
+
+ Device (COM2)
+ {
+ Name (_UID, 0x04)
+ Name (_HID, EisaId ("PNP0501"))
+ Method (_STA, 0, NotSerialized)
+ {
+ IENF ()
+ Store (0x05, ILDN)
+ Store (IACT, Local0)
+ IEXF ()
+ If (LEqual (Local0, 0xFF))
+ {
+ Return (0x00)
+ }
+
+ If (LEqual (Local0, One))
+ {
+ Return (0x0F)
+ }
+ Else
+ {
+ Return (0x0D)
+ }
+ }
+
+ Method (_DIS, 0, NotSerialized)
+ {
+ IENF ()
+ Store (0x05, ILDN)
+ Store (Zero, IACT)
+ IEXF ()
+ }
+
+ Method (_CRS, 0, NotSerialized)
+ {
+ Name (BFU1, ResourceTemplate ()
+ {
+ IO (Decode16,
+ 0x03F8, // Range Minimum
+ 0x03F8, // Range Maximum
+ 0x08, // Alignment
+ 0x08, // Length
+ _Y05)
+ IRQNoFlags (_Y06)
+ {9}
+ })
+ CreateWordField (BFU1, \_SB.PCI0.ISA.SIO.COM2._CRS._Y05._MIN, IMIN)
+ CreateWordField (BFU1, \_SB.PCI0.ISA.SIO.COM2._CRS._Y05._MAX, IMAX)
+ CreateWordField (BFU1, \_SB.PCI0.ISA.SIO.COM2._CRS._Y06._INT, IRQ0)
+ IENF ()
+ Store (0x05, ILDN)
+ Store (IIOH, Local0)
+ ShiftLeft (Local0, 0x08, Local1)
+ Store (IIOL, Local0)
+ Add (Local1, Local0, Local0)
+ Store (Local0, IMIN)
+ Store (Local0, IMAX)
+ Store (IINT, Local0)
+ IEXF ()
+ Store (0x01, Local1)
+ ShiftLeft (Local1, Local0, IRQ0)
+ Return (BFU1)
+ }
+
+ Name (_PRS, ResourceTemplate ()
+ {
+ StartDependentFnNoPri ()
+ {
+ IO (Decode16,
+ 0x03F8, // Range Minimum
+ 0x03F8, // Range Maximum
+ 0x08, // Alignment
+ 0x08, // Length
+ )
+ IRQNoFlags ()
+ {5}
+ }
+ StartDependentFnNoPri ()
+ {
+ IO (Decode16,
+ 0x02F8, // Range Minimum
+ 0x02F8, // Range Maximum
+ 0x08, // Alignment
+ 0x08, // Length
+ )
+ IRQNoFlags ()
+ {9}
+ }
+ EndDependentFn ()
+ })
+ Method (_SRS, 1, NotSerialized)
+ {
+ CreateByteField (Arg0, 0x02, IOLO)
+ CreateByteField (Arg0, 0x03, IOHI)
+ CreateWordField (Arg0, 0x09, IRQ0)
+ IENF ()
+ Store (0x05, ILDN)
+ Store (Zero, IACT)
+ Store (IOLO, IIOL)
+ Store (IOHI, IIOH)
+ FindSetRightBit (IRQ0, Local0)
+ If (LGreater (Local0, 0x00))
+ {
+ Decrement (Local0)
+ }
+
+ Store (Local0, IINT)
+ Store (One, IACT)
+ IEXF ()
+ }
+ } /* COM2 */
+ } /* Device SIO */
+ } /* Device ISA */
+ } /* Device PCI 0*/
+ } /* Scope SB */
+
+ OperationRegion (_SB.PCI0.ISA.PIX0, PCI_Config, 0x60, 0x0C)
+ Field (\_SB.PCI0.ISA.PIX0, ByteAcc, NoLock, Preserve)
+ {
+ PIRA, 8,
+ PIRB, 8,
+ PIRC, 8,
+ PIRD, 8,
+ Offset (0x08),
+ PIRE, 8,
+ PIRF, 8,
+ PIRG, 8,
+ PIRH, 8
+ }
+
+ Scope (_SB)
+ {
+ Name (BUFA, ResourceTemplate ()
+ {
+ IRQ (Level, ActiveLow, Shared, _Y1C)
+ {15}
+ })
+ CreateWordField (BUFA, \_SB._Y1C._INT, IRA0)
+ Device (LNKA)
+ {
+ Name (_HID, EisaId ("PNP0C0F"))
+ Name (_UID, 0x01)
+ Method (_STA, 0, NotSerialized)
+ {
+ And (PIRA, 0x80, Local0)
+ If (Local0)
+ {
+ Return (0x09)
+ }
+ Else
+ {
+ Return (0x0B)
+ }
+ }
+
+ Method (_PRS, 0, NotSerialized)
+ {
+ Return (PRSA)
+ }
+
+ Method (_DIS, 0, NotSerialized)
+ {
+ Or (PIRA, 0x80, PIRA)
+ }
+
+ Method (_CRS, 0, NotSerialized)
+ {
+ And (PIRA, 0x0F, Local0)
+ ShiftLeft (0x01, Local0, IRA0)
+ Return (BUFA)
+ }
+
+ Method (_SRS, 1, NotSerialized)
+ {
+ CreateWordField (Arg0, 0x01, IRA)
+ FindSetRightBit (IRA, Local0)
+ Decrement (Local0)
+ Store (Local0, PIRA)
+ }
+ }
+
+ Device (LNKB)
+ {
+ Name (_HID, EisaId ("PNP0C0F"))
+ Name (_UID, 0x02)
+ Method (_STA, 0, NotSerialized)
+ {
+ And (PIRB, 0x80, Local0)
+ If (Local0)
+ {
+ Return (0x09)
+ }
+ Else
+ {
+ Return (0x0B)
+ }
+ }
+
+ Method (_PRS, 0, NotSerialized)
+ {
+ Return (PRSB)
+ }
+
+ Method (_DIS, 0, NotSerialized)
+ {
+ Or (PIRB, 0x80, PIRB)
+ }
+
+ Method (_CRS, 0, NotSerialized)
+ {
+ And (PIRB, 0x0F, Local0)
+ ShiftLeft (0x01, Local0, IRA0)
+ Return (BUFA)
+ }
+
+ Method (_SRS, 1, NotSerialized)
+ {
+ CreateWordField (Arg0, 0x01, IRA)
+ FindSetRightBit (IRA, Local0)
+ Decrement (Local0)
+ Store (Local0, PIRB)
+ }
+ }
+
+ Device (LNKC)
+ {
+ Name (_HID, EisaId ("PNP0C0F"))
+ Name (_UID, 0x03)
+ Method (_STA, 0, NotSerialized)
+ {
+ And (PIRC, 0x80, Local0)
+ If (Local0)
+ {
+ Return (0x09)
+ }
+ Else
+ {
+ Return (0x0B)
+ }
+ }
+
+ Method (_PRS, 0, NotSerialized)
+ {
+ Return (PRSC)
+ }
+
+ Method (_DIS, 0, NotSerialized)
+ {
+ Or (PIRC, 0x80, PIRC)
+ }
+
+ Method (_CRS, 0, NotSerialized)
+ {
+ And (PIRC, 0x0F, Local0)
+ ShiftLeft (0x01, Local0, IRA0)
+ Return (BUFA)
+ }
+
+ Method (_SRS, 1, NotSerialized)
+ {
+ CreateWordField (Arg0, 0x01, IRA)
+ FindSetRightBit (IRA, Local0)
+ Decrement (Local0)
+ Store (Local0, PIRC)
+ }
+ }
+
+ Device (LNKD)
+ {
+ Name (_HID, EisaId ("PNP0C0F"))
+ Name (_UID, 0x04)
+ Method (_STA, 0, NotSerialized)
+ {
+ And (PIRD, 0x80, Local0)
+ If (Local0)
+ {
+ Return (0x09)
+ }
+ Else
+ {
+ Return (0x0B)
+ }
+ }
+
+ Method (_PRS, 0, NotSerialized)
+ {
+ Return (PRSD)
+ }
+
+ Method (_DIS, 0, NotSerialized)
+ {
+ Or (PIRD, 0x80, PIRD)
+ }
+
+ Method (_CRS, 0, NotSerialized)
+ {
+ And (PIRD, 0x0F, Local0)
+ ShiftLeft (0x01, Local0, IRA0)
+ Return (BUFA)
+ }
+
+ Method (_SRS, 1, NotSerialized)
+ {
+ CreateWordField (Arg0, 0x01, IRA)
+ FindSetRightBit (IRA, Local0)
+ Decrement (Local0)
+ Store (Local0, PIRD)
+ }
+ }
+
+ Device (LNKE)
+ {
+ Name (_HID, EisaId ("PNP0C0F"))
+ Name (_UID, 0x05)
+ Method (_STA, 0, NotSerialized)
+ {
+ And (PIRE, 0x80, Local0)
+ If (Local0)
+ {
+ Return (0x09)
+ }
+ Else
+ {
+ Return (0x0B)
+ }
+ }
+
+ Method (_PRS, 0, NotSerialized)
+ {
+ Return (PRSE)
+ }
+
+ Method (_DIS, 0, NotSerialized)
+ {
+ Or (PIRE, 0x80, PIRE)
+ }
+
+ Method (_CRS, 0, NotSerialized)
+ {
+ And (PIRE, 0x0F, Local0)
+ ShiftLeft (0x01, Local0, IRA0)
+ Return (BUFA)
+ }
+
+ Method (_SRS, 1, NotSerialized)
+ {
+ CreateWordField (Arg0, 0x01, IRA)
+ FindSetRightBit (IRA, Local0)
+ Decrement (Local0)
+ Store (Local0, PIRE)
+ }
+ }
+
+ Device (LNKF)
+ {
+ Name (_HID, EisaId ("PNP0C0F"))
+ Name (_UID, 0x06)
+ Method (_STA, 0, NotSerialized)
+ {
+ And (PIRF, 0x80, Local0)
+ If (Local0)
+ {
+ Return (0x09)
+ }
+ Else
+ {
+ Return (0x0B)
+ }
+ }
+
+ Method (_PRS, 0, NotSerialized)
+ {
+ Return (PRSF)
+ }
+
+ Method (_DIS, 0, NotSerialized)
+ {
+ Or (PIRF, 0x80, PIRF)
+ }
+
+ Method (_CRS, 0, NotSerialized)
+ {
+ And (PIRF, 0x0F, Local0)
+ ShiftLeft (0x01, Local0, IRA0)
+ Return (BUFA)
+ }
+
+ Method (_SRS, 1, NotSerialized)
+ {
+ CreateWordField (Arg0, 0x01, IRA)
+ FindSetRightBit (IRA, Local0)
+ Decrement (Local0)
+ Store (Local0, PIRF)
+ }
+ }
+
+ Device (LNKG)
+ {
+ Name (_HID, EisaId ("PNP0C0F"))
+ Name (_UID, 0x07)
+ Method (_STA, 0, NotSerialized)
+ {
+ And (PIRG, 0x80, Local0)
+ If (Local0)
+ {
+ Return (0x09)
+ }
+ Else
+ {
+ Return (0x0B)
+ }
+ }
+
+ Method (_PRS, 0, NotSerialized)
+ {
+ Return (PRSG)
+ }
+
+ Method (_DIS, 0, NotSerialized)
+ {
+ Or (PIRG, 0x80, PIRG)
+ }
+
+ Method (_CRS, 0, NotSerialized)
+ {
+ And (PIRG, 0x0F, Local0)
+ ShiftLeft (0x01, Local0, IRA0)
+ Return (BUFA)
+ }
+
+ Method (_SRS, 1, NotSerialized)
+ {
+ CreateWordField (Arg0, 0x01, IRA)
+ FindSetRightBit (IRA, Local0)
+ Decrement (Local0)
+ Store (Local0, PIRG)
+ }
+ }
+
+ Device (LNKH)
+ {
+ Name (_HID, EisaId ("PNP0C0F"))
+ Name (_UID, 0x08)
+ Method (_STA, 0, NotSerialized)
+ {
+ And (PIRH, 0x80, Local0)
+ If (Local0)
+ {
+ Return (0x09)
+ }
+ Else
+ {
+ Return (0x0B)
+ }
+ }
+
+ Method (_PRS, 0, NotSerialized)
+ {
+ Return (PRSH)
+ }
+
+ Method (_DIS, 0, NotSerialized)
+ {
+ Or (PIRH, 0x80, PIRH)
+ }
+
+ Method (_CRS, 0, NotSerialized)
+ {
+ And (PIRH, 0x0F, Local0)
+ ShiftLeft (0x01, Local0, IRA0)
+ Return (BUFA)
+ }
+
+ Method (_SRS, 1, NotSerialized)
+ {
+ CreateWordField (Arg0, 0x01, IRA)
+ FindSetRightBit (IRA, Local0)
+ Decrement (Local0)
+ Store (Local0, PIRH)
+ }
+ }
+ }
+}
+
+
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2008 coresystems GmbH
+ * Copyright (C) 2009 Thomas Jourdan <thomas.jourdan@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <string.h>
+#include <device/pci.h>
+#include <arch/acpi.h>
+
+#define ACPI_PM1_STS (pmbase + 0x00)
+#define ACPI_PM1_EN (pmbase + 0x02)
+#define ACPI_PM1_CNT (pmbase + 0x04)
+#define ACPI_PM1_TMR (pmbase + 0x08)
+#define ACPI_PROC_CNT (pmbase + 0x10)
+#define ACPI_LV2 (pmbase + 0x14)
+#define ACPI_GPE0_STS (pmbase + 0x28)
+#define ACPI_GPE0_EN (pmbase + 0x2C)
+#define ACPI_SMI_EN (pmbase + 0x30)
+#define ACPI_SMI_STS (pmbase + 0x34)
+#define ACPI_ALT_GP_SMI_EN (pmbase + 0x38)
+#define ACPI_ALT_GP_SMI_STS (pmbase + 0x3A)
+#define ACPI_MON_SMI (pmbase + 0x40)
+#define ACPI_DEVACT_STS (pmbase + 0x44)
+#define ACPI_DEVTRAP_EN (pmbase + 0x48)
+#define ACPI_BUS_ADDR_TRACK (pmbase + 0x4C)
+#define ACPI_BUS_CYC_TRACK (pmbase + 0x4E)
+
+#define ACPI_PM1a_EVT_BLK ACPI_PM1_STS
+#define ACPI_PM1a_CNT_BLK ACPI_PM1_CNT
+#define ACPI_PM_TMR_BLK ACPI_PM1_TMR
+#define ACPI_P_BLK ACPI_PROC_CNT
+#define ACPI_GPE0_BLK ACPI_GPE0_STS
+
+void acpi_create_fadt(acpi_fadt_t * fadt, acpi_facs_t * facs, void *dsdt)
+{
+ acpi_header_t *header = &(fadt->header);
+ u16 pmbase = pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f,0)), 0x40) & 0xfffe;
+
+ memset((void *) fadt, 0, sizeof(acpi_fadt_t));
+ memcpy(header->signature, "FACP", 4);
+ header->length = 244;
+ header->revision = 1;
+ memcpy(header->oem_id, "CORE ", 6);
+ memcpy(header->oem_table_id, "COREBOOT", 8);
+ memcpy(header->asl_compiler_id, "CORE", 4);
+ header->asl_compiler_revision = 0;
+
+ fadt->firmware_ctrl = (unsigned long) facs;
+ fadt->dsdt = (unsigned long) dsdt;
+ fadt->preferred_pm_profile = 7; /* Performance Server */
+ fadt->sci_int = 0x9;
+#if HAVE_SMI_HANDLER == 1
+ fadt->smi_cmd = 0xb2;
+#else
+ fadt->smi_cmd = 0x00;
+#endif
+ fadt->acpi_enable = 0xe1;
+ fadt->acpi_disable = 0x1e;
+ fadt->s4bios_req = 0x0;
+ fadt->pstate_cnt = 0xe2;
+
+ fadt->pm1a_evt_blk = pmbase;
+ fadt->pm1b_evt_blk = 0x0;
+ fadt->pm1a_cnt_blk = pmbase + 0x4;
+ fadt->pm1b_cnt_blk = 0x0;
+ fadt->pm2_cnt_blk = 0x0;
+ fadt->pm_tmr_blk = pmbase + 0x8;
+ fadt->gpe0_blk = pmbase + 0x28;
+ fadt->gpe1_blk = 0x0;
+
+ fadt->pm1_evt_len = 0x4;
+ fadt->pm1_cnt_len = 0x2;
+ fadt->pm2_cnt_len = 0x0;
+ fadt->pm_tmr_len = 0x4;
+ fadt->gpe0_blk_len = 0x8;
+ fadt->gpe1_blk_len = 0x0;
+ fadt->gpe1_base = 0x0;
+ fadt->cst_cnt = 0xe3;
+ fadt->p_lvl2_lat = 0x65;
+ fadt->p_lvl3_lat = 0x3e9;
+ fadt->flush_size = 0x400;
+ fadt->flush_stride = 0x10;
+ fadt->duty_offset = 0x1;
+ fadt->duty_width = 0x3;
+ fadt->day_alrm = 0xd;
+ fadt->mon_alrm = 0x00;
+ fadt->century = 0x00;
+ fadt->iapc_boot_arch = 0x03;
+ fadt->flags = 0xa5;
+
+ fadt->reset_reg.space_id = 1;
+ fadt->reset_reg.bit_width = 8;
+ fadt->reset_reg.bit_offset = 0;
+ fadt->reset_reg.resv = 0;
+ fadt->reset_reg.addrl = 0xcf9;
+ fadt->reset_reg.addrh = 0;
+ fadt->reset_value = 6;
+ fadt->res3 = 0;
+ fadt->res4 = 0;
+ fadt->res5 = 0;
+ fadt->x_firmware_ctl_l = facs;
+ fadt->x_firmware_ctl_h = 0;
+ fadt->x_dsdt_l = dsdt;
+ fadt->x_dsdt_h = 0;
+
+ fadt->x_pm1a_evt_blk.space_id = 1;
+ fadt->x_pm1a_evt_blk.bit_width = 32;
+ fadt->x_pm1a_evt_blk.bit_offset = 0;
+ fadt->x_pm1a_evt_blk.resv = 0;
+ fadt->x_pm1a_evt_blk.addrl = pmbase;
+ fadt->x_pm1a_evt_blk.addrh = 0x0;
+
+ fadt->x_pm1b_evt_blk.space_id = 1;
+ fadt->x_pm1b_evt_blk.bit_width = 32;
+ fadt->x_pm1b_evt_blk.bit_offset = 0;
+ fadt->x_pm1b_evt_blk.resv = 0;
+ fadt->x_pm1b_evt_blk.addrl = 0x0;
+ fadt->x_pm1b_evt_blk.addrh = 0x0;
+
+ fadt->x_pm1a_cnt_blk.space_id = 1;
+ fadt->x_pm1a_cnt_blk.bit_width = 16;
+ fadt->x_pm1a_cnt_blk.bit_offset = 0;
+ fadt->x_pm1a_cnt_blk.resv = 0;
+ fadt->x_pm1a_cnt_blk.addrl = pmbase + 0x4;
+ fadt->x_pm1a_cnt_blk.addrh = 0x0;
+
+ fadt->x_pm1b_cnt_blk.space_id = 1;
+ fadt->x_pm1b_cnt_blk.bit_width = 0;
+ fadt->x_pm1b_cnt_blk.bit_offset = 0;
+ fadt->x_pm1b_cnt_blk.resv = 0;
+ fadt->x_pm1b_cnt_blk.addrl = 0x0;
+ fadt->x_pm1b_cnt_blk.addrh = 0x0;
+
+ fadt->x_pm2_cnt_blk.space_id = 1;
+ fadt->x_pm2_cnt_blk.bit_width = 0;
+ fadt->x_pm2_cnt_blk.bit_offset = 0;
+ fadt->x_pm2_cnt_blk.resv = 0;
+ fadt->x_pm2_cnt_blk.addrl = 0x0;
+ fadt->x_pm2_cnt_blk.addrh = 0x0;
+
+ fadt->x_pm_tmr_blk.space_id = 1;
+ fadt->x_pm_tmr_blk.bit_width = 32;
+ fadt->x_pm_tmr_blk.bit_offset = 0;
+ fadt->x_pm_tmr_blk.resv = 0;
+ fadt->x_pm_tmr_blk.addrl = pmbase + 0x8;
+ fadt->x_pm_tmr_blk.addrh = 0x0;
+
+ fadt->x_gpe0_blk.space_id = 1;
+ fadt->x_gpe0_blk.bit_width = 64;
+ fadt->x_gpe0_blk.bit_offset = 0;
+ fadt->x_gpe0_blk.resv = 0;
+ fadt->x_gpe0_blk.addrl = pmbase + 0x28;
+ fadt->x_gpe0_blk.addrh = 0x0;
+
+ fadt->x_gpe1_blk.space_id = 1;
+ fadt->x_gpe1_blk.bit_width = 32;
+ fadt->x_gpe1_blk.bit_offset = 0;
+ fadt->x_gpe1_blk.resv = 0;
+ fadt->x_gpe1_blk.addrl = 0x0;
+ fadt->x_gpe1_blk.addrh = 0x0;
+
+ header->checksum =
+ acpi_checksum((void *) fadt, header->length);
+}
--- /dev/null
+#define IOAPIC_I3100 2
+#define INTEL_IOAPIC_NUM_INTERRUPTS 24
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2009 Thomas Jourdan <thomas.jourdan@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <arch/pirq_routing.h>
+
+const struct irq_routing_table intel_irq_routing_table = {
+ PIRQ_SIGNATURE, /* u32 signature */
+ PIRQ_VERSION, /* u16 version */
+ 32 + 16 * 9, /* Max. number of devices on the bus */
+ 0x00, /* Interrupt router bus */
+ (0x1f << 3) | 0x0, /* Interrupt router dev */
+ 0, /* IRQs devoted exclusively to PCI usage */
+ 0x8086, /* Vendor */
+ 0x2670, /* Device */
+ 0, /* Miniport */
+ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
+ 0x4b, /* Checksum (has to be set to some value that
+ * would give 0 after the sum of all bytes
+ * for this structure (including checksum).
+ */
+ {
+ /* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
+ {0x00, (0x01 << 3) | 0x0, {{0x60, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
+ {0x00, (0x02 << 3) | 0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcf8}}, 0x0, 0x0},
+ {0x00, (0x03 << 3) | 0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcf8}}, 0x0, 0x0},
+ {0x00, (0x1f << 3) | 0x0, {{0x00, 0x0000}, {0x63, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
+ {0x00, (0x1d << 3) | 0x0, {{0x6b, 0xdcf8}, {0x63, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
+ {0x00, (0x1c << 3) | 0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcf8}}, 0x0, 0x0},
+ {0x02, (0x00 << 3) | 0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcf8}}, 0x20, 0x0},
+ {0x01, (0x00 << 3) | 0x0, {{0x60, 0xdcf8}, {0x61, 0xdcf8}, {0x62, 0xdcf8}, {0x63, 0xdcf8}}, 0x1, 0x0},
+ {0x01, (0x01 << 3) | 0x0, {{0x61, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x0, 0x0},
+ }
+};
+
+unsigned long write_pirq_routing_table(unsigned long addr)
+{
+ return copy_pirq_routing_table(addr);
+}
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2008 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+
+#include <device/device.h>
+#include "chip.h"
+
+int add_mainboard_resources(struct lb_memory *mem)
+{
+}
+
+struct chip_operations mainboard_ops = {
+ CHIP_NAME("Intel Eagle Heights Mainboard")
+};
+
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2008 coresystems GmbH
+ * Copyright (C) 2009 Thomas Jourdan <thomas.jourdan@gmail.com>
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+
+#include <console/console.h>
+#include <arch/io.h>
+#include <arch/smp/mpspec.h>
+#include <device/pci.h>
+#include <string.h>
+#include <stdint.h>
+
+// Generate MP-table IRQ numbers for PCI devices.
+#define IO_APIC0 2
+
+#define INT_A 0
+#define INT_B 1
+#define INT_C 2
+#define INT_D 3
+#define PCI_IRQ(dev, intLine) (((dev)<<2) | intLine)
+
+#define PIRQ_A 16
+#define PIRQ_B 17
+#define PIRQ_C 18
+#define PIRQ_D 19
+#define PIRQ_E 20
+#define PIRQ_F 21
+#define PIRQ_G 22
+#define PIRQ_H 23
+
+// RCBA
+#define RCBA 0xF0
+
+#define RCBA_D31IP 0x3100
+#define RCBA_D30IP 0x3104
+#define RCBA_D29IP 0x3108
+#define RCBA_D28IP 0x310C
+#define RCBA_D31IR 0x3140
+#define RCBA_D30IR 0x3142
+#define RCBA_D29IR 0x3144
+#define RCBA_D28IR 0x3146
+
+void *smp_write_config_table(void *v)
+{
+ static const char sig[4] = "PCMP";
+ static const char oem[8] = "Intel ";
+ static const char productid[12] = "EagleHeights";
+ struct mp_config_table *mc;
+ unsigned char bus_num, bus_chipset, bus_isa, bus_pci;
+ unsigned char bus_pcie_a, bus_pcie_a1, bus_pcie_b;
+ int i;
+ uint32_t pin, route;
+ device_t dev;
+ struct resource *res;
+ unsigned long rcba;
+
+ dev = dev_find_slot(0, PCI_DEVFN(0x1F,0));
+ res = find_resource(dev, RCBA);
+ if (!res) {
+ return;
+ }
+ rcba = res->base;
+
+ mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);
+ memset(mc, 0, sizeof(*mc));
+
+ memcpy(mc->mpc_signature, sig, sizeof(sig));
+ mc->mpc_length = sizeof(*mc); /* initially just the header */
+ mc->mpc_spec = 0x04;
+ mc->mpc_checksum = 0; /* not yet computed */
+ memcpy(mc->mpc_oem, oem, sizeof(oem));
+ memcpy(mc->mpc_productid, productid, sizeof(productid));
+ mc->mpc_oemptr = 0;
+ mc->mpc_oemsize = 0;
+ mc->mpc_entry_count = 0; /* No entries yet... */
+ mc->mpc_lapic = LAPIC_ADDR;
+ mc->mpe_length = 0;
+ mc->mpe_checksum = 0;
+ mc->reserved = 0;
+
+ smp_write_processors(mc);
+
+ /* Get bus numbers */
+ bus_chipset = 0;
+
+ /* PCI */
+ dev = dev_find_slot(0, PCI_DEVFN(0x1E,0));
+ if (dev) {
+ bus_pci = pci_read_config8(dev, PCI_SECONDARY_BUS);
+ bus_isa = pci_read_config8(dev, PCI_SUBORDINATE_BUS);
+ bus_isa++;
+ } else {
+ printk_debug("ERROR - could not find PCI 0:1e.0, using defaults\n");
+ bus_pci = 6;
+ bus_isa = 7;
+ }
+
+ dev = dev_find_slot(0, PCI_DEVFN(2,0));
+ if(dev) {
+ bus_pcie_a = pci_read_config8(dev, PCI_SECONDARY_BUS);
+ } else {
+ printk_debug("ERROR - could not find PCIe Port A 0:2.0, using defaults\n");
+ bus_pcie_a = 1;
+ }
+
+ dev = dev_find_slot(0, PCI_DEVFN(3,0));
+ if(dev) {
+ bus_pcie_a1 = pci_read_config8(dev, PCI_SECONDARY_BUS);
+ } else {
+ printk_debug("ERROR - could not find PCIe Port B 0:3.0, using defaults\n");
+ bus_pcie_a1 = 2;
+ }
+
+ dev = dev_find_slot(0, PCI_DEVFN(0x1C,0));
+ if(dev) {
+ bus_pcie_b = pci_read_config8(dev, PCI_SECONDARY_BUS);
+ } else {
+ printk_debug("ERROR - could not find PCIe Port B 0:3.0, using defaults\n");
+ bus_pcie_b = 3;
+ }
+
+ /*Bus: Bus ID Type*/
+ for(bus_num = 0; bus_num < bus_isa; bus_num++) {
+ smp_write_bus(mc, bus_num, "PCI ");
+ }
+ smp_write_bus(mc, bus_isa, "ISA ");
+
+ /*I/O APICs: APIC ID Version State Address*/
+ smp_write_ioapic(mc, 2, 0x20, 0xfec00000);
+ /*
+ {
+ device_t dev;
+ struct resource *res;
+ dev = dev_find_slot(1, PCI_DEVFN(0x1e,0));
+ if (dev) {
+ res = find_resource(dev, PCI_BASE_ADDRESS_0);
+ if (res) {
+ smp_write_ioapic(mc, 3, 0x20, res->base);
+ }
+ }
+ dev = dev_find_slot(1, PCI_DEVFN(0x1c,0));
+ if (dev) {
+ res = find_resource(dev, PCI_BASE_ADDRESS_0);
+ if (res) {
+ smp_write_ioapic(mc, 4, 0x20, res->base);
+ }
+ }
+ dev = dev_find_slot(4, PCI_DEVFN(0x1e,0));
+ if (dev) {
+ res = find_resource(dev, PCI_BASE_ADDRESS_0);
+ if (res) {
+ smp_write_ioapic(mc, 5, 0x20, res->base);
+ }
+ }
+ dev = dev_find_slot(4, PCI_DEVFN(0x1c,0));
+ if (dev) {
+ res = find_resource(dev, PCI_BASE_ADDRESS_0);
+ if (res) {
+ smp_write_ioapic(mc, 8, 0x20, res->base);
+ }
+ }
+ }
+ */
+ /*I/O Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
+ /* IRQ0 8254 Counter 0, MNT0 */
+ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 0, IO_APIC0, 0);
+ /* IRQ1 Keyboard */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 1, IO_APIC0, 1);
+ /* IRQ2 8259 cascade only */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 0, IO_APIC0, 2);
+ /* IRQ3 COM2, Option for PIRQx */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 3, IO_APIC0, 3);
+ /* IRQ4 COM1, Option for PIRQx */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 4, IO_APIC0, 4);
+ /* IRQ5 Option for PIRQx */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 5, IO_APIC0, 5);
+ /* IRQ6 Option for PIRQx */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 6, IO_APIC0, 6);
+ /* IRQ7 OPtion for PIRQx */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 7, IO_APIC0, 7);
+ /* IRQ8# RTC, MNT1 */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE |MP_IRQ_POLARITY_HIGH, bus_isa, 8, IO_APIC0, 8);
+ /* IRQ9 Option for PIRQx, SCI, TCO */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 9, IO_APIC0, 9);
+ /* IRQ10 Option for PIRQx, SCI, TCO */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 12, IO_APIC0, 10);
+ /* IRQ11 Option for PIRQx, SCI, TCO, MMT2 */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 12, IO_APIC0, 11);
+ /* IRQ12 Mouse, Option for PIRQx */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 12, IO_APIC0, 12);
+ /* IRQ13 Floating point interrupt generated off of the processor assertion of FERR# */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 13, IO_APIC0, 13);
+ /* IRQ14 PIRQx Sata primary (legacy mode) */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 14, IO_APIC0, 14);
+ /* IRQ15 PIRQx Sata secondary (legacy mode) */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 15, IO_APIC0, 15);
+
+ /*Local Ints: Type Polarity Trigger Bus ID IRQ APIC ID PIN#*/
+ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 0, MP_APIC_ALL, 0);
+ smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, bus_isa, 0, MP_APIC_ALL, 1);
+
+ /* Internal PCI device for i3100 */
+
+ /* EDMA
+ */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_chipset, PCI_IRQ(1, INT_A), IO_APIC0, PIRQ_A);
+
+ /* PCIe Port A
+ */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_chipset, PCI_IRQ(2, INT_A), IO_APIC0, PIRQ_A);
+
+ /* PCIe Port A1
+ */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_chipset, PCI_IRQ(3, INT_A), IO_APIC0, PIRQ_A);
+
+ /* PCIe Port B
+ */
+ for(i = 0; i < 4; i++) {
+ pin = (readl(rcba + RCBA_D28IP) >> (i * 4)) & 0x0F;
+ if(pin > 0) {
+ pin -= 1;
+ route = PIRQ_A + ((readw(rcba + RCBA_D28IR) >> (pin * 4)) & 0x07);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_chipset, PCI_IRQ(28, pin), IO_APIC0, route);
+ }
+ }
+
+ /* USB 1.1 : device 29, function 0, 1
+ */
+ for(i = 0; i < 2; i++) {
+ pin = (readl(rcba + RCBA_D29IP) >> (i * 4)) & 0x0F;
+ if(pin > 0) {
+ pin -= 1;
+ route = PIRQ_A + ((readw(rcba + RCBA_D29IR) >> (pin * 4)) & 0x07);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_chipset, PCI_IRQ(29, pin), IO_APIC0, route);
+ }
+ }
+
+ /* USB 2.0 : device 29, function 7
+ */
+ pin = (readl(rcba + RCBA_D29IP) >> (7 * 4)) & 0x0F;
+ if(pin > 0) {
+ pin -= 1;
+ route = PIRQ_A + ((readw(rcba + RCBA_D29IR) >> (pin * 4)) & 0x07);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_chipset, PCI_IRQ(29, pin), IO_APIC0, route);
+ }
+
+ /* SATA : device 31 function 2
+ SMBus : device 31 function 3
+ Performance counters : device 31 function 4
+ */
+ for(i = 2; i < 5; i++) {
+ pin = (readl(rcba + RCBA_D31IP) >> (i * 4)) & 0x0F;
+ if(pin > 0) {
+ pin -= 1;
+ route = PIRQ_A + ((readw(rcba + RCBA_D31IR) >> (pin * 4)) & 0x07);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_chipset, PCI_IRQ(31, pin), IO_APIC0, route);
+ }
+ }
+
+ /* SLOTS */
+
+ /* PCIe 4x slot A
+ */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcie_a, PCI_IRQ(0, INT_A), IO_APIC0, PIRQ_A);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcie_a, PCI_IRQ(0, INT_B), IO_APIC0, PIRQ_B);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcie_a, PCI_IRQ(0, INT_C), IO_APIC0, PIRQ_C);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcie_a, PCI_IRQ(0, INT_D), IO_APIC0, PIRQ_D);
+
+ /* PCIe 4x slot A1
+ */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcie_a1, PCI_IRQ(0, INT_A), IO_APIC0, PIRQ_A);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcie_a1, PCI_IRQ(0, INT_B), IO_APIC0, PIRQ_B);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcie_a1, PCI_IRQ(0, INT_C), IO_APIC0, PIRQ_C);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcie_a1, PCI_IRQ(0, INT_D), IO_APIC0, PIRQ_D);
+
+ /* PCIe 4x slot B
+ */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcie_b, PCI_IRQ(0, INT_A), IO_APIC0, PIRQ_A);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcie_b, PCI_IRQ(0, INT_B), IO_APIC0, PIRQ_B);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcie_b, PCI_IRQ(0, INT_C), IO_APIC0, PIRQ_C);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pcie_b, PCI_IRQ(0, INT_D), IO_APIC0, PIRQ_D);
+
+ /* PCI slot
+ */
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pci, PCI_IRQ(0, INT_A), IO_APIC0, PIRQ_A);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pci, PCI_IRQ(0, INT_B), IO_APIC0, PIRQ_B);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pci, PCI_IRQ(0, INT_C), IO_APIC0, PIRQ_C);
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, bus_pci, PCI_IRQ(0, INT_D), IO_APIC0, PIRQ_D);
+
+ /* There is no extension information... */
+
+ /* Compute the checksums */
+ mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);
+ mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);
+ printk_debug("Wrote the mp table end at: %p - %p\n",
+ mc, smp_next_mpe_entry(mc));
+ return smp_next_mpe_entry(mc);
+}
+
+unsigned long write_smp_table(unsigned long addr)
+{
+ void *v;
+ v = smp_write_floating_table(addr);
+ return (unsigned long)smp_write_config_table(v);
+}
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2008 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+
+static void power_down_reset_check(void)
+{
+ uint8_t cmos;
+
+ cmos=cmos_read(RTC_BOOT_BYTE)>>4 ;
+ printk_debug("Boot byte = %x\r\n", cmos);
+
+ if((cmos>2)&&(cmos&1)) full_reset();
+}
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2007-2008 coresystems GmbH
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston,
+ * MA 02110-1301 USA
+ */
+
+#include <arch/io.h>
+#include <device/pci_def.h>
+#include <device/pci_ids.h>
+#ifndef __ROMCC__
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ops.h>
+#define PCI_ID(VENDOR_ID, DEVICE_ID) \
+ ((((DEVICE_ID) & 0xFFFF) << 16) | ((VENDOR_ID) & 0xFFFF))
+#define PCI_DEV_INVALID 0
+
+static inline device_t pci_locate_device(unsigned pci_id, device_t from)
+{
+ return dev_find_device(pci_id >> 16, pci_id & 0xffff, from);
+}
+#endif
+
+void soft_reset(void)
+{
+ outb(0x04, 0xcf9);
+}
+
+void hard_reset(void)
+{
+ outb(0x06, 0xcf9);
+}
+
+void full_reset(void)
+{
+ device_t dev;
+ /* Enable power on after power fail... */
+ dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_3100_LPC), 0);
+ if (dev != PCI_DEV_INVALID) {
+ unsigned byte;
+ byte = pci_read_config8(dev, 0xa4);
+ byte &= 0xfe;
+ pci_write_config8(dev, 0xa4, byte);
+ }
+ outb(0x0e, 0xcf9);
+}
+
#define DEVPRES1_D0F1 (1 << 5)
#define DEVPRES1_D8F0 (1 << 1)
#define MSCFG 0XF6
+
+/* DRC */
+#define DRC_NOECC_MODE (0 << 20)
+#define DRC_72BIT_ECC (1 << 20)
{{ 0x00000120, 0x00000000, 0x00000032, 0x00000010}},
/* FSB 167 */
{{ 0x00154320, 0x00000000, 0x00065432, 0x00010000}},
- /* N/A */
- {{ 0xffffffff, 0xffffffff, 0xffffffff, 0xffffffff}},
+ /* FSB 200 DIMM 400 */
+ {{ 0x00000001, 0x00000000, 0x00000001, 0x00000000}},
};
static const u32 dqs_data[] = {
pci_write_config16(ctrl->f0, MCHSCRB, data16);
/* The memory is now setup, use it */
+#if CONFIG_USE_DCACHE_RAM == 0
cache_lbmem(MTRR_TYPE_WRBACK);
+#endif
}
--- /dev/null
+/* Convert to C by yhlu */
+#define MCH_DRC 0x7c
+#define DRC_DONE (1 << 29)
+
+/* If I have already booted once skip a bunch of initialization */
+/* To see if I have already booted I check to see if memory
+ * has been enabled.
+ */
+static int bios_reset_detected(void)
+{
+ uint32_t dword;
+
+ dword = pci_read_config32(PCI_DEV(0, 0, 0), MCH_DRC);
+
+ if( (dword & DRC_DONE) != 0 ) {
+ return 1;
+ }
+
+ return 0;
+}
driver i3100_smbus.o
driver i3100_pci.o
object i3100_reset.o
+object i3100_pciexp_portb.o
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include "i3100.h"
+
+#define RTC_FAILED (1 <<2)
+#define GEN_PMCON_3 0xa4
+
+static void check_cmos_failed(void)
+{
+ u8 byte;
+ byte = pci_read_config8(PCI_DEV(0, 0x1f, 0), GEN_PMCON_3);
+ if (byte & RTC_FAILED) {
+ // clear bit 1 and bit 2
+ byte = cmos_read(RTC_BOOT_BYTE);
+ byte &= 0x0c;
+ byte |= CONFIG_MAX_REBOOT_CNT << 4;
+ cmos_write(byte, RTC_BOOT_BYTE);
+ }
+}
#define GPIO_BAR 0x48
#define RCBA 0xf0
+#define SERIRQ_CNTL 0x64
+
+#define GEN_PMCON_1 0xA0
+#define GEN_PMCON_2 0xA2
+#define GEN_PMCON_3 0xA4
+
#define NMI_OFF 0
#define MAINBOARD_POWER_OFF 0
#define MAINBOARD_POWER_ON 1
-#ifndef MAINBOARD_POWER_ON_AFTER_FAIL
-#define MAINBOARD_POWER_ON_AFTER_FAIL MAINBOARD_POWER_ON
+#ifndef CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL
+#define CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL MAINBOARD_POWER_ON
#endif
#define ALL (0xff << 24)
}
/* Put the APIC in virtual wire mode */
- l[0] = 0x10;
+ l[0] = 0x12;
l[4] = ENABLED | TRIGGER_EDGE | POLARITY_HIGH | PHYSICAL_DEST | ExtINT;
}
-#define SERIRQ_CNTL 0x64
static void i3100_enable_serial_irqs(device_t dev)
{
/* set packet length and toggle silent mode bit */
}
}
+static void i3100_power_options(device_t dev) {
+ u8 reg8;
+ u16 reg16;
+ int pwr_on = CONFIG_MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
+ int nmi_option;
+
+ /* Which state do we want to goto after g3 (power restored)?
+ * 0 == S0 Full On
+ * 1 == S5 Soft Off
+ */
+ get_option(&pwr_on, "power_on_after_fail");
+ reg8 = pci_read_config8(dev, GEN_PMCON_3);
+ reg8 &= 0xfe;
+ if (pwr_on) {
+ reg8 &= ~1;
+ } else {
+ reg8 |= 1;
+ }
+ /* avoid #S4 assertions */
+ reg8 |= (3 << 4);
+ /* minimum asssertion is 1 to 2 RTCCLK */
+ reg8 &= ~(1 << 3);
+ pci_write_config8(dev, GEN_PMCON_3, reg8);
+ printk_info("set power %s after power fail\n", pwr_on ? "on" : "off");
+
+ /* Set up NMI on errors. */
+ reg8 = inb(0x61);
+ /* Higher Nibble must be 0 */
+ reg8 &= 0x0f;
+ /* IOCHK# NMI Enable */
+ reg8 &= ~(1 << 3);
+ /* PCI SERR# Enable */
+ // reg8 &= ~(1 << 2);
+ /* PCI SERR# Disable for now */
+ reg8 |= (1 << 2);
+ outb(reg8, 0x61);
+
+ reg8 = inb(0x70);
+ nmi_option = NMI_OFF;
+ get_option(&nmi_option, "nmi");
+ if (nmi_option) {
+ /* Set NMI. */
+ printk_info ("NMI sources enabled.\n");
+ reg8 &= ~(1 << 7);
+ } else {
+ /* Can't mask NMI from PCI-E and NMI_NOW */
+ printk_info ("NMI sources disabled.\n");
+ reg8 |= ( 1 << 7);
+ }
+ outb(reg8, 0x70);
+
+ // Enable CPU_SLP# and Intel Speedstep, set SMI# rate down
+ reg16 = pci_read_config16(dev, GEN_PMCON_1);
+ reg16 &= ~((3 << 0) | (1 << 10));
+ reg16 |= (1 << 3) | (1 << 5);
+ /* CLKRUN_EN */
+ // reg16 |= (1 << 2);
+ pci_write_config16(dev, GEN_PMCON_1, reg16);
+
+ // Set the board's GPI routing.
+ // i82801gx_gpi_routing(dev);
+}
static void i3100_gpio_init(device_t dev)
{
static void lpc_init(struct device *dev)
{
- u8 byte;
- int pwr_on = MAINBOARD_POWER_ON_AFTER_FAIL;
-
setup_ioapic(dev);
/* Decode 0xffc00000 - 0xffffffff to fwh idsel 0 */
i3100_enable_serial_irqs(dev);
- get_option(&pwr_on, "power_on_after_fail");
- byte = pci_read_config8(dev, 0xa4);
- byte &= 0xfe;
- if (!pwr_on) {
- byte |= 1;
- }
- pci_write_config8(dev, 0xa4, byte);
- printk_info("set power %s after power fail\n", pwr_on ? "on" : "off");
-
/* Set up the PIRQ */
i3100_pirq_init(dev);
+ /* Setup power options */
+ i3100_power_options(dev);
+
/* Set the state of the gpio lines */
i3100_gpio_init(dev);
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2008 Arastra, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License version 2 as
+ * published by the Free Software Foundation.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ *
+ */
+
+/* This code is based on src/northbridge/intel/e7520/pciexp_porta.c */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <device/pci_ops.h>
+#include <device/pciexp.h>
+#include <arch/io.h>
+#include "chip.h"
+#include <part/hard_reset.h>
+
+#define PCIE_LCTL 0x50
+#define PCIE_LSTS 0x52
+
+typedef struct northbridge_intel_i3100_config config_t;
+
+static void pcie_init(struct device *dev)
+{
+}
+
+static unsigned int pcie_scan_bridge(struct device *dev, unsigned int max)
+{
+ u16 val;
+ u16 ctl;
+ int flag = 0;
+ do {
+ val = pci_read_config16(dev, PCIE_LSTS);
+ printk_debug("pcie portb link status: %02x\n", val);
+ if ((val & (1<<10)) && (!flag)) { /* training error */
+ ctl = pci_read_config16(dev, PCIE_LCTL);
+ pci_write_config16(dev, PCIE_LCTL, (ctl | (1<<5)));
+ val = pci_read_config16(dev, PCIE_LSTS);
+ printk_debug("pcie portb reset link status: %02x\n", val);
+ flag=1;
+ hard_reset();
+ }
+ } while (val & (3<<10));
+ return pciexp_scan_bridge(dev, max);
+}
+
+static struct device_operations pcie_ops = {
+ .read_resources = pci_bus_read_resources,
+ .set_resources = pci_dev_set_resources,
+ .enable_resources = pci_bus_enable_resources,
+ .init = pcie_init,
+ .scan_bus = pcie_scan_bridge,
+ .reset_bus = pci_bus_reset,
+ .ops_pci = 0,
+};
+
+static struct pci_driver pci_driver_0 __pci_driver = {
+ .ops = &pcie_ops,
+ .vendor = PCI_VENDOR_ID_INTEL,
+ .device = PCI_DEVICE_ID_INTEL_3100_PCIE_PB0,
+};
+
+static struct pci_driver pci_driver_1 __pci_driver = {
+ .ops = &pcie_ops,
+ .vendor = PCI_VENDOR_ID_INTEL,
+ .device = PCI_DEVICE_ID_INTEL_3100_PCIE_PB1,
+};
+
+static struct pci_driver pci_driver_2 __pci_driver = {
+ .ops = &pcie_ops,
+ .vendor = PCI_VENDOR_ID_INTEL,
+ .device = PCI_DEVICE_ID_INTEL_3100_PCIE_PB2,
+};
+
+static struct pci_driver pci_driver_3 __pci_driver = {
+ .ops = &pcie_ops,
+ .vendor = PCI_VENDOR_ID_INTEL,
+ .device = PCI_DEVICE_ID_INTEL_3100_PCIE_PB3,
+};
#include <device/pci_ops.h>
#include "i3100.h"
+#define SATA_CMD 0x04
+#define SATA_PI 0x09
+#define SATA_PTIM 0x40
+#define SATA_STIM 0x42
+#define SATA_D1TIM 0x44
+#define SATA_SYNCC 0x48
+#define SATA_SYNCTIM 0x4A
+#define SATA_IIOC 0x54
+#define SATA_MAP 0x90
+#define SATA_PCS 0x91
+#define SATA_ACR0 0xA8
+#define SATA_ACR1 0xAC
+#define SATA_ATC 0xC0
+#define SATA_ATS 0xC4
+#define SATA_SP 0xD0
+
+typedef struct southbridge_intel_i3100_config config_t;
+
static void sata_init(struct device *dev)
{
- /* Enable SATA devices */
-
- printk_debug("SATA init\n");
- /* SATA configuration */
- pci_write_config8(dev, 0x04, 0x07);
- pci_write_config8(dev, 0x09, 0x8f);
-
- /* Set timings */
- pci_write_config16(dev, 0x40, 0x0a307);
- pci_write_config16(dev, 0x42, 0x0a307);
+ u8 ahci;
- /* Sync DMA */
- pci_write_config16(dev, 0x48, 0x000f);
- pci_write_config16(dev, 0x4a, 0x1111);
-
- /* Fast ATA */
- pci_write_config16(dev, 0x54, 0x1000);
-
- /* Select IDE mode */
- pci_write_config8(dev, 0x90, 0x00);
-
- /* Enable ports 0-3 */
- pci_write_config8(dev, 0x92, 0x0f);
+ /* Get the chip configuration */
+ ahci = (pci_read_config8(dev, SATA_MAP) >> 6) & 0x03;
+ /* Enable SATA devices */
+ printk_info("SATA init (%s mode)\n", ahci ? "AHCI" : "Legacy");
+
+ if(ahci) {
+ /* AHCI mode */
+ pci_write_config8(dev, SATA_MAP, (1 << 6) | (0 << 0));
+
+ /* Enable ports */
+ pci_write_config8(dev, SATA_PCS, 0x03);
+ pci_write_config8(dev, SATA_PCS + 1, 0x0F);
+
+ /* Setup timings */
+ pci_write_config16(dev, SATA_PTIM, 0x8000);
+ pci_write_config16(dev, SATA_STIM, 0x8000);
+
+ /* Synchronous DMA */
+ pci_write_config8(dev, SATA_SYNCC, 0);
+ pci_write_config16(dev, SATA_SYNCTIM, 0);
+
+ /* IDE I/O configuration */
+ pci_write_config32(dev, SATA_IIOC, 0);
+
+ } else {
+ /* SATA configuration */
+ pci_write_config8(dev, SATA_CMD, 0x07);
+ pci_write_config8(dev, SATA_PI, 0x8f);
+
+ /* Set timings */
+ pci_write_config16(dev, SATA_PTIM, 0x0a307);
+ pci_write_config16(dev, SATA_STIM, 0x0a307);
+
+ /* Sync DMA */
+ pci_write_config8(dev, SATA_SYNCC, 0x0f);
+ pci_write_config16(dev, SATA_SYNCTIM, 0x1111);
+
+ /* Fast ATA */
+ pci_write_config16(dev, SATA_IIOC, 0x1000);
+
+ /* Select IDE mode */
+ pci_write_config8(dev, SATA_MAP, 0x00);
+
+ /* Enable ports 0-3 */
+ pci_write_config8(dev, SATA_PCS + 1, 0x0f);
+
+ }
printk_debug("SATA Enabled\n");
}
#include "chip.h"
/* The following Super I/O chips are currently supported by this driver: */
+#define LPC47M172 0x14
#define FDC37B80X 0x42 /* Same ID: FDC37M70X (a.k.a. FDC37M707) */
#define FDC37B78X 0x44
#define FDC37B72X 0x4c
/* Register defines */
#define DEVICE_ID_REG 0x20 /* Device ID register */
#define DEVICE_REV_REG 0x21 /* Device revision register */
+#define DEVICE_TEST7_REG 0x29 /* Device test 7 register */
/* Static variables for the Super I/O device ID and revision. */
static int first_time = 1;
int devs[MAX_LOGICAL_DEVICES];
} logical_device_table[] = {
// Chip FDC PP SP1 SP2 RTC KBC AUX XBUS HWM GAME PME MPU RT ACPI SMB
+ {LPC47M172,{0, 3, 4, 2, -1, 7, -1, -1, -1, -1, -1, -1, 10, -1, -1}},
{FDC37B80X,{0, 3, 4, 5, -1, 7, 8, -1, -1, -1, -1, -1, -1, -1, -1}},
{FDC37B78X,{0, 3, 4, 5, 6, 7, 8, -1, -1, -1, -1, -1, -1, 10, -1}},
{FDC37B72X,{0, 3, 4, 5, -1, 7, 8, -1, -1, -1, -1, -1, -1, 10, -1}},
{
int i, j, fn;
int tmp[MAX_LOGICAL_DEVICES];
+ uint8_t test7;
if (first_time) {
/* Read the device ID and revision of the Super I/O chip. */
printk_info("Found SMSC Super I/O (ID=0x%02x, rev=0x%02x)\n",
superio_id, superio_rev);
first_time = 0;
+
+ if(superio_id == LPC47M172) {
+ /* Do not use the default logical device number
+ * but instead the standard smsc registers set
+ */
+
+ /* TEST7 configuration register (0x29)
+ * bit 0 : LD_NUM (0 = new, 1 = std smsc)
+ */
+ test7 = pnp_read_config(dev, DEVICE_TEST7_REG);
+ test7 |= 1;
+ pnp_write_config(dev, DEVICE_TEST7_REG, test7);
+ }
}
/* Find the correct Super I/O. */
--- /dev/null
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2008 Arastra, Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License version 2 as
+## published by the Free Software Foundation.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+target eagleheights
+mainboard intel/eagleheights
+
+## CONFIG_ROM_SIZE is the total number of bytes allocated for coreboot use
+## (normal AND fallback images and payloads).
+option CONFIG_ROM_SIZE = 1024 * 1024
+
+romimage "fallback"
+ option CONFIG_USE_FALLBACK_IMAGE=1
+ payload ../payload.elf
+end
+
+buildrom ./coreboot.rom CONFIG_ROM_SIZE "fallback"
projects / coreboot.git / commitdiff