Add w83627hf_set_clksel_48() function which sets CLKSEL to 48MHz.

The Win Ent platforms are using the Winbond W83627HG part, but this part does
not appear to enable 48MHz clock by default as claimed in the datasheet.

Signed-off-by: Anish K Patel <anishp@win-ent.com>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5125 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

diff --git a/src/superio/winbond/w83627hf/w83627hf_early_serial.c b/src/superio/winbond/w83627hf/w83627hf_early_serial.c
index cc0bf1cfe4e75415a0822e9cb2947c943a6c7480..e4b49d1eeef87e620513e4b97bbbd86a2a7847cf 100644 (file)
--- a/src/superio/winbond/w83627hf/w83627hf_early_serial.c
+++ b/src/superio/winbond/w83627hf/w83627hf_early_serial.c
@@ -45,3 +45,13 @@ static void w83627hf_enable_serial(device_t dev, unsigned iobase)
        pnp_set_enable(dev, 1);
        pnp_exit_ext_func_mode(dev);
 }
+
+static void w83627hf_set_clksel_48(device_t dev)
+{
+       unsigned port = dev >> 8;
+       pnp_enter_ext_func_mode(dev);
+       outb(0x24, port);
+       /* Set CLKSEL (clock input on pin 1) to 48MHz. */
+       outb(inb(port + 1) | (1 << 6), port + 1);
+       pnp_exit_ext_func_mode(dev);
+}