This patch fixes the decoding of the IO address range 0x0820->0x0827 into the

LPC device of the MCP55 southbridge, thus enabling flashrom access to the SPI
interface of the IT8716 SIO chip.
 Changes :
  1) - increase MAX_RESOURCES to 24 in device.h -> this was needed because some
functions of a PNP device can have more than 12 resources (ex the GPIO function
of IT8716f), in which case one could have an "array overflow" inside the device
structure (yes gcc is stupid!..) and ultimately a disaster (fool pointer at
device init time..)
  2) - define resource masks for the GPIO function in
src/superio/ite/it8716f/superio.c -> this is needed because otherwise the IO
ranges which are set into the LPC bridge of the SB are very strange (f.ex.:
0x800->0x7ff and so on..). Problem: the PNP_IO0 resource is not defined for the
GPIO function, thus we have to define a "fake" mask "{0,0}" to avoid mismatching
by the init code
  3) - enable the flash SPI interface into
src/mainboard/gigabyte/m57sli/Config.lb (by enabling the corresponding resource
into the GPIO function). I know that this is problematic because not all m57sli
boards are SPI, but .. do anyone have a better idea how to handle this?..

Signed-off-by: Florentin Demetrescu <echelon@free.fr>
I (Ward) have verified your patch on a rev2 of this board (it works!) as well
as on a rev1 (plcc). It does not affect flashing on rev1 nor have any averse
side effects that I noticed, so I think this patch should go in.

Acked-by: Ward Vandewege <ward@gnu.org>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006@gmx.net>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3088 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

diff --git a/src/include/device/device.h b/src/include/device/device.h
index b922e2687e457f2b8c1a58871d52bce0aae22639..09d163cf595eea7cd4fae3d05b2980671751107e 100644 (file)
--- a/src/include/device/device.h
+++ b/src/include/device/device.h
@@ -55,7 +55,7 @@ struct bus {
        unsigned        disable_relaxed_ordering : 1;
 };
 
-#define MAX_RESOURCES 12 
+#define MAX_RESOURCES 24 
 #define MAX_LINKS    8 
 /*
  * There is one device structure for each slot-number/function-number

diff --git a/src/mainboard/gigabyte/m57sli/Config.lb b/src/mainboard/gigabyte/m57sli/Config.lb
index 88eb4d3d1f0785c9ffd244222e69ca1aae11094e..5f34c9eeb593f677df73c7d6f38104daa5fff8ca 100644 (file)
--- a/src/mainboard/gigabyte/m57sli/Config.lb
+++ b/src/mainboard/gigabyte/m57sli/Config.lb
@@ -290,7 +290,7 @@ chip northbridge/amd/amdk8/root_complex
                                # Simple I/O base
                                                                io 0x62 = 0x800
                                # Serial Flash I/O (SPI only)
-                                                               #io 0x64 = 0x820 
+                                                               io 0x64 = 0x820
                                # watch dog force timeout (parallel flash only)
                                                                #irq 0x71 = 0x1
                                                                # No WDT interrupt

diff --git a/src/superio/ite/it8716f/superio.c b/src/superio/ite/it8716f/superio.c
index f310511d95223df9fa25cdf553ab759e41d5a2f8..be78639b870fed308a951e0589247c6cc11ed4ce 100644 (file)
--- a/src/superio/ite/it8716f/superio.c
+++ b/src/superio/ite/it8716f/superio.c
@@ -152,7 +152,7 @@ static struct pnp_info pnp_dev_info[] = {
        {&ops, IT8716F_KBCK, PNP_IO0 | PNP_IO1 | PNP_IRQ0, {0x7ff, 0},
         {0x7ff, 0x4},},
        {&ops, IT8716F_KBCM, PNP_IRQ0,},
-       {&ops, IT8716F_GPIO,},
+       {&ops, IT8716F_GPIO, PNP_IO1 | PNP_IO2, {0, 0}, {0x7f8, 0}, {0x7f8, 0},},
        {&ops, IT8716F_MIDI, PNP_IO0 | PNP_IRQ0, {0x7fe, 0x4},},
        {&ops, IT8716F_GAME, PNP_IO0, {0x7ff, 0},},
        {&ops, IT8716F_IR,},