jmp *%esp
-/* originally this macro was from STPC BIOS */
-#define intel_chip_post_macro(value) \
- movb $value, %al ; \
+#define post_code(value) \
+ movb $value, %al; \
outb %al, $0x80
-
#endif /* ROM_INTEL_H */
.section ".rom.data", "a", @progbits
.section ".rom.text", "ax", @progbits
- intel_chip_post_macro(0x01) /* delay for chipsets */
+ post_code(0x01) /* delay for chipsets */
/* Save the BIST result. */
movl %eax, %ebp
- intel_chip_post_macro(0x01)
+ post_code(0x01)
movw $ROM_DATA_SEG, %ax
movw %ax, %ds
#include <arch/intel.h>
#include <console/loglevel.h>
+#ifndef ASM_CONSOLE_LOGLEVEL
+#define ASM_CONSOLE_LOGLEVEL CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
+#endif
+
/*
* This is the entry code the code in .reset section
* jumps to this address.
.section ".rom.data", "a", @progbits
.section ".rom.text", "ax", @progbits
- intel_chip_post_macro(0x01) /* delay for chipsets */
+ post_code(0x01) /* delay for chipsets */
#include "crt0_includes.h"
* isn\'t really that big we just copy/clear using bytes, not
* double words.
*/
- intel_chip_post_macro(0x11) /* post 11 */
+ post_code(0x11) /* post 11 */
cld /* clear direction flag */
call cbfs_and_run_core
.Lhlt:
- intel_chip_post_macro(0xee) /* post fe */
+ post_code(0xee) /* post fe */
hlt
jmp .Lhlt
movl %eax, %fs
movl %eax, %gs
- intel_chip_post_macro(0x13) /* post 13 */
+ post_code(0x13) /* post 13 */
/** clear stack */
cld
* bss is cleared. Now we call the main routine and
* let it do the rest.
*/
- intel_chip_post_macro(0xfe) /* post fe */
+ post_code(0xfe) /* post fe */
/* Restore the stack location */
movl %ebp, %esp
call hardwaremain
/*NOTREACHED*/
.Lhlt:
- intel_chip_post_macro(0xee) /* post ee */
+ post_code(0xee) /* post ee */
hlt
jmp .Lhlt
#include <console/console.h>
#include <console/vtxprintf.h>
-#include <console/loglevel.h>
#include <uart8250.h>
-/* Using a global varible can cause problems when we reset the stack
- * from cache as ram to ram. If we make this a define USE_SHARED_STACK
- * we could use the same code on all architectures.
- */
-#if 0
-int console_loglevel = CONFIG_DEFAULT_CONSOLE_LOGLEVEL;
-#else
-#define console_loglevel CONFIG_DEFAULT_CONSOLE_LOGLEVEL
-#endif
-
static void console_tx_byte(unsigned char byte)
{
if (byte == '\n')
#define CONSOLE_SPEW_TX_STRING(string) __CONSOLE_TX_STRING(string)
#define CONSOLE_SPEW_INLINE_TX_STRING(string) __CONSOLE_INLINE_TX_STRING(string)
-#if 0
-#if ASM_CONSOLE_LOGLEVEL <= BIOS_EMERG
-#undef CONSOLE_EMERG_TX_CHAR
-#undef CONSOLE_EMERG_INLINE_TX_CHAR
-#undef CONSOLE_EMERG_TX_HEX8
-#undef CONSOLE_EMERG_INLINE_TX_HEX8
-#undef CONSOLE_EMERG_TX_HEX32
-#undef CONSOLE_EMERG_INLINE_TX_HEX32
-#undef CONSOLE_EMERG_TX_STRING
-#undef CONSOLE_EMERG_INLINE_TX_STRING
-#define CONSOLE_EMERG_TX_CHAR(byte)
-#define CONSOLE_EMERG_INLINE_TX_CHAR(byte)
-#define CONSOLE_EMERG_TX_HEX8(byte)
-#define CONSOLE_EMERG_INLINE_TX_HEX8(byte)
-#define CONSOLE_EMERG_TX_HEX32(lword)
-#define CONSOLE_EMERG_INLINE_TX_HEX32(lword)
-#define CONSOLE_EMERG_TX_STRING(string)
-#define CONSOLE_EMERG_INLINE_TX_STRING(string)
-#endif
-
-
-#if ASM_CONSOLE_LOGLEVEL <= BIOS_ALERT
-#undef CONSOLE_ALERT_TX_CHAR
-#undef CONSOLE_ALERT_INLINE_TX_CHAR
-#undef CONSOLE_ALERT_TX_HEX8
-#undef CONSOLE_ALERT_INLINE_TX_HEX8
-#undef CONSOLE_ALERT_TX_HEX32
-#undef CONSOLE_ALERT_INLINE_TX_HEX32
-#undef CONSOLE_ALERT_TX_STRING
-#undef CONSOLE_ALERT_INLINE_TX_STRING
-#define CONSOLE_ALERT_TX_CHAR(byte)
-#define CONSOLE_ALERT_INLINE_TX_CHAR(byte)
-#define CONSOLE_ALERT_TX_HEX8(byte)
-#define CONSOLE_ALERT_INLINE_TX_HEX8(byte)
-#define CONSOLE_ALERT_TX_HEX32(lword)
-#define CONSOLE_ALERT_INLINE_TX_HEX32(lword)
-#define CONSOLE_ALERT_TX_STRING(string)
-#define CONSOLE_ALERT_INLINE_TX_STRING(string)
-#endif
-
-#if ASM_CONSOLE_LOGLEVEL <= BIOS_CRIT
-#undef CONSOLE_CRIT_TX_CHAR
-#undef CONSOLE_CRIT_INLINE_TX_CHAR
-#undef CONSOLE_CRIT_TX_HEX8
-#undef CONSOLE_CRIT_INLINE_TX_HEX8
-#undef CONSOLE_CRIT_TX_HEX32
-#undef CONSOLE_CRIT_INLINE_TX_HEX32
-#undef CONSOLE_CRIT_TX_STRING
-#undef CONSOLE_CRIT_INLINE_TX_STRING
-#define CONSOLE_CRIT_TX_CHAR(byte)
-#define CONSOLE_CRIT_INLINE_TX_CHAR(byte)
-#define CONSOLE_CRIT_TX_HEX8(byte)
-#define CONSOLE_CRIT_INLINE_TX_HEX8(byte)
-#define CONSOLE_CRIT_TX_HEX32(lword)
-#define CONSOLE_CRIT_INLINE_TX_HEX32(lword)
-#define CONSOLE_CRIT_TX_STRING(string)
-#define CONSOLE_CRIT_INLINE_TX_STRING(string)
-#endif
-
-#if ASM_CONSOLE_LOGLEVEL <= BIOS_ERR
-#undef CONSOLE_ERR_TX_CHAR
-#undef CONSOLE_ERR_INLINE_TX_CHAR
-#undef CONSOLE_ERR_TX_HEX8
-#undef CONSOLE_ERR_INLINE_TX_HEX8
-#undef CONSOLE_ERR_TX_HEX32
-#undef CONSOLE_ERR_INLINE_TX_HEX32
-#undef CONSOLE_ERR_TX_STRING
-#undef CONSOLE_ERR_INLINE_TX_STRING
-#define CONSOLE_ERR_TX_CHAR(byte)
-#define CONSOLE_ERR_INLINE_TX_CHAR(byte)
-#define CONSOLE_ERR_TX_HEX8(byte)
-#define CONSOLE_ERR_INLINE_TX_HEX8(byte)
-#define CONSOLE_ERR_TX_HEX32(lword)
-#define CONSOLE_ERR_INLINE_TX_HEX32(lword)
-#define CONSOLE_ERR_TX_STRING(string)
-#define CONSOLE_ERR_INLINE_TX_STRING(string)
-#endif
-
-#if ASM_CONSOLE_LOGLEVEL <= BIOS_WARNING
-#undef CONSOLE_WARNING_TX_CHAR
-#undef CONSOLE_WARNING_INLINE_TX_CHAR
-#undef CONSOLE_WARNING_TX_HEX8
-#undef CONSOLE_WARNING_INLINE_TX_HEX8
-#undef CONSOLE_WARNING_TX_HEX32
-#undef CONSOLE_WARNING_INLINE_TX_HEX32
-#undef CONSOLE_WARNING_TX_STRING
-#undef CONSOLE_WARNING_INLINE_TX_STRING
-#define CONSOLE_WARNING_TX_CHAR(byte)
-#define CONSOLE_WARNING_INLINE_TX_CHAR(byte)
-#define CONSOLE_WARNING_TX_HEX8(byte)
-#define CONSOLE_WARNING_INLINE_TX_HEX8(byte)
-#define CONSOLE_WARNING_TX_HEX32(lword)
-#define CONSOLE_WARNING_INLINE_TX_HEX32(lword)
-#define CONSOLE_WARNING_TX_STRING(string)
-#define CONSOLE_WARNING_INLINE_TX_STRING(string)
-#endif
-
-#if ASM_CONSOLE_LOGLEVEL <= BIOS_NOTICE
-#undef CONSOLE_NOTICE_TX_CHAR
-#undef CONSOLE_NOTICE_INLINE_TX_CHAR
-#undef CONSOLE_NOTICE_TX_HEX8
-#undef CONSOLE_NOTICE_INLINE_TX_HEX8
-#undef CONSOLE_NOTICE_TX_HEX32
-#undef CONSOLE_NOTICE_INLINE_TX_HEX32
-#undef CONSOLE_NOTICE_TX_STRING
-#undef CONSOLE_NOTICE_INLINE_TX_STRING
-#define CONSOLE_NOTICE_TX_CHAR(byte)
-#define CONSOLE_NOTICE_INLINE_TX_CHAR(byte)
-#define CONSOLE_NOTICE_TX_HEX8(byte)
-#define CONSOLE_NOTICE_INLINE_TX_HEX8(byte)
-#define CONSOLE_NOTICE_TX_HEX32(lword)
-#define CONSOLE_NOTICE_INLINE_TX_HEX32(lword)
-#define CONSOLE_NOTICE_TX_STRING(string)
-#define CONSOLE_NOTICE_INLINE_TX_STRING(string)
-#endif
-
-#if ASM_CONSOLE_LOGLEVEL <= BIOS_INFO
-#undef CONSOLE_INFO_TX_CHAR
-#undef CONSOLE_INFO_INLINE_TX_CHAR
-#undef CONSOLE_INFO_TX_HEX8
-#undef CONSOLE_INFO_INLINE_TX_HEX8
-#undef CONSOLE_INFO_TX_HEX32
-#undef CONSOLE_INFO_INLINE_TX_HEX32
-#undef CONSOLE_INFO_TX_STRING
-#undef CONSOLE_INFO_INLINE_TX_STRING
-#define CONSOLE_INFO_TX_CHAR(byte)
-#define CONSOLE_INFO_INLINE_TX_CHAR(byte)
-#define CONSOLE_INFO_TX_HEX8(byte)
-#define CONSOLE_INFO_INLINE_TX_HEX8(byte)
-#define CONSOLE_INFO_TX_HEX32(lword)
-#define CONSOLE_INFO_INLINE_TX_HEX32(lword)
-#define CONSOLE_INFO_TX_STRING(string)
-#define CONSOLE_INFO_INLINE_TX_STRING(string)
-#endif
-
-#if ASM_CONSOLE_LOGLEVEL <= BIOS_DEBUG
-#undef CONSOLE_DEBUG_TX_CHAR
-#undef CONSOLE_DEBUG_INLINE_TX_CHAR
-#undef CONSOLE_DEBUG_TX_HEX8
-#undef CONSOLE_DEBUG_INLINE_TX_HEX8
-#undef CONSOLE_DEBUG_TX_HEX32
-#undef CONSOLE_DEBUG_INLINE_TX_HEX32
-#undef CONSOLE_DEBUG_TX_STRING
-#undef CONSOLE_DEBUG_INLINE_TX_STRING
-#define CONSOLE_DEBUG_TX_CHAR(byte)
-#define CONSOLE_DEBUG_INLINE_TX_CHAR(byte)
-#define CONSOLE_DEBUG_TX_HEX8(byte)
-#define CONSOLE_DEBUG_INLINE_TX_HEX8(byte)
-#define CONSOLE_DEBUG_TX_HEX32(lword)
-#define CONSOLE_DEBUG_INLINE_TX_HEX32(lword)
-#define CONSOLE_DEBUG_TX_STRING(string)
-#define CONSOLE_DEBUG_INLINE_TX_STRING(string)
-#endif
-
-#if ASM_CONSOLE_LOGLEVEL <= BIOS_SPEW
-#undef CONSOLE_SPEW_TX_CHAR
-#undef CONSOLE_SPEW_INLINE_TX_CHAR
-#undef CONSOLE_SPEW_TX_HEX8
-#undef CONSOLE_SPEW_INLINE_TX_HEX8
-#undef CONSOLE_SPEW_TX_HEX32
-#undef CONSOLE_SPEW_INLINE_TX_HEX32
-#undef CONSOLE_SPEW_TX_STRING
-#undef CONSOLE_SPEW_INLINE_TX_STRING
-#define CONSOLE_SPEW_TX_CHAR(byte)
-#define CONSOLE_SPEW_INLINE_TX_CHAR(byte)
-#define CONSOLE_SPEW_TX_HEX8(byte)
-#define CONSOLE_SPEW_INLINE_TX_HEX8(byte)
-#define CONSOLE_SPEW_TX_HEX32(lword)
-#define CONSOLE_SPEW_INLINE_TX_HEX32(lword)
-#define CONSOLE_SPEW_TX_STRING(string)
-#define CONSOLE_SPEW_INLINE_TX_STRING(string)
-#endif
-#endif
-
/* uses: esp, ax, dx */
console_tx_al:
__CONSOLE_INLINE_TX_AL
jmp 3b
5:
CONSOLE_INFO_TX_STRING($rt_toomany)
- intel_chip_post_macro(0xf1)
+ post_code(0xf1)
jmp .Lhlt
6:
3) Optionally, comment out two lines in ramtest.inc:
5:
CONSOLE_INFO_TX_STRING($rt_toomany)
- // intel_chip_post_macro(0xf1)
+ // post_code(0xf1)
// jmp .Lhlt
otherwise, a ramtest failure will hang
/*
* Write POST information
*/
-void post_code(uint8_t value)
+void post_code(u8 value)
{
#if !defined(CONFIG_NO_POST) || CONFIG_NO_POST==0
#if CONFIG_SERIAL_POST==1
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
+#ifndef ASM_CONSOLE_LOGLEVEL
+#define ASM_CONSOLE_LOGLEVEL CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
+#endif
+
#define LX_STACK_BASE CONFIG_DCACHE_RAM_BASE /* this is where the DCache will be mapped and be used as stack, It would be cool if it was the same base as coreboot normal stack */
#define LX_STACK_END LX_STACK_BASE+(CONFIG_DCACHE_RAM_SIZE-1)
* isn\'t really that big we just copy/clear using bytes, not
* double words.
*/
- intel_chip_post_macro(0x11) /* post 11 */
+ post_code(0x11) /* post 11 */
cld /* clear direction flag */
call cbfs_and_run_core
.Lhlt:
- intel_chip_post_macro(0xee) /* post fail ee */
+ post_code(0xee) /* post fail ee */
hlt
jmp .Lhlt
#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
-#define post_code(x) intel_chip_post_macro(x)
#include <cpu/x86/mtrr.h>
#include <cpu/amd/mtrr.h>
#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
-#define post_code(x) intel_chip_post_macro(x)
#include <cpu/x86/mtrr.h>
#include <cpu/amd/mtrr.h>
#define CACHE_AS_RAM_SIZE CONFIG_DCACHE_RAM_SIZE
#define CACHE_AS_RAM_BASE CONFIG_DCACHE_RAM_BASE
-#define post_code(x) intel_chip_post_macro(x)
#include <cpu/x86/mtrr.h>
#include <cpu/amd/mtrr.h>
/* Save the BIST value */
movl %eax, %ebp
- intel_chip_post_macro(0x10) /* post 10 */
+ post_code(0x10) /* post 10 */
movw $ROM_DATA_SEG, %ax
movw %ax, %ds
void console_tx_flush(void);
unsigned char console_rx_byte(void);
int console_tst_byte(void);
-void post_code(uint8_t value);
+void post_code(u8 value);
void __attribute__ ((noreturn)) die(const char *msg);
#if CONFIG_CONSOLE_VGA == 1
void vga_console_init(void);
extern struct console_driver econsole_drivers[];
extern int console_loglevel;
-#endif /* !__PRE_RAM__ */
+#else
+/* __PRE_RAM__ */
+/* Using a global varible can cause problems when we reset the stack
+ * from cache as ram to ram. If we make this a define USE_SHARED_STACK
+ * we could use the same code on all architectures.
+ */
+#define console_loglevel CONFIG_DEFAULT_CONSOLE_LOGLEVEL
+#endif
#ifndef __ROMCC__
int do_printk(int msg_level, const char *fmt, ...) __attribute__((format(printf, 2, 3)));
#define print_debug_hex32(HEX) printk(BIOS_DEBUG, "%08x", (HEX))
#define print_spew_hex32(HEX) printk(BIOS_SPEW, "%08x", (HEX))
#else
+
+
/* __ROMCC__ */
static void __console_tx_byte(unsigned char byte)
{
static void __console_tx_char(int loglevel, unsigned char byte)
{
- if (ASM_CONSOLE_LOGLEVEL >= loglevel) {
+ if (console_loglevel >= loglevel) {
uart_tx_byte(byte);
}
}
static void __console_tx_hex8(int loglevel, unsigned char value)
{
- if (ASM_CONSOLE_LOGLEVEL >= loglevel) {
+ if (console_loglevel >= loglevel) {
__console_tx_nibble((value >> 4U) & 0x0fU);
__console_tx_nibble(value & 0x0fU);
}
static void __console_tx_hex16(int loglevel, unsigned short value)
{
- if (ASM_CONSOLE_LOGLEVEL >= loglevel) {
+ if (console_loglevel >= loglevel) {
__console_tx_nibble((value >> 12U) & 0x0fU);
__console_tx_nibble((value >> 8U) & 0x0fU);
__console_tx_nibble((value >> 4U) & 0x0fU);
static void __console_tx_hex32(int loglevel, unsigned int value)
{
- if (ASM_CONSOLE_LOGLEVEL >= loglevel) {
+ if (console_loglevel >= loglevel) {
__console_tx_nibble((value >> 28U) & 0x0fU);
__console_tx_nibble((value >> 24U) & 0x0fU);
__console_tx_nibble((value >> 20U) & 0x0fU);
static void __console_tx_string(int loglevel, const char *str)
{
- if (ASM_CONSOLE_LOGLEVEL >= loglevel) {
+ if (console_loglevel >= loglevel) {
unsigned char ch;
while((ch = *str++) != '\0') {
if (ch == '\n')
#define LOGLEVEL_H
/* Safe for inclusion in assembly */
-
-#ifndef ASM_CONSOLE_LOGLEVEL
-#define ASM_CONSOLE_LOGLEVEL CONFIG_MAXIMUM_CONSOLE_LOGLEVEL
-#endif
-
#define BIOS_EMERG 0 /* system is unusable */
#define BIOS_ALERT 1 /* action must be taken immediately */
#define BIOS_CRIT 2 /* critical conditions */
#include "southbridge/amd/cs5536/cs5536.h"
#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))
-#define POST_CODE(x) outb(x, 0x80)
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
#include "southbridge/amd/cs5536/cs5536_early_smbus.c"
void cache_as_ram_main(void)
{
- POST_CODE(0x01);
+ post_code(0x01);
static const struct mem_controller memctrl[] = {
{.channel0 = {(0xa << 3) | 0, (0xa << 3) | 1}}
#include "pc80/serial.c"
#include "console/console.c"
-#define post_code(x) outb(x, 0x80)
-
#include <cpu/amd/model_fxx_rev.h>
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c"
#include "pc80/serial.c"
#include "console/console.c"
-#define post_code(x) outb(x, 0x80)
-
#include <cpu/amd/model_fxx_rev.h>
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c"
#include <cpu/amd/geode_post_code.h>
#include "southbridge/amd/cs5536/cs5536.h"
-#define POST_CODE(x) outb(x, 0x80)
-
#include "southbridge/amd/cs5536/cs5536_early_smbus.c"
#include "southbridge/amd/cs5536/cs5536_early_setup.c"
void cache_as_ram_main(void)
{
- POST_CODE(0x01);
+ post_code(0x01);
static const struct mem_controller memctrl[] = {
{.channel0 = {(0xa << 3) | 0, (0xa << 3) | 1}}
#include "pc80/serial.c"
#include "console/console.c"
-#define post_code(x) outb(x, 0x80)
-
#include <cpu/amd/model_fxx_rev.h>
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c"
#include "southbridge/amd/cs5536/cs5536.h"
#include "spd_table.h"
-#define POST_CODE(x) outb(x, 0x80)
-
#include "southbridge/amd/cs5536/cs5536_early_smbus.c"
#include "southbridge/amd/cs5536/cs5536_early_setup.c"
void cache_as_ram_main(void)
{
- POST_CODE(0x01);
+ post_code(0x01);
static const struct mem_controller memctrl[] = {
{.channel0 = {(0xa << 3) | 0, (0xa << 3) | 1}}
#include "console/console.c"
#include "lib/ramtest.c"
-#if 0
-static void post_code(uint8_t value) {
-#if 0
- int i;
- for(i=0;i<0x80000;i++) {
- outb(value, 0x80);
- }
-#endif
-}
-#endif
-
#include <cpu/amd/model_fxx_rev.h>
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "southbridge/broadcom/bcm5785/bcm5785_early_smbus.c"
-#define ASM_CONSOLE_LOGLEVEL 8
#include <stdint.h>
#include <device/pci_def.h>
#include <arch/io.h>
-#define ASM_CONSOLE_LOGLEVEL 8
#include <stdint.h>
#include <device/pci_def.h>
#include <arch/io.h>
#include <cpu/amd/geode_post_code.h>
#include "southbridge/amd/cs5536/cs5536.h"
-#define POST_CODE(x) outb(x, 0x80)
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
#include "southbridge/amd/cs5536/cs5536_early_smbus.c"
void cache_as_ram_main(void)
{
extern void RestartCAR();
- POST_CODE(0x01);
+ post_code(0x01);
static const struct mem_controller memctrl [] = {
{.channel0 = {(0xa<<3)|0, (0xa<<3)|1}}
We use method 1 on Norwich.
*/
- POST_CODE(0x02);
+ post_code(0x02);
print_err("POST 02\n");
__asm__("wbinvd\n");
print_err("Past wbinvd\n");
#include <cpu/amd/geode_post_code.h>
#include "southbridge/amd/cs5536/cs5536.h"
-#define POST_CODE(x) outb(x, 0x80)
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
#include "southbridge/amd/cs5536/cs5536_early_smbus.c"
void cache_as_ram_main(void)
{
- POST_CODE(0x01);
+ post_code(0x01);
static const struct mem_controller memctrl[] = {
{.channel0 = {(0xa << 3) | 0, (0xa << 3) | 1}}
#include "pc80/serial.c"
#include "console/console.c"
-#define post_code(x) outb(x, 0x80)
-
#include <cpu/amd/model_fxx_rev.h>
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c"
#include <cpu/amd/geode_post_code.h>
#include "southbridge/amd/cs5536/cs5536.h"
-#define POST_CODE(x) outb(x, 0x80)
-
#include "southbridge/amd/cs5536/cs5536_early_smbus.c"
#include "southbridge/amd/cs5536/cs5536_early_setup.c"
#include "superio/ite/it8712f/it8712f_early_serial.c"
void cache_as_ram_main(void)
{
- POST_CODE(0x01);
+ post_code(0x01);
static const struct mem_controller memctrl[] = {
{.channel0 = {(0xa << 3) | 0, (0xa << 3) | 1}}
#include <cpu/amd/geode_post_code.h>
#include "southbridge/amd/cs5536/cs5536.h"
-#define POST_CODE(x) outb(x, 0x80)
-
#include "southbridge/amd/cs5536/cs5536_early_smbus.c"
#include "southbridge/amd/cs5536/cs5536_early_setup.c"
#include "superio/ite/it8712f/it8712f_early_serial.c"
void cache_as_ram_main(void)
{
int err;
- POST_CODE(0x01);
+ post_code(0x01);
static const struct mem_controller memctrl[] = {
{.channel0 = {(0xa << 3) | 0, (0xa << 3) | 1}}
#include "pc80/serial.c"
#include "console/console.c"
-#if 0
-static void post_code(uint8_t value) {
-#if 1
- int i;
- for(i=0;i<0x80000;i++) {
- outb(value, 0x80);
- }
-#endif
-}
-#endif
-
#include <cpu/amd/model_fxx_rev.h>
#include "southbridge/broadcom/bcm5785/bcm5785_early_smbus.c"
#include "northbridge/amd/amdk8/raminit.h"
#include "console/console.c"
#include "lib/ramtest.c"
-#if 0
-static void post_code(uint8_t value) {
-#if 1
- int i;
- for(i=0;i<0x80000;i++) {
- outb(value, 0x80);
- }
-#endif
-}
-#endif
-
#include <cpu/amd/model_fxx_rev.h>
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include <cpu/amd/geode_post_code.h>
#include "southbridge/amd/cs5536/cs5536.h"
-#define POST_CODE(x) outb(x, 0x80)
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
/* The ALIX1.C has no SMBus; the setup is hard-wired. */
extern void RestartCAR();
- POST_CODE(0x01);
+ post_code(0x01);
SystemPreInit();
msr_init();
*
* We use method 1 on Norwich and on this board too.
*/
- POST_CODE(0x02);
+ post_code(0x02);
print_err("POST 02\n");
__asm__("wbinvd\n");
print_err("Past wbinvd\n");
#include "pc80/serial.c"
#include "console/console.c"
-#define post_code(x) outb(x, 0x80)
-
#include <cpu/amd/model_fxx_rev.h>
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c"
#include "pc80/serial.c"
#include "console/console.c"
-#define post_code(x) outb(x, 0x80)
-
#include <cpu/amd/model_fxx_rev.h>
#include "northbridge/amd/amdk8/raminit.h"
#include "cpu/amd/model_fxx/apic_timer.c"
* (c) 2006 coresystems GmbH
*/
-#define ASM_CONSOLE_LOGLEVEL 6
#include <stdint.h>
#include <device/pci_def.h>
#include <arch/io.h>
#include "console/console.c"
#include "lib/ramtest.c"
-#if 0
-static void post_code(uint8_t value) {
-#if 1
- int i;
- for(i=0;i<0x80000;i++) {
- outb(value, 0x80);
- }
-#endif
-}
-#endif
-
#include <cpu/amd/model_fxx_rev.h>
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "southbridge/amd/amd8111/amd8111_early_smbus.c"
#include "console/console.c"
#include "lib/ramtest.c"
-#if 0
-static void post_code(uint8_t value) {
-#if 1
- int i;
- for(i=0;i<0x80000;i++) {
- outb(value, 0x80);
- }
-#endif
-}
-#endif
-
#include <cpu/amd/model_fxx_rev.h>
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "console/console.c"
#include "lib/ramtest.c"
-#if 0
-static void post_code(uint8_t value) {
-#if 1
- int i;
- for(i=0;i<0x80000;i++) {
- outb(value, 0x80);
- }
-#endif
-}
-#endif
-
#include <cpu/amd/model_fxx_rev.h>
#include "northbridge/amd/amdk8/incoherent_ht.c"
#include "southbridge/amd/cs5536/cs5536.h"
#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))
-#define POST_CODE(x) outb(x, 0x80)
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
#include "southbridge/amd/cs5536/cs5536_early_smbus.c"
void cache_as_ram_main(void)
{
- POST_CODE(0x01);
+ post_code(0x01);
static const struct mem_controller memctrl[] = {
{.channel0 = {(0xa << 3) | 0, (0xa << 3) | 1}}
#if USE_GOODRICH_VERSION
///////////////////////////////////////////////////////////////////////////////
// Goodrich Version of pll_reset
-#define POST_CODE(x) outb(x, 0x80)
// PLLCHECK_COMPLETED is the "we've already done this" flag
#define PLLCHECK_COMPLETED (1 << RSTPLL_LOWER_SWFLAGS_SHIFT)
// Store PCI33(0)/66(1), SDR(0)/DDR(1), and CRT(0)/TFT(1) in upper esi to get to the
// correct Strap Table.
- POST_CODE(POST_PLL_INIT);
+ post_code(POST_PLL_INIT);
// configure for DDR
msrGlcpSysRstpll.lo &= ~(1 << RSTPPL_LOWER_SDRMODE_SHIFT);
// Use Manual settings
// UseManual:
- POST_CODE(POST_PLL_MANUAL);
+ post_code(POST_PLL_MANUAL);
// DIV settings manually entered.
// ax = VDIV, upper eax = MDIV, upper ecx = FbDIV
wrmsr(GLCP_SYS_RSTPLL, msrGlcpSysRstpll);
// You should never get here..... The chip has reset.
- POST_CODE(POST_PLL_RESET_FAIL);
+ post_code(POST_PLL_RESET_FAIL);
while (1);
} // we haven't configured the PLL; do it now
print_debug(":");
print_debug_hex32(msrGlcpSysRstpll.lo);
print_debug("\n");
- POST_CODE(POST_PLL_INIT);
+ post_code(POST_PLL_INIT);
if (!(msrGlcpSysRstpll.lo & (1 << RSTPLL_LOWER_SWFLAGS_SHIFT))) {
print_debug("Configuring PLL\n");
if (manualconf) {
- POST_CODE(POST_PLL_MANUAL);
+ post_code(POST_PLL_MANUAL);
/* CPU and GLIU mult/div (GLMC_CLK = GLIU_CLK / 2) */
msrGlcpSysRstpll.hi = PLLMSRhi;
msrGlcpSysRstpll.lo = PLLMSRlo;
} else {
/*automatic configuration (straps) */
- POST_CODE(POST_PLL_STRAP);
+ post_code(POST_PLL_STRAP);
msrGlcpSysRstpll.lo &=
~(0xFF << RSTPPL_LOWER_HOLD_COUNT_SHIFT);
msrGlcpSysRstpll.lo |=
/* You should never get here..... The chip has reset. */
print_debug("CONFIGURING PLL FAILURE\n");
- POST_CODE(POST_PLL_RESET_FAIL);
+ post_code(POST_PLL_RESET_FAIL);
__asm__ __volatile__("hlt\n");
}
spd_byte = spd_read_byte(dimm, SPD_NUM_DIMM_BANKS);
if ((MIN_MOD_BANKS > spd_byte) || (spd_byte > MAX_MOD_BANKS)) {
print_emerg("Number of module banks not compatible\n");
- POST_CODE(ERROR_BANK_SET);
+ post_code(ERROR_BANK_SET);
hcf();
}
dimm_setting |= (spd_byte >> 1) << CF07_UPPER_D0_MB_SHIFT;
spd_byte = spd_read_byte(dimm, SPD_NUM_BANKS_PER_SDRAM);
if ((MIN_DEV_BANKS > spd_byte) || (spd_byte > MAX_DEV_BANKS)) {
print_emerg("Number of device banks not compatible\n");
- POST_CODE(ERROR_BANK_SET);
+ post_code(ERROR_BANK_SET);
hcf();
}
dimm_setting |= (spd_byte >> 2) << CF07_UPPER_D0_CB_SHIFT;
if ((spd_read_byte(dimm, SPD_NUM_ROWS) & 0xF0)
|| (spd_read_byte(dimm, SPD_NUM_COLUMNS) & 0xF0)) {
print_emerg("Assymetirc DIMM not compatible\n");
- POST_CODE(ERROR_UNSUPPORTED_DIMM);
+ post_code(ERROR_UNSUPPORTED_DIMM);
hcf();
}
banner("SPDBANKDENSITY");
banner("TEST DIMM SIZE>8");
if (dimm_size > 8) { /* 8 is 1GB only support 1GB per DIMM */
print_emerg("Only support up to 1 GB per DIMM\n");
- POST_CODE(ERROR_DENSITY_DIMM);
+ post_code(ERROR_DENSITY_DIMM);
hcf();
}
dimm_setting |= dimm_size << CF07_UPPER_D0_SZ_SHIFT;
banner("MAXCOLADDR");
if (spd_byte > MAX_COL_ADDR) {
print_emerg("DIMM page size not compatible\n");
- POST_CODE(ERROR_SET_PAGE);
+ post_code(ERROR_SET_PAGE);
hcf();
}
banner(">12address test");
/* I don't think you need this check.
if (spd_byte0 >= 0xA0 || spd_byte1 >= 0xA0){
print_emerg("DIMM overclocked. Check GeodeLink Speed\n");
- POST_CODE(POST_PLL_MEM_FAIL);
+ post_code(POST_PLL_MEM_FAIL);
hcf();
} */
/* current speed > max speed? */
if (GeodeLinkSpeed() > speed) {
print_emerg("DIMM overclocked. Check GeodeLink Speed\n");
- POST_CODE(POST_PLL_MEM_FAIL);
+ post_code(POST_PLL_MEM_FAIL);
hcf();
}
}
spd_byte = CASDDR[__builtin_ctz((uint32_t) casmap0)];
} else {
print_emerg("DIMM CAS Latencies not compatible\n");
- POST_CODE(ERROR_DIFF_DIMMS);
+ post_code(ERROR_DIFF_DIMMS);
hcf();
}
uint8_t spd_byte;
banner("sdram_set_spd_register\n");
- POST_CODE(POST_MEM_SETUP); // post_70h
+ post_code(POST_MEM_SETUP); // post_70h
spd_byte = spd_read_byte(DIMM0, SPD_MODULE_ATTRIBUTES);
banner("Check DIMM 0");
/* Check DIMM is not Register and not Buffered DIMMs. */
if ((spd_byte != 0xFF) && (spd_byte & 3)) {
print_emerg("DIMM0 NOT COMPATIBLE\n");
- POST_CODE(ERROR_UNSUPPORTED_DIMM);
+ post_code(ERROR_UNSUPPORTED_DIMM);
hcf();
}
banner("Check DIMM 1");
spd_byte = spd_read_byte(DIMM1, SPD_MODULE_ATTRIBUTES);
if ((spd_byte != 0xFF) && (spd_byte & 3)) {
print_emerg("DIMM1 NOT COMPATIBLE\n");
- POST_CODE(ERROR_UNSUPPORTED_DIMM);
+ post_code(ERROR_UNSUPPORTED_DIMM);
hcf();
}
- POST_CODE(POST_MEM_SETUP2); // post_72h
+ post_code(POST_MEM_SETUP2); // post_72h
banner("Check DDR MAX");
/* Check that the memory is not overclocked. */
checkDDRMax();
/* Size the DIMMS */
- POST_CODE(POST_MEM_SETUP3); // post_73h
+ post_code(POST_MEM_SETUP3); // post_73h
banner("AUTOSIZE DIMM 0");
auto_size_dimm(DIMM0);
- POST_CODE(POST_MEM_SETUP4); // post_74h
+ post_code(POST_MEM_SETUP4); // post_74h
banner("AUTOSIZE DIMM 1");
auto_size_dimm(DIMM1);
/* Set CAS latency */
banner("set cas latency");
- POST_CODE(POST_MEM_SETUP5); // post_75h
+ post_code(POST_MEM_SETUP5); // post_75h
setCAS();
/* Set all the other latencies here (tRAS, tRP....) */
;* 9) MRS w/ memory config & reset DLL clear
;* 8) DDR SDRAM ready for normal operation
;********************************************************************/
- POST_CODE(POST_MEM_ENABLE); // post_76h
+ post_code(POST_MEM_ENABLE); // post_76h
/* Only enable MTest for TLA memory debug */
/*EnableMTest(); */
if ((msr.hi & ((7 << CF07_UPPER_D1_PSZ_SHIFT) | (7 << CF07_UPPER_D0_PSZ_SHIFT))) ==
((7 << CF07_UPPER_D1_PSZ_SHIFT) | (7 << CF07_UPPER_D0_PSZ_SHIFT))) {
print_emerg("No memory in the system\n");
- POST_CODE(ERROR_NO_DIMMS);
+ post_code(ERROR_NO_DIMMS);
hcf();
}
wrmsr(msrnum, msr);
print_emerg("DRAM controller init done.\n");
- POST_CODE(POST_MEM_SETUP_GOOD); //0x7E
+ post_code(POST_MEM_SETUP_GOOD); //0x7E
/* make sure there is nothing stale in the cache */
/* CAR stack is in the cache __asm__ __volatile__("wbinvd\n"); */
projects / coreboot.git / commitdiff