--- /dev/null
+##################################################################\r
+## BEGIN BOILERPLATE - DO NOT EDIT\r
+##\r
+## Compute the location and size of where this firmware image\r
+## (linuxBIOS plus payload) will live in the boot rom chip.\r
+##\r
+if USE_FALLBACK_IMAGE\r
+# The fallback image uses FALLBACK_SIZE bytes at the end of the ROM\r
+\r
+ default ROM_SECTION_SIZE = FALLBACK_SIZE\r
+ default ROM_SECTION_OFFSET = ( ROM_SIZE - FALLBACK_SIZE )\r
+\r
+else\r
+# The normal image goes at the beginning of the LinuxBIOS ROM region\r
+# and uses all the remaining space\r
+\r
+ default ROM_SECTION_SIZE = ( ROM_SIZE - FALLBACK_SIZE )\r
+ default ROM_SECTION_OFFSET = 0\r
+end\r
+\r
+##\r
+## Compute where this copy of linuxBIOS will start in the boot rom\r
+##\r
+default _ROMBASE = ( CONFIG_ROM_STREAM_START + PAYLOAD_SIZE )\r
+\r
+##\r
+## Compute a range of ROM that can cached to speed up linuxBIOS,\r
+## execution speed.\r
+##\r
+## XIP_ROM_SIZE must be a power of 2.\r
+## XIP_ROM_BASE must be a multiple of XIP_ROM_SIZE\r
+default XIP_ROM_SIZE = 65536\r
+default XIP_ROM_BASE = ((( _ROMBASE + ROM_IMAGE_SIZE ) / XIP_ROM_SIZE ) * XIP_ROM_SIZE - XIP_ROM_SIZE )\r
+\r
+## END BOILERPLATE\r
+##################################################################\r
+\r
+arch i386 end \r
+\r
+##\r
+## Build the objects we have code for in this directory.\r
+##\r
+\r
+driver mainboard.o\r
+if HAVE_MP_TABLE object mptable.o end\r
+if HAVE_PIRQ_TABLE object irq_tables.o end\r
+if HAVE_ACPI_TABLES object acpi_tables.o end\r
+object reset.o\r
+\r
+# Include the VGA option ROM, but only if we're compiled to use it\r
+if CONFIG_PCI_ROM_RUN\r
+ if CONFIG_CONSOLE_VGA \r
+ object vgarom.S\r
+ else\r
+ object no_vgarom.S\r
+ end\r
+else\r
+ object no_vgarom.S\r
+end\r
+\r
+##\r
+## Romcc output\r
+##\r
+makerule ./failover.E\r
+ depends "$(MAINBOARD)/failover.c ./romcc"\r
+ action "./romcc -E -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"\r
+end\r
+\r
+makerule ./failover.inc\r
+ depends "$(MAINBOARD)/failover.c ./romcc"\r
+ action "./romcc -O --label-prefix=failover -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/failover.c -o $@"\r
+end\r
+\r
+makerule ./auto.E\r
+ depends "$(MAINBOARD)/auto.c option_table.h ./romcc"\r
+ action "./romcc -E -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"\r
+end\r
+makerule ./auto.inc\r
+ depends "$(MAINBOARD)/auto.c option_table.h ./romcc"\r
+ action "./romcc -mcpu=p4 -O2 -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"\r
+end\r
+\r
+##\r
+## Build our 16 bit and 32 bit linuxBIOS entry code\r
+##\r
+mainboardinit cpu/x86/16bit/entry16.inc\r
+mainboardinit cpu/x86/32bit/entry32.inc\r
+ldscript /cpu/x86/16bit/entry16.lds\r
+ldscript /cpu/x86/32bit/entry32.lds\r
+\r
+##\r
+## Build our reset vector (This is where linuxBIOS is entered)\r
+##\r
+if HAVE_FALLBACK_BOOT\r
+ if USE_FALLBACK_IMAGE \r
+ mainboardinit cpu/x86/16bit/reset16.inc \r
+ ldscript /cpu/x86/16bit/reset16.lds\r
+ else\r
+ mainboardinit cpu/x86/32bit/reset32.inc \r
+ ldscript /cpu/x86/32bit/reset32.lds \r
+ end\r
+else\r
+ mainboardinit cpu/x86/16bit/reset16.inc \r
+ ldscript /cpu/x86/16bit/reset16.lds\r
+end\r
+\r
+### Should this be in the northbridge code?\r
+mainboardinit arch/i386/lib/cpu_reset.inc\r
+\r
+##\r
+## Include an id string (For safe flashing)\r
+##\r
+mainboardinit arch/i386/lib/id.inc\r
+ldscript /arch/i386/lib/id.lds\r
+\r
+###\r
+### This is the early phase of linuxBIOS startup \r
+### Things are delicate and we test to see if we should\r
+### failover to another image.\r
+###\r
+if USE_FALLBACK_IMAGE\r
+ ldscript /arch/i386/lib/failover.lds \r
+ mainboardinit ./failover.inc\r
+end\r
+\r
+###\r
+### O.k. We aren't just an intermediary anymore!\r
+###\r
+\r
+##\r
+## Setup RAM\r
+##\r
+mainboardinit cpu/x86/fpu/enable_fpu.inc\r
+mainboardinit cpu/x86/mmx/enable_mmx.inc\r
+mainboardinit cpu/x86/sse/enable_sse.inc\r
+mainboardinit ./auto.inc\r
+mainboardinit cpu/x86/sse/disable_sse.inc\r
+mainboardinit cpu/x86/mmx/disable_mmx.inc\r
+\r
+##\r
+## Include the secondary Configuration files \r
+##\r
+dir /pc80\r
+\r
+if CONFIG_CHIP_NAME\r
+ config chip.h\r
+end\r
+\r
+# based on sample config for tyan/s2735\r
+chip northbridge/intel/e7501\r
+ device pci_domain 0 on\r
+ device pci 0.0 on end # Chipset host controller\r
+ device pci 0.1 on end # Host RASUM controller\r
+ device pci 2.0 on # Hub interface B\r
+ chip southbridge/intel/i82870 # P64H2\r
+ device pci 1c.0 on end # IOAPIC - bus B\r
+ device pci 1d.0 on end # Hub to PCI-B bridge \r
+ device pci 1e.0 on end # IOAPIC - bus A \r
+ device pci 1f.0 on end # Hub to PCI-A bridge\r
+ end\r
+ end\r
+ device pci 3.0 off end # Hub interface C (82808AA connector - disable for now)\r
+ device pci 4.0 on # Hub interface D\r
+ chip southbridge/intel/i82870 # P64H2\r
+ device pci 1c.0 on end # IOAPIC - bus B\r
+ device pci 1d.0 on end # Hub to PCI-B bridge\r
+ device pci 1e.0 on end # IOAPIC - bus A\r
+ device pci 1f.0 on end # Hub to PCI-A bridge\r
+ end\r
+ end\r
+ device pci 6.0 on end # E7501 Power management registers? (undocumented)\r
+ chip southbridge/intel/i82801ca\r
+ device pci 1d.0 off end # USB (might not work, Southbridge code needs looking at)\r
+ device pci 1d.1 off end # USB (not populated)\r
+ device pci 1d.2 off end # USB (not populated)\r
+ device pci 1e.0 on # Hub to PCI bridge\r
+ chip drivers/pci/onboard # VGA ROM
+ device pci 0.0 on end
+ register "rom_address" = "_vgarom_start"
+ end\r
+ end
+ device pci 1f.0 on # LPC bridge\r
+ chip superio/smsc/lpc47b272\r
+ device pnp 2e.0 off # Floppy\r
+ io 0x60 = 0x3f0\r
+ irq 0x70 = 6\r
+ drq 0x74 = 2\r
+ end\r
+ device pnp 2e.3 off # Parallel Port\r
+ io 0x60 = 0x378\r
+ irq 0x70 = 7\r
+ end\r
+ device pnp 2e.4 on # Com1\r
+ io 0x60 = 0x3f8\r
+ irq 0x70 = 4\r
+ end\r
+ device pnp 2e.5 off # Com2\r
+ io 0x60 = 0x2f8\r
+ irq 0x70 = 3\r
+ end\r
+ device pnp 2e.7 on # Keyboard\r
+ io 0x60 = 0x60\r
+ io 0x62 = 0x64\r
+ irq 0x70 = 1 # Keyboard interrupt\r
+ irq 0x72 = 12 # Mouse interrupt\r
+ end\r
+ device pnp 2e.a off end # ACPI\r
+ end\r
+ end\r
+ device pci 1f.1 on end # IDE\r
+ device pci 1f.3 on end # SMBus\r
+ device pci 1f.5 off end # AC97 Audio\r
+ device pci 1f.6 off end # AC97 Modem\r
+ end # SB\r
+ end # PCI_DOMAIN\r
+ device apic_cluster 0 on\r
+ chip cpu/intel/socket_mPGA604_533Mhz\r
+ device apic 0 on end\r
+ end\r
+ chip cpu/intel/socket_mPGA604_533Mhz\r
+ device apic 6 on end\r
+ end\r
+ end\r
+end\r
--- /dev/null
+uses HAVE_MP_TABLE\r
+uses HAVE_ACPI_TABLES\r
+uses HAVE_PIRQ_TABLE\r
+uses HAVE_FALLBACK_BOOT\r
+uses HAVE_OPTION_TABLE\r
+uses IRQ_SLOT_COUNT\r
+uses CONFIG_MAX_CPUS\r
+uses CONFIG_LOGICAL_CPUS\r
+uses CONFIG_MAX_PHYSICAL_CPUS\r
+uses CONFIG_IOAPIC\r
+uses CONFIG_SMP\r
+uses CONFIG_ROM_STREAM\r
+uses STACK_SIZE\r
+uses HEAP_SIZE\r
+uses USE_OPTION_TABLE\r
+uses LB_CKS_RANGE_START\r
+uses LB_CKS_RANGE_END\r
+uses LB_CKS_LOC\r
+uses MAINBOARD_PART_NUMBER\r
+uses MAINBOARD_VENDOR\r
+uses MAINBOARD\r
+uses MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID\r
+uses MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID\r
+uses _RAMBASE\r
+uses TTYS0_BAUD\r
+uses TTYS0_BASE\r
+uses TTYS0_LCS\r
+uses DEFAULT_CONSOLE_LOGLEVEL\r
+uses MAXIMUM_CONSOLE_LOGLEVEL\r
+uses MAINBOARD_POWER_ON_AFTER_POWER_FAIL\r
+uses CONFIG_CONSOLE_SERIAL8250\r
+uses CONFIG_UDELAY_TSC\r
+uses CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2\r
+uses HAVE_INIT_TIMER\r
+uses CONFIG_GDB_STUB\r
+uses CROSS_COMPILE\r
+uses CC\r
+uses HOSTCC\r
+uses OBJCOPY\r
+uses CONFIG_CHIP_NAME\r
+uses CONFIG_CONSOLE_VGA\r
+uses CONFIG_PCI_ROM_RUN\r
+uses DEBUG\r
+uses CPU_OPT\r
+uses CONFIG_IDE\r
+\r
+## The default definitions are used for these\r
+uses CONFIG_ROM_STREAM_START\r
+uses PAYLOAD_SIZE\r
+\r
+## These are defined in target Config.lb, don't add here\r
+uses USE_FALLBACK_IMAGE\r
+uses ROM_SIZE\r
+uses ROM_IMAGE_SIZE\r
+uses FALLBACK_SIZE\r
+uses LINUXBIOS_EXTRA_VERSION\r
+\r
+## These are defined in mainboard Config.lb, don't add here\r
+uses ROM_SECTION_SIZE\r
+uses ROM_SECTION_OFFSET\r
+uses _ROMBASE\r
+uses XIP_ROM_SIZE\r
+uses XIP_ROM_BASE\r
+\r
+###\r
+### Build options\r
+###\r
+\r
+##\r
+## Build code for the fallback boot?\r
+##\r
+default HAVE_FALLBACK_BOOT=0\r
+\r
+\r
+## Delay timer options\r
+##\r
+default CONFIG_UDELAY_TSC=1\r
+default CONFIG_TSC_X86RDTSC_CALIBRATE_WITH_TIMER2=1\r
+\r
+##\r
+## Build code to export a programmable irq routing table\r
+##\r
+default HAVE_PIRQ_TABLE=1\r
+default IRQ_SLOT_COUNT=12\r
+\r
+##\r
+## Build code to export an x86 MP table\r
+## Useful for specifying IRQ routing values\r
+##\r
+default HAVE_MP_TABLE=1\r
+\r
+## Build code to export ACPI tables?\r
+default HAVE_ACPI_TABLES=1\r
+\r
+##\r
+## Build code to export a CMOS option table?\r
+##\r
+default HAVE_OPTION_TABLE=0\r
+\r
+## CMOS checksum definitions (units == bytes)\r
+## These must match the checksum record in cmos.layout\r
+default LB_CKS_RANGE_START=128\r
+default LB_CKS_RANGE_END=130\r
+default LB_CKS_LOC=131\r
+\r
+##\r
+## Build code for SMP support\r
+## Only worry about 2 micro processors\r
+## NOTE: CONFIG_MAX_CPUS is the number of LOGICAL CPUs,\r
+## so if CONFIG_LOGICAL_CPUS is 1, CONFIG_MAX_CPUS should be 4.\r
+##\r
+default CONFIG_SMP=1\r
+default CONFIG_MAX_CPUS=2\r
+default CONFIG_LOGICAL_CPUS=0\r
+default CONFIG_MAX_PHYSICAL_CPUS=2\r
+\r
+# VGA Console\r
+# NOTE: to initialize VGA, need to copy the VGA option ROM from the factory BIOS\r
+# to VGA.rom\r
+default CONFIG_CONSOLE_VGA=0\r
+default CONFIG_PCI_ROM_RUN=0\r
+\r
+##\r
+## Build code to setup a generic IOAPIC\r
+##\r
+default CONFIG_IOAPIC=1\r
+\r
+##\r
+## Motherboard identification\r
+##\r
+default MAINBOARD_PART_NUMBER="EIDXE7501DEVKIT"\r
+default MAINBOARD_VENDOR="Intel"\r
+default MAINBOARD_PCI_SUBSYSTEM_VENDOR_ID=0x8086\r
+default MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID=0x2480\r
+\r
+###\r
+### LinuxBIOS layout values\r
+###\r
+\r
+##\r
+## Use a small 8K stack\r
+##\r
+default STACK_SIZE=0x2000\r
+\r
+##\r
+## Use a small 16K heap\r
+##\r
+default HEAP_SIZE=0x4000\r
+\r
+##\r
+## CMOS settings not currently supported due to conflicts with factory BIOS\r
+##\r
+default USE_OPTION_TABLE = 0\r
+\r
+##\r
+## LinuxBIOS C code runs at this location in RAM\r
+##\r
+default _RAMBASE=0x00004000\r
+\r
+##\r
+## Load the payload from the ROM\r
+##\r
+default CONFIG_ROM_STREAM = 1\r
+\r
+###\r
+### Defaults of options that you may want to override in the target config file\r
+### \r
+\r
+##\r
+## The default compiler\r
+##\r
+default CC="$(CROSS_COMPILE)gcc -m32"\r
+default HOSTCC="gcc"\r
+\r
+##\r
+## Disable the gdb stub by default\r
+## \r
+default CONFIG_GDB_STUB=0\r
+\r
+##\r
+## The Serial Console\r
+##\r
+\r
+# To Enable the Serial Console\r
+default CONFIG_CONSOLE_SERIAL8250=1\r
+\r
+## Select the serial console baud rate\r
+default TTYS0_BAUD=115200\r
+#default TTYS0_BAUD=57600\r
+#default TTYS0_BAUD=38400\r
+#default TTYS0_BAUD=19200\r
+#default TTYS0_BAUD=9600\r
+#default TTYS0_BAUD=4800\r
+#default TTYS0_BAUD=2400\r
+#default TTYS0_BAUD=1200\r
+\r
+# Select the serial console base port\r
+default TTYS0_BASE=0x3f8\r
+\r
+# Select the serial protocol\r
+# This defaults to 8 data bits, 1 stop bit, and no parity\r
+default TTYS0_LCS=0x3\r
+\r
+##\r
+### Select the linuxBIOS loglevel\r
+##\r
+## EMERG 1 system is unusable \r
+## ALERT 2 action must be taken immediately \r
+## CRIT 3 critical conditions \r
+## ERR 4 error conditions \r
+## WARNING 5 warning conditions \r
+## NOTICE 6 normal but significant condition \r
+## INFO 7 informational \r
+## DEBUG 8 debug-level messages \r
+## SPEW 9 Way too many details \r
+\r
+## Request this level of debugging output\r
+default DEFAULT_CONSOLE_LOGLEVEL=8\r
+## At a maximum only compile in this level of debugging\r
+default MAXIMUM_CONSOLE_LOGLEVEL=8\r
+\r
+##\r
+## Select power on after power fail setting\r
+default MAINBOARD_POWER_ON_AFTER_POWER_FAIL="MAINBOARD_POWER_ON"\r
+\r
+## Things we may not have\r
+default CONFIG_IDE=1\r
+\r
+default DEBUG=1\r
+default CPU_OPT="-g"\r
+default CONFIG_CHIP_NAME=1\r
+\r
+### End Options.lb\r
+end\r
--- /dev/null
+/*\r
+ * Ported to Intel XE7501DEVKIT from Island Aruma\r
+ * written by Stefan Reinauer <stepan@openbios.org>\r
+ * (C) 2005 Stefan Reinauer\r
+ * (C) 2005 Digital Design Corporation\r
+ */\r
+\r
+#include <console/console.h>\r
+#include <string.h>\r
+#include <arch/acpi.h>\r
+#include <device/pci.h>\r
+#include <device/pci_ids.h>\r
+#include <assert.h>\r
+#include "bus.h"\r
+#include "ioapic.h"\r
+\r
+unsigned long acpi_dump_apics(unsigned long current)\r
+{\r
+ unsigned int irq_start = 0;\r
+ device_t dev = 0;\r
+ struct resource* res = NULL;\r
+\r
+ \r
+ // SJM: Hard-code CPU LAPIC entries for now\r
+ // Use SourcePoint numbering of processors\r
+ current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 0, 6);\r
+ current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 1, 7);\r
+ current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 2, 0);\r
+ current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 3, 1);\r
+ \r
+\r
+ // Southbridge IOAPIC\r
+ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, IOAPIC_ICH3, 0xfec00000, irq_start);\r
+ irq_start += INTEL_IOAPIC_NUM_INTERRUPTS;\r
+\r
+ // P64H2#2 Bus A IOAPIC\r
+ dev = dev_find_slot(PCI_BUS_E7501_HI_B, PCI_DEVFN(30, 0)); \r
+ if (!dev)\r
+ BUG(); // Config.lb error?\r
+ res = find_resource(dev, PCI_BASE_ADDRESS_0);\r
+ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, IOAPIC_P64H2_2_BUS_A, res->base, irq_start);\r
+ irq_start += INTEL_IOAPIC_NUM_INTERRUPTS;\r
+\r
+ // P64H2#2 Bus B IOAPIC\r
+ dev = dev_find_slot(PCI_BUS_E7501_HI_B, PCI_DEVFN(28, 0)); \r
+ if (!dev)\r
+ BUG(); // Config.lb error?\r
+ res = find_resource(dev, PCI_BASE_ADDRESS_0);\r
+ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, IOAPIC_P64H2_2_BUS_B, res->base, irq_start);\r
+ irq_start += INTEL_IOAPIC_NUM_INTERRUPTS;\r
+\r
+\r
+ // P64H2#1 Bus A IOAPIC\r
+ dev = dev_find_slot(PCI_BUS_E7501_HI_D, PCI_DEVFN(30, 0)); \r
+ if (!dev)\r
+ BUG(); // Config.lb error?\r
+ res = find_resource(dev, PCI_BASE_ADDRESS_0);\r
+ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, IOAPIC_P64H2_1_BUS_A, res->base, irq_start);\r
+ irq_start += INTEL_IOAPIC_NUM_INTERRUPTS;\r
+\r
+ // P64H2#1 Bus B IOAPIC\r
+ dev = dev_find_slot(PCI_BUS_E7501_HI_D, PCI_DEVFN(28, 0)); \r
+ if (!dev)\r
+ BUG(); // Config.lb error?\r
+ res = find_resource(dev, PCI_BASE_ADDRESS_0);\r
+ current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, IOAPIC_P64H2_1_BUS_B, res->base, irq_start);\r
+ irq_start += INTEL_IOAPIC_NUM_INTERRUPTS;\r
+\r
+ // Map ISA IRQ 0 to IRQ 2\r
+ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)current, 1, 0, 2, 0);\r
+\r
+ // IRQ9 differs from ISA standard - ours is active high, level-triggered\r
+ current += acpi_create_madt_irqoverride((acpi_madt_irqoverride_t *)current, 0, 9, 9, 0xD);\r
+\r
+ return current;\r
+}\r
+\r
+\r
+unsigned long write_acpi_tables(unsigned long start)\r
+{\r
+ unsigned long current;\r
+ acpi_rsdp_t *rsdp;\r
+ acpi_rsdt_t *rsdt;\r
+ acpi_madt_t *madt;\r
+\r
+ /* Align ACPI tables to 16byte */\r
+ start = ( start + 0x0f ) & -0x10;\r
+ current = start;\r
+ \r
+ printk_info("ACPI: Writing ACPI tables at %lx...\n", start);\r
+\r
+ /* We need at least an RSDP and an RSDT Table */\r
+ rsdp = (acpi_rsdp_t *) current;\r
+ current += sizeof(acpi_rsdp_t);\r
+ rsdt = (acpi_rsdt_t *) current;\r
+ current += sizeof(acpi_rsdt_t);\r
+\r
+ /* clear all table memory */\r
+ memset((void *)start, 0, current - start);\r
+ \r
+ acpi_write_rsdp(rsdp, rsdt);\r
+ acpi_write_rsdt(rsdt);\r
+ \r
+ /*\r
+ * We explicitly add these tables later on:\r
+ */\r
+ /* QNX wants an MADT */\r
+ printk_debug("ACPI: * MADT\n");\r
+\r
+ madt = (acpi_madt_t *) current;\r
+ acpi_create_madt(madt);\r
+ current+=madt->header.length;\r
+ acpi_add_table(rsdt,madt);\r
+\r
+ printk_info("ACPI: done.\n");\r
+ return current;\r
+}\r
+\r
--- /dev/null
+#define ASSEMBLY 1\r
+\r
+#include <stdint.h>\r
+#include <device/pci_def.h>\r
+#include <arch/io.h>\r
+#include <device/pnp_def.h>\r
+#include <arch/romcc_io.h>\r
+#include <cpu/x86/lapic.h>\r
+#include <arch/cpu.h>\r
+#include "option_table.h"\r
+#include "pc80/mc146818rtc_early.c"\r
+#include "pc80/serial.c"\r
+#include "arch/i386/lib/console.c"\r
+#include "ram/ramtest.c"\r
+#include "southbridge/intel/i82801ca/i82801ca_early_smbus.c"\r
+#include "northbridge/intel/e7501/raminit.h"\r
+#include "cpu/x86/lapic/boot_cpu.c"\r
+#include "northbridge/intel/e7501/debug.c"\r
+#include "superio/smsc/lpc47b272/lpc47b272_early_serial.c"\r
+#include "cpu/x86/mtrr/earlymtrr.c"\r
+#include "cpu/x86/bist.h"\r
+\r
+#define SUPERIO_PORT 0x2e\r
+#define SERIAL_DEV PNP_DEV(SUPERIO_PORT, LPC47B272_SP1)\r
+\r
+static void hard_reset(void)\r
+{\r
+ outb(0x0e, 0x0cf9);\r
+}\r
+\r
+static inline void activate_spd_rom(const struct mem_controller *ctrl)\r
+{\r
+ /* nothing to do */\r
+}\r
+ \r
+static inline int spd_read_byte(unsigned device, unsigned address)\r
+{\r
+ return smbus_read_byte(device, address);\r
+}\r
+\r
+#include "northbridge/intel/e7501/raminit.c"\r
+#include "northbridge/intel/e7501/reset_test.c"\r
+#include "sdram/generic_sdram.c"\r
+\r
+\r
+// This function MUST appear last (ROMCC limitation)\r
+static void main(unsigned long bist)\r
+{\r
+ static const struct mem_controller memctrl[] = {\r
+ {\r
+ .d0 = PCI_DEV(0, 0, 0),\r
+ .d0f1 = PCI_DEV(0, 0, 1),\r
+ .channel0 = { (0xa<<3)|0, (0xa<<3)|1, (0xa<<3)|2, 0 },\r
+ .channel1 = { (0xa<<3)|4, (0xa<<3)|5, (0xa<<3)|6, 0 },\r
+ },\r
+ };\r
+\r
+ if (bist == 0) \r
+ {\r
+ // Skip this if there was a built in self test failure\r
+\r
+ early_mtrr_init();\r
+ enable_lapic();\r
+ }\r
+\r
+ // Get the serial port running and print a welcome banner\r
+\r
+ lpc47b272_enable_serial(SERIAL_DEV, TTYS0_BASE);\r
+ uart_init();\r
+ console_init();\r
+\r
+ // Halt if there was a built in self test failure\r
+ report_bist_failure(bist);\r
+\r
+// print_pci_devices();\r
+\r
+ // If this is a warm boot, some initialization can be skipped\r
+\r
+ if (!bios_reset_detected()) \r
+ {\r
+ enable_smbus();\r
+// dump_spd_registers(&memctrl[0]);\r
+// dump_smbus_registers();\r
+\r
+// memreset_setup(); No-op for this chipset\r
+ sdram_initialize(sizeof(memctrl)/sizeof(memctrl[0]), memctrl);\r
+ }\r
+ \r
+ // NOTE: ROMCC dies with an internal compiler error\r
+ // if the following line is removed.\r
+ print_debug("SDRAM is up.\r\n");\r
+}\r
--- /dev/null
+#ifndef XE7501DEVKIT_BUS_H_INCLUDED\r
+#define XE7501DEVKIT_BUS_H_INCLUDED\r
+\r
+// These were determined by seeing how LinuxBIOS enumerates the various\r
+// PCI (and PCI-like) buses on the board.\r
+\r
+#define PCI_BUS_CHIPSET 0\r
+#define PCI_BUS_E7501_HI_B 1 // P64H2#2\r
+#define PCI_BUS_P64H2_2_B 2 // P64H2#2 bus B\r
+#define PCI_BUS_P64H2_2_A 3 // P64H2#2 bus A\r
+#define PCI_BUS_E7501_HI_D 4 // P64H2#1\r
+#define PCI_BUS_P64H2_1_B 5 // P64H2#1 bus B\r
+#define PCI_BUS_P64H2_1_A 6 // P64H2#1 bus A\r
+#define PCI_BUS_ICH3 7 // ICH3-S\r
+#define SUPERIO_BUS 8 // (arbitrary but unique bus #)\r
+\r
+#endif // XE7501DEVKIT_BUS_H_INCLUDED\r
--- /dev/null
+extern unsigned char _vgarom_start[];\r
+\r
+extern struct chip_operations mainboard_intel_xe7501devkit_ops;\r
+\r
+struct mainboard_intel_xe7501devkit_config {\r
+};\r
--- /dev/null
+# NOTE: This file must be in UNIX format (not DOS) or build_opt_tbl fails:
+# "Error - Name is an invalid identifier in line"
+
+entries
+
+#start-bit length config config-ID name
+0 512 r 0 reserved_memory1 # We know nothing about the factory BIOS
+512 512 r 0 reserved_memory2 # More factory BIOS
+
+# Work in progress.\r
+# This is where we would put the LB RTC_BOOT_BYTE options once the code\r
+# supports finding them there.
+#1024 1 e 4 boot_option
+#1025 1 e 4 last_boot
+#1026 1 e 1 ECC_memory
+#1028 4 r 0 reboot_bits
+
+# Options used by XE7501DevKit
+#1032 3 e 5 baud_rate
+#1035 1 e 2 hyper_threading
+#1036 1 e 1 power_on_after_fail
+#1037 1 e 1 nmi
+
+#1040 4 e 6 debug_level
+
+#1048 16 h 0 check_sum
+
+
+
+enumerations
+
+#ID value text
+1 0 Disable
+1 1 Enable
+2 0 Enable
+2 1 Disable
+4 0 Fallback
+4 1 Normal
+5 0 115200
+5 1 57600
+5 2 38400
+5 3 19200
+5 4 9600
+5 5 4800
+5 6 2400
+5 7 1200
+6 6 Notice
+6 7 Info
+6 8 Debug
+6 9 Spew
+
+checksums
+
+# Checksum FROM bit-location TO bit-location STORE AT bit-location
+#checksum 1024 1047 1048
--- /dev/null
+#define ASSEMBLY 1\r
+#include <stdint.h>\r
+#include <device/pci_def.h>\r
+#include <device/pci_ids.h>\r
+#include <arch/io.h>\r
+#include <arch/romcc_io.h>\r
+#include <cpu/x86/lapic.h>\r
+#include "pc80/mc146818rtc_early.c"\r
+#include "southbridge/intel/i82801ca/cmos_failover.c"\r
+#include "cpu/x86/lapic/boot_cpu.c"\r
+#include "northbridge/intel/e7501/reset_test.c"\r
+\r
+static unsigned long main(unsigned long bist)\r
+{\r
+ /* Is this a deliberate reset by the bios */\r
+ if (bios_reset_detected() && last_boot_normal()) {\r
+ goto normal_image;\r
+ }\r
+ /* This is the primary cpu how should I boot? */\r
+ else {\r
+\r
+ check_cmos_failed(); \r
+\r
+ if (do_normal_boot()) {\r
+ goto normal_image;\r
+ }\r
+ else {\r
+ goto fallback_image;\r
+ }\r
+ }\r
+ normal_image:\r
+ asm volatile ("jmp __normal_image" \r
+ : /* outputs */ \r
+ : "a" (bist) /* inputs */\r
+ : /* clobbers */\r
+ );\r
+#if 0\r
+ cpu_reset:\r
+ asm volatile ("jmp __cpu_reset"\r
+ : /* outputs */ \r
+ : "a"(bist) /* inputs */\r
+ : /* clobbers */\r
+ );\r
+#endif\r
+ fallback_image:\r
+ return bist;\r
+}\r
--- /dev/null
+// IOAPIC addresses determined by LinuxBIOS enumeration. \r
+// Someday add functions to get APIC IDs and versions from the chips themselves.\r
+ \r
+#define IOAPIC_ICH3 2\r
+#define IOAPIC_P64H2_2_BUS_B 3 // IOAPIC 3 at 01:1c.0 MBAR = fe300000 DataAddr = fe300010\r
+#define IOAPIC_P64H2_2_BUS_A 4 // IOAPIC 4 at 01:1e.0 MBAR = fe301000 DataAddr = fe301010\r
+#define IOAPIC_P64H2_1_BUS_B 5 // IOAPIC 5 at 04:1c.0 MBAR = fe500000 DataAddr = fe500010\r
+#define IOAPIC_P64H2_1_BUS_A 8 // IOAPIC 8 at 04:1e.0 MBAR = fe501000 DataAddr = fe501010\r
+\r
+#define P64H2_IOAPIC_VERSION 0x20\r
+#define INTEL_IOAPIC_NUM_INTERRUPTS 24 // Both ICH-3 and P64-H2\r
--- /dev/null
+/* Run checkpir to verify any changes to this table...\r
+ Documentation at : http://www.microsoft.com/whdc/archive/pciirq.mspx\r
+*/\r
+\r
+#include <arch/pirq_routing.h>\r
+#include <device/pci_def.h>\r
+#include <device/pci_ids.h>\r
+#include "bus.h"\r
+\r
+#define UNUSED_INTERRUPT {0, 0}\r
+#define PIRQ_A 0x60\r
+#define PIRQ_B 0x61\r
+#define PIRQ_C 0x62\r
+#define PIRQ_D 0x63\r
+#define PIRQ_E 0x68\r
+#define PIRQ_F 0x69\r
+#define PIRQ_G 0x6A\r
+#define PIRQ_H 0x6B\r
+\r
+const struct irq_routing_table intel_irq_routing_table = {\r
+ PIRQ_SIGNATURE,\r
+ PIRQ_VERSION,\r
+ 32 + 12*sizeof(struct irq_info), // Size of this struct in bytes\r
+ 0, // PCI bus number on which the interrupt router resides\r
+ PCI_DEVFN(31, 0), // PCI device/function number of the interrupt router\r
+ 0, // PCI-exclusive IRQ bitmap\r
+ PCI_VENDOR_ID_INTEL, // Vendor ID of compatible PCI interrupt router\r
+ PCI_DEVICE_ID_INTEL_82801CA_LPC, // Device ID of compatible PCI interrupt router\r
+ 0, // Additional miniport information\r
+ { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, // Reserved, must be zero\r
+ 0xB1, // Checksum of the entire structure (causes 8-bit sum == 0)\r
+ {\r
+ // NOTE: For 82801, a nonzero link value is a pointer to a PIRQ[n]_ROUT register in PCI configuration space\r
+ // This was determined from linux-2.6.11/arch/i386/pci/irq.c\r
+ // bitmap of 0xdcf8 == routable to IRQ3-IRQ7, IRQ10-IRQ12, or IRQ14-IRQ15\r
+ // ICH-3 doesn't allow SERIRQ or PCI message to generate IRQ0, IRQ2, IRQ8, or IRQ13\r
+ // Not sure why IRQ9 isn't routable (inherited from Tyan S2735)\r
+ \r
+ // INTA# INTB# INTC# INTD#\r
+ // bus, device # {link , bitmap}, {link , bitmap}, {link , bitmap}, {link , bitmap}, slot, rfu\r
+ \r
+ {PCI_BUS_CHIPSET, PCI_DEVFN(31, 0), {{PIRQ_C, 0xdcf8}, {PIRQ_B, 0xdcf8}, UNUSED_INTERRUPT, UNUSED_INTERRUPT}, 0, 0}, // IDE / SMBus\r
+ {PCI_BUS_CHIPSET, PCI_DEVFN(29, 0), {{PIRQ_A, 0xdcf8}, {PIRQ_D, 0xdcf8}, {PIRQ_C, 0xdcf8}, UNUSED_INTERRUPT}, 0, 0}, // USB 1.1\r
+ \r
+ // P64H2#2 Bus A\r
+ {PCI_BUS_P64H2_2_A, PCI_DEVFN(1, 0), {{PIRQ_B, 0xdcf8}, {PIRQ_B, 0xdcf8}, UNUSED_INTERRUPT, UNUSED_INTERRUPT}, 0, 0}, // SCSI\r
+ // NOTE: Hotplug disabled on this bus\r
+ \r
+ // P64H2#2 Bus B\r
+ {PCI_BUS_P64H2_2_B, PCI_DEVFN(1, 0), {{PIRQ_B, 0xdcf8}, {PIRQ_B, 0xdcf8}, {PIRQ_B, 0xdcf8}, {PIRQ_B, 0xdcf8}}, 23, 0}, // Slot 2A (J23)\r
+ {PCI_BUS_P64H2_2_B, PCI_DEVFN(2, 0), {{PIRQ_B, 0xdcf8}, {PIRQ_B, 0xdcf8}, {PIRQ_B, 0xdcf8}, {PIRQ_B, 0xdcf8}}, 24, 0}, // Slot 2B (J24)\r
+ {PCI_BUS_P64H2_2_B, PCI_DEVFN(3, 0), {{PIRQ_B, 0xdcf8}, {PIRQ_B, 0xdcf8}, {PIRQ_B, 0xdcf8}, {PIRQ_B, 0xdcf8}}, 25, 0}, // Slot 2C (J25)\r
+ {PCI_BUS_P64H2_2_B, PCI_DEVFN(4, 0), {{PIRQ_B, 0xdcf8}, {PIRQ_B, 0xdcf8}, {PIRQ_B, 0xdcf8}, {PIRQ_B, 0xdcf8}}, 12, 0}, // Slot 2D (J12)\r
+ // NOTE: Hotplug disabled on this bus\r
+\r
+ // P64H2#1 Bus A\r
+ {PCI_BUS_P64H2_1_A, PCI_DEVFN(1, 0), {{PIRQ_A, 0xdcf8}, {PIRQ_A, 0xdcf8}, {PIRQ_A, 0xdcf8}, {PIRQ_A, 0xdcf8}}, 20, 0}, // Slot 1A (J20)\r
+ // NOTE: Hotplug disabled on this bus\r
+\r
+ // P64H2#1 Bus B\r
+ {PCI_BUS_P64H2_1_B, PCI_DEVFN(1, 0), {{PIRQ_A, 0xdcf8}, UNUSED_INTERRUPT, UNUSED_INTERRUPT, UNUSED_INTERRUPT}, 0, 0}, // GB Ethernet\r
+ {PCI_BUS_P64H2_1_B, PCI_DEVFN(2, 0), {{PIRQ_A, 0xdcf8}, {PIRQ_A, 0xdcf8}, {PIRQ_A, 0xdcf8}, {PIRQ_A, 0xdcf8}}, 21, 0}, // Slot 1B (J21)\r
+ // NOTE: Hotplug disabled on this bus\r
+ \r
+ // ICH-3 PCI bus\r
+ {PCI_BUS_ICH3, PCI_DEVFN(0, 0), {{PIRQ_A, 0xdcf8}, UNUSED_INTERRUPT, UNUSED_INTERRUPT, UNUSED_INTERRUPT}, 0, 0}, // Video\r
+ {PCI_BUS_ICH3, PCI_DEVFN(2, 0), {{PIRQ_C, 0xdcf8}, {PIRQ_D, 0xdcf8}, {PIRQ_A, 0xdcf8}, {PIRQ_B, 0xdcf8}}, 11, 0}, // Debug slot (J11)\r
+ }\r
+};\r
+\r
+unsigned long write_pirq_routing_table(unsigned long addr)\r
+{\r
+ return copy_pirq_routing_table(addr);\r
+}\r
--- /dev/null
+#include <console/console.h>\r
+#include <device/device.h>\r
+#include <device/pci.h>\r
+#include <device/pci_ids.h>\r
+#include <device/pci_ops.h>\r
+#include "chip.h"\r
+\r
+#if CONFIG_CHIP_NAME == 1\r
+struct chip_operations mainboard_intel_xe7501devkit_ops = {\r
+ CHIP_NAME("Intel Xeon E7501 DevKit mainboard")\r
+};\r
+#endif\r
--- /dev/null
+#include <console/console.h>\r
+#include <arch/smp/mpspec.h>\r
+#include <device/pci.h>\r
+#include <string.h>\r
+#include <stdint.h>\r
+#include <assert.h>\r
+#include "bus.h"\r
+#include "ioapic.h"\r
+\r
+// Generate MP-table IRQ numbers for PCI devices.\r
+#define INT_A 0\r
+#define INT_B 1\r
+#define INT_C 2\r
+#define INT_D 3\r
+#define PCI_IRQ(dev, intLine) (((dev)<<2) | intLine)\r
+\r
+\r
+void xe7501devkit_register_buses(struct mp_config_table *mc)\r
+{\r
+ // Bus ID, Bus Type\r
+ smp_write_bus(mc, PCI_BUS_CHIPSET, BUSTYPE_PCI);\r
+ smp_write_bus(mc, PCI_BUS_E7501_HI_B, BUSTYPE_PCI);\r
+ smp_write_bus(mc, PCI_BUS_P64H2_2_B, BUSTYPE_PCI);\r
+ smp_write_bus(mc, PCI_BUS_P64H2_2_A, BUSTYPE_PCI);\r
+ smp_write_bus(mc, PCI_BUS_E7501_HI_D, BUSTYPE_PCI);\r
+ smp_write_bus(mc, PCI_BUS_P64H2_1_B, BUSTYPE_PCI);\r
+ smp_write_bus(mc, PCI_BUS_P64H2_1_A, BUSTYPE_PCI);\r
+ smp_write_bus(mc, PCI_BUS_ICH3, BUSTYPE_PCI);\r
+ smp_write_bus(mc, SUPERIO_BUS, BUSTYPE_ISA);\r
+}\r
+\r
+void xe7501devkit_register_ioapics(struct mp_config_table *mc)\r
+{\r
+ device_t dev;\r
+ struct resource *res;\r
+\r
+ // TODO: Gack. This is REALLY ugly.\r
+\r
+ // Southbridge IOAPIC\r
+ smp_write_ioapic(mc, IOAPIC_ICH3, 0x20, 0xfec00000); // APIC ID, Version, Address\r
+\r
+ // P64H2#2 Bus A IOAPIC\r
+ dev = dev_find_slot(PCI_BUS_E7501_HI_B, PCI_DEVFN(30, 0)); \r
+ if (!dev)\r
+ BUG(); // Config.lb error?\r
+ res = find_resource(dev, PCI_BASE_ADDRESS_0);\r
+ smp_write_ioapic(mc, IOAPIC_P64H2_2_BUS_A, P64H2_IOAPIC_VERSION, res->base);\r
+\r
+ // P64H2#2 Bus B IOAPIC\r
+ dev = dev_find_slot(PCI_BUS_E7501_HI_B, PCI_DEVFN(28, 0)); \r
+ if (!dev)\r
+ BUG(); // Config.lb error?\r
+ res = find_resource(dev, PCI_BASE_ADDRESS_0);\r
+ smp_write_ioapic(mc, IOAPIC_P64H2_2_BUS_B, P64H2_IOAPIC_VERSION, res->base);\r
+\r
+\r
+ // P64H2#1 Bus A IOAPIC\r
+ dev = dev_find_slot(PCI_BUS_E7501_HI_D, PCI_DEVFN(30, 0)); \r
+ if (!dev)\r
+ BUG(); // Config.lb error?\r
+ res = find_resource(dev, PCI_BASE_ADDRESS_0);\r
+ smp_write_ioapic(mc, IOAPIC_P64H2_1_BUS_A, P64H2_IOAPIC_VERSION, res->base);\r
+\r
+ // P64H2#1 Bus B IOAPIC\r
+ dev = dev_find_slot(PCI_BUS_E7501_HI_D, PCI_DEVFN(28, 0)); \r
+ if (!dev)\r
+ BUG(); // Config.lb error?\r
+ res = find_resource(dev, PCI_BASE_ADDRESS_0);\r
+ smp_write_ioapic(mc, IOAPIC_P64H2_1_BUS_B, P64H2_IOAPIC_VERSION, res->base);\r
+}\r
+\r
+void xe7501devkit_register_interrupts(struct mp_config_table *mc)\r
+{\r
+ // Chipset PCI bus\r
+ // Type Trigger | Polarity Bus ID IRQ APIC ID PIN#\r
+ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE |MP_IRQ_POLARITY_HIGH, PCI_BUS_CHIPSET, 0, MP_APIC_ALL, 0);\r
+ smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE |MP_IRQ_POLARITY_HIGH, PCI_BUS_CHIPSET, 0, MP_APIC_ALL, 1);\r
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_CHIPSET, PCI_IRQ(29, INT_A), IOAPIC_ICH3, 16); // USB 1.1 Controller #1\r
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_CHIPSET, PCI_IRQ(31, INT_B), IOAPIC_ICH3, 17); // SMBus\r
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_CHIPSET, PCI_IRQ(29, INT_C), IOAPIC_ICH3, 18); // USB 1.1 Controller #3\r
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_CHIPSET, PCI_IRQ(31, INT_C), IOAPIC_ICH3, 18); // IDE\r
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_CHIPSET, PCI_IRQ(29, INT_D), IOAPIC_ICH3, 19); // USB 1.1 Controller #2\r
+\r
+ // P64H2#2 Bus B\r
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_B, PCI_IRQ(1, INT_A), IOAPIC_P64H2_2_BUS_B, 0); // Slot 2A (J23)\r
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_B, PCI_IRQ(1, INT_B), IOAPIC_P64H2_2_BUS_B, 1); // Slot 2A (J23)\r
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_B, PCI_IRQ(1, INT_C), IOAPIC_P64H2_2_BUS_B, 2); // Slot 2A (J23)\r
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_B, PCI_IRQ(1, INT_D), IOAPIC_P64H2_2_BUS_B, 3); // Slot 2A (J23)\r
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_B, PCI_IRQ(2, INT_A), IOAPIC_P64H2_2_BUS_B, 4); // Slot 2B (J24)\r
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_B, PCI_IRQ(2, INT_B), IOAPIC_P64H2_2_BUS_B, 5); // Slot 2B (J24)\r
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_B, PCI_IRQ(2, INT_C), IOAPIC_P64H2_2_BUS_B, 6); // Slot 2B (J24)\r
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_B, PCI_IRQ(2, INT_D), IOAPIC_P64H2_2_BUS_B, 7); // Slot 2B (J24)\r
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_B, PCI_IRQ(3, INT_A), IOAPIC_P64H2_2_BUS_B, 8); // Slot 2C (J25)\r
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_B, PCI_IRQ(3, INT_B), IOAPIC_P64H2_2_BUS_B, 9); // Slot 2C (J25)\r
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_B, PCI_IRQ(3, INT_C), IOAPIC_P64H2_2_BUS_B, 10); // Slot 2C (J25)\r
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_B, PCI_IRQ(3, INT_D), IOAPIC_P64H2_2_BUS_B, 11); // Slot 2C (J25)\r
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_B, PCI_IRQ(4, INT_A), IOAPIC_P64H2_2_BUS_B, 12); // Slot 2D (J12)\r
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_B, PCI_IRQ(4, INT_B), IOAPIC_P64H2_2_BUS_B, 13); // Slot 2D (J12)\r
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_B, PCI_IRQ(4, INT_C), IOAPIC_P64H2_2_BUS_B, 14); // Slot 2D (J12)\r
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_B, PCI_IRQ(4, INT_D), IOAPIC_P64H2_2_BUS_B, 15); // Slot 2D (J12)\r
+ \r
+ // P64H2#2 Bus A\r
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_A, PCI_IRQ(1, INT_A), IOAPIC_P64H2_2_BUS_A, 0); // SCSI\r
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_2_A, PCI_IRQ(1, INT_B), IOAPIC_P64H2_2_BUS_A, 1); // SCSI\r
+ \r
+ // P64H2#1 Bus B\r
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_1_B, PCI_IRQ(1, INT_A), IOAPIC_P64H2_1_BUS_B, 0); // GB Ethernet\r
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_1_B, PCI_IRQ(2, INT_A), IOAPIC_P64H2_1_BUS_B, 4); // Slot 1B (J21)\r
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_1_B, PCI_IRQ(2, INT_B), IOAPIC_P64H2_1_BUS_B, 5); // Slot 1B (J21)\r
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_1_B, PCI_IRQ(2, INT_C), IOAPIC_P64H2_1_BUS_B, 6); // Slot 1B (J21)\r
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_1_B, PCI_IRQ(2, INT_D), IOAPIC_P64H2_1_BUS_B, 7); // Slot 1B (J21)\r
+\r
+ // P64H2#1 Bus A\r
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_1_A, PCI_IRQ(1, INT_A), IOAPIC_P64H2_1_BUS_A, 0); // Slot 1A (J20)\r
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_1_A, PCI_IRQ(1, INT_B), IOAPIC_P64H2_1_BUS_A, 1); // Slot 1A (J20)\r
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_1_A, PCI_IRQ(1, INT_C), IOAPIC_P64H2_1_BUS_A, 2); // Slot 1A (J20)\r
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_P64H2_1_A, PCI_IRQ(1, INT_D), IOAPIC_P64H2_1_BUS_A, 3); // Slot 1A (J20)\r
+\r
+ // ICH-3\r
+ \r
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_ICH3, PCI_IRQ(0, INT_A), IOAPIC_ICH3, 16); // Video\r
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_ICH3, PCI_IRQ(2, INT_A), IOAPIC_ICH3, 18); // Debug slot (J11)\r
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_ICH3, PCI_IRQ(2, INT_B), IOAPIC_ICH3, 19); // Debug slot (J11)\r
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_ICH3, PCI_IRQ(2, INT_C), IOAPIC_ICH3, 16); // Debug slot (J11)\r
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_ICH3, PCI_IRQ(2, INT_D), IOAPIC_ICH3, 17); // Debug slot (J11)\r
+ \r
+ // TODO: Not sure how to handle BT_INTR# signals from the P64H2s. Do we even need to, in APIC mode?\r
+\r
+ // Super I/O (ISA interrupts)\r
+ smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE |MP_IRQ_POLARITY_HIGH, SUPERIO_BUS, 0, IOAPIC_ICH3, 0);\r
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE |MP_IRQ_POLARITY_HIGH, SUPERIO_BUS, 1, IOAPIC_ICH3, 1);\r
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE |MP_IRQ_POLARITY_HIGH, SUPERIO_BUS, 0, IOAPIC_ICH3, 2);\r
+\r
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE |MP_IRQ_POLARITY_HIGH, SUPERIO_BUS, 3, IOAPIC_ICH3, 3);\r
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE |MP_IRQ_POLARITY_HIGH, SUPERIO_BUS, 4, IOAPIC_ICH3, 4);\r
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE |MP_IRQ_POLARITY_HIGH, SUPERIO_BUS, 6, IOAPIC_ICH3, 6);\r
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE |MP_IRQ_POLARITY_HIGH, SUPERIO_BUS, 8, IOAPIC_ICH3, 8);\r
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE |MP_IRQ_POLARITY_HIGH, SUPERIO_BUS, 9, IOAPIC_ICH3, 9);\r
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE |MP_IRQ_POLARITY_HIGH, SUPERIO_BUS, 12, IOAPIC_ICH3, 12);\r
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE |MP_IRQ_POLARITY_HIGH, SUPERIO_BUS, 13, IOAPIC_ICH3, 13);\r
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE |MP_IRQ_POLARITY_HIGH, SUPERIO_BUS, 14, IOAPIC_ICH3, 14);\r
+ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_EDGE |MP_IRQ_POLARITY_HIGH, SUPERIO_BUS, 15, IOAPIC_ICH3, 15);\r
+}\r
+\r
+void* smp_write_config_table(void* v)\r
+{\r
+ static const char sig[4] = MPC_SIGNATURE;\r
+ static const char oem[8] = "INTEL ";\r
+ static const char productid[12] = "XE7501DEVKIT";\r
+ struct mp_config_table *mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN);\r
+ memset(mc, 0, sizeof(*mc));\r
+\r
+ memcpy(mc->mpc_signature, sig, sizeof(sig));\r
+ memcpy(mc->mpc_oem, oem, sizeof(oem));\r
+ memcpy(mc->mpc_productid, productid, sizeof(productid));\r
+\r
+ mc->mpc_length = sizeof(*mc); // initially just the header\r
+ mc->mpc_spec = 0x04; // Multiprocessing Spec V1.4\r
+ mc->mpc_lapic = LAPIC_ADDR;\r
+\r
+ smp_write_processors(mc);\r
+\r
+ xe7501devkit_register_buses(mc);\r
+ xe7501devkit_register_ioapics(mc);\r
+ xe7501devkit_register_interrupts(mc);\r
+\r
+ /* Compute the checksums */\r
+ mc->mpe_checksum = smp_compute_checksum(smp_next_mpc_entry(mc), mc->mpe_length);\r
+ mc->mpc_checksum = smp_compute_checksum(mc, mc->mpc_length);\r
+ printk_debug("Wrote the mp table end at: %p - %p\n", mc, smp_next_mpe_entry(mc));\r
+\r
+ return smp_next_mpe_entry(mc);\r
+}\r
+\r
+unsigned long write_smp_table(unsigned long addr)\r
+{\r
+ void *v;\r
+ v = smp_write_floating_table(addr);\r
+ return (unsigned long)smp_write_config_table(v);\r
+}\r
--- /dev/null
+ .section .rodata.optionrom
+ .globl _vgarom_start
+_vgarom_start:
+ .word 0xFFFF // Invalid option ROM signature
+ .globl _vgarom_end
+_vgarom_end:
--- /dev/null
+
+void hard_reset(void)
+{
+ i82801ca_hard_reset();
+}
--- /dev/null
+ .section .rodata.optionrom
+ .globl _vgarom_start
+_vgarom_start:
+ .incbin "../../../../../src/mainboard/intel/xe7501devkit/vga.rom"
+ .globl _vgarom_end
+_vgarom_end:
projects / coreboot.git / commitdiff