1. Remove warnings and multiple blank lines.

2. Mahogany uses GPIO9 to detect 80-pin IDE cable.

Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Patrick Georgi <patrick.georgi@coresystems.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5300 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

diff --git a/src/mainboard/amd/mahogany/acpi_tables.c b/src/mainboard/amd/mahogany/acpi_tables.c
index 248c0f888eda0d4822df68455edc394a585644cf..ec99acf1939e517b55277c22119056ff99a027a4 100644 (file)
--- a/src/mainboard/amd/mahogany/acpi_tables.c
+++ b/src/mainboard/amd/mahogany/acpi_tables.c
@@ -101,6 +101,7 @@ unsigned long acpi_fill_madt(unsigned long current)
 
 extern void get_bus_conf(void);
 
+#if CONFIG_ACPI_SSDTX_NUM >= 1
 static void update_ssdtx(void *ssdtx, int i)
 {
        uint8_t *PCI;
@@ -122,6 +123,7 @@ static void update_ssdtx(void *ssdtx, int i)
        /* FIXME: need to update the GSI id in the ssdtx too */
 
 }
+#endif
 
 unsigned long acpi_fill_ssdt_generator(unsigned long current, const char *oem_table_id) {
        k8acpi_write_vars();
@@ -140,6 +142,11 @@ unsigned long write_acpi_tables(unsigned long start)
        acpi_facs_t *facs;
        acpi_header_t *dsdt;
        acpi_header_t *ssdt;
+#if CONFIG_ACPI_SSDTX_NUM >= 1
+       acpi_header_t *ssdtx;
+       acpi_header_t const *p;
+       int i;
+#endif
 
        get_bus_conf();         /* it will get sblk, pci1234, hcdn, and sbdn */
 

diff --git a/src/mainboard/amd/mahogany/devicetree.cb b/src/mainboard/amd/mahogany/devicetree.cb
index 2cc3baf83707ddc7cd30fe904b9175e6e5ad7ef3..19979a2e919a889ffd27bc2aab3eec021407d2ae 100644 (file)
--- a/src/mainboard/amd/mahogany/devicetree.cb
+++ b/src/mainboard/amd/mahogany/devicetree.cb
@@ -121,4 +121,3 @@ chip northbridge/amd/amdk8/root_complex
                end             #northbridge/amd/amdk8
        end #pci_domain
 end            #northbridge/amd/amdk8/root_complex
-

diff --git a/src/mainboard/amd/mahogany/get_bus_conf.c b/src/mainboard/amd/mahogany/get_bus_conf.c
index f17124ba41ea23b183334f424b9792e4f1cd1984..25d83d6005b727fb79d361d46820e57874379e83 100644 (file)
--- a/src/mainboard/amd/mahogany/get_bus_conf.c
+++ b/src/mainboard/amd/mahogany/get_bus_conf.c
@@ -63,6 +63,8 @@ extern void get_sblk_pci1234(void);
 
 static u32 get_bus_conf_done = 0;
 
+void get_bus_conf(void);
+
 void get_bus_conf(void)
 {
        u32 apicid_base;

diff --git a/src/mainboard/amd/mahogany/mainboard.c b/src/mainboard/amd/mahogany/mainboard.c
index ed0f50a5a462d70ba8da8d6d2c564fc1a5d8abba..44752f1e91af2dbd33f0c2fbb2ac9f26328b493d 100644 (file)
--- a/src/mainboard/amd/mahogany/mainboard.c
+++ b/src/mainboard/amd/mahogany/mainboard.c
@@ -25,6 +25,7 @@
 #include <cpu/x86/msr.h>
 #include <cpu/amd/mtrr.h>
 #include <device/pci_def.h>
+#include <arch/coreboot_tables.h>
 #include <../southbridge/amd/sb700/sb700.h>
 #include "chip.h"
 
@@ -35,6 +36,9 @@ extern void lb_add_memory_range(struct lb_memory *mem, uint32_t type,
 
 uint64_t uma_memory_base, uma_memory_size;
 
+void set_pcie_dereset(void);
+void set_pcie_reset(void);
+
 /*
  * Mahogany uses GPIO 6 as PCIe slot reset, GPIO4 as GFX slot reset. We need to
  * pull it up before training the slot.
@@ -65,12 +69,13 @@ void set_pcie_reset()
        pci_write_config16(sm_dev, 0xA8, word);
 }
 
+#if 0       /* not tested yet */
 /********************************************************
-* mahogany uses SB700 GPIO8 to detect IDE_DMA66.
-* IDE_DMA66 is routed to GPIO 8. So we read Gpio 8 to
+* mahogany uses SB700 GPIO9 to detect IDE_DMA66.
+* IDE_DMA66 is routed to GPIO 9. So we read Gpio 9 to
 * get the cable type, 40 pin or 80 pin?
 ********************************************************/
-static void get_ide_dma66()
+static void get_ide_dma66(void)
 {
        u8 byte;
        /*u32 sm_dev, ide_dev; */
@@ -79,27 +84,29 @@ static void get_ide_dma66()
        sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
 
        byte = pci_read_config8(sm_dev, 0xA9);
-       byte |= (1 << 4);       /* Set Gpio8 as input */
+       byte |= (1 << 5);       /* Set Gpio9 as input */
        pci_write_config8(sm_dev, 0xA9, byte);
 
        ide_dev = dev_find_slot(0, PCI_DEVFN(0x14, 1));
        byte = pci_read_config8(ide_dev, 0x56);
        byte &= ~(7 << 0);
-       if ((1 << 4) & pci_read_config8(sm_dev, 0xAA))
+       if ((1 << 5) & pci_read_config8(sm_dev, 0xAA))
                byte |= 2 << 0; /* mode 2 */
        else
                byte |= 5 << 0; /* mode 5 */
        pci_write_config8(ide_dev, 0x56, byte);
 }
+#endif /* get_ide_dma66 */
 
 /*************************************************
 * enable the dedicated function in mahogany board.
 * This function called early than rs780_enable.
 *************************************************/
-void mahogany_enable(device_t dev)
+static void mahogany_enable(device_t dev)
 {
-       struct mainboard_config *mainboard =
-           (struct mainboard_config *)dev->chip_info;
+       /* Leave it for future. */
+       /* struct mainboard_config *mainboard =
+          (struct mainboard_config *)dev->chip_info;*/
 
        printk(BIOS_INFO, "Mainboard MAHOGANY Enable. dev=0x%p\n", dev);
 
@@ -158,6 +165,7 @@ int add_mainboard_resources(struct lb_memory *mem)
        lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base,
                            uma_memory_size);
 #endif
+       return 0;
 }
 
 struct chip_operations mainboard_ops = {

diff --git a/src/mainboard/amd/mahogany_fam10/Kconfig b/src/mainboard/amd/mahogany_fam10/Kconfig
index fa956eee759c40ad5ec4fd239f1b366c16a68c87..2c379337dc216d6574d47ebe3c50130826a06ccf 100644 (file)
--- a/src/mainboard/amd/mahogany_fam10/Kconfig
+++ b/src/mainboard/amd/mahogany_fam10/Kconfig
@@ -117,7 +117,7 @@ config HEAP_SIZE
 
 config ACPI_SSDTX_NUM
        int
-       default 31
+       default 0
        depends on BOARD_AMD_MAHOGANY_FAM10
 
 config MAINBOARD_PCI_SUBSYSTEM_DEVICE_ID

diff --git a/src/mainboard/amd/mahogany_fam10/acpi_tables.c b/src/mainboard/amd/mahogany_fam10/acpi_tables.c
index 878141da5443ac2b57af52370360526bada5c418..203254b0dba07cd7f54d7c2d65a7d7a6eb5386c1 100644 (file)
--- a/src/mainboard/amd/mahogany_fam10/acpi_tables.c
+++ b/src/mainboard/amd/mahogany_fam10/acpi_tables.c
@@ -92,7 +92,8 @@ unsigned long acpi_fill_madt(unsigned long current)
 extern void get_bus_conf(void);
 extern void update_ssdt(void *ssdt);
 
-
+/* not tested yet. */
+#if CONFIG_ACPI_SSDTX_NUM >= 1
 static void update_ssdtx(void *ssdtx, int i)
 {
        u8 *PCI;
@@ -115,6 +116,7 @@ static void update_ssdtx(void *ssdtx, int i)
        /* FIXME: need to update the GSI id in the ssdtx too */
 
 }
+#endif
 
 unsigned long write_acpi_tables(unsigned long start)
 {
@@ -129,10 +131,11 @@ unsigned long write_acpi_tables(unsigned long start)
        acpi_facs_t *facs;
        acpi_header_t *dsdt;
        acpi_header_t *ssdt;
+#if CONFIG_ACPI_SSDTX_NUM >= 1
        acpi_header_t *ssdtx;
        acpi_header_t const *p;
-
        int i;
+#endif
 
        get_bus_conf(); //it will get sblk, pci1234, hcdn, and sbdn
 
@@ -204,7 +207,7 @@ unsigned long write_acpi_tables(unsigned long start)
        printk(BIOS_DEBUG, "ACPI:    * SSDT for PState at %lx\n", current);
        current = acpi_add_ssdt_pstates(rsdp, current);
 
-#if 0 //CONFIG_ACPI_SSDTX_NUM >= 1
+#if CONFIG_ACPI_SSDTX_NUM >= 1
 
        /* same htio, but different possition? We may have to copy,
        change HCIN, and recalculate the checknum and add_table */

diff --git a/src/mainboard/amd/mahogany_fam10/devicetree.cb b/src/mainboard/amd/mahogany_fam10/devicetree.cb
index 085fe70fa22cb753fcfade1f508e3dd7ac04e799..8478ac11656c9c12bf1365227d18e505c31e6f98 100644 (file)
--- a/src/mainboard/amd/mahogany_fam10/devicetree.cb
+++ b/src/mainboard/amd/mahogany_fam10/devicetree.cb
@@ -143,5 +143,3 @@ chip northbridge/amd/amdfam10/root_complex
 #       end
 
 end
-
-

diff --git a/src/mainboard/amd/mahogany_fam10/mainboard.c b/src/mainboard/amd/mahogany_fam10/mainboard.c
index ed0f50a5a462d70ba8da8d6d2c564fc1a5d8abba..82a9b9eeef965342ee1574ee8becd9608f697406 100644 (file)
--- a/src/mainboard/amd/mahogany_fam10/mainboard.c
+++ b/src/mainboard/amd/mahogany_fam10/mainboard.c
@@ -25,6 +25,7 @@
 #include <cpu/x86/msr.h>
 #include <cpu/amd/mtrr.h>
 #include <device/pci_def.h>
+#include <arch/coreboot_tables.h>
 #include <../southbridge/amd/sb700/sb700.h>
 #include "chip.h"
 
@@ -35,6 +36,9 @@ extern void lb_add_memory_range(struct lb_memory *mem, uint32_t type,
 
 uint64_t uma_memory_base, uma_memory_size;
 
+void set_pcie_dereset(void);
+void set_pcie_reset(void);
+
 /*
  * Mahogany uses GPIO 6 as PCIe slot reset, GPIO4 as GFX slot reset. We need to
  * pull it up before training the slot.
@@ -65,12 +69,13 @@ void set_pcie_reset()
        pci_write_config16(sm_dev, 0xA8, word);
 }
 
+#if 0       /* not tested yet. */
 /********************************************************
-* mahogany uses SB700 GPIO8 to detect IDE_DMA66.
-* IDE_DMA66 is routed to GPIO 8. So we read Gpio 8 to
+* mahogany uses SB700 GPIO9 to detect IDE_DMA66.
+* IDE_DMA66 is routed to GPIO 9. So we read Gpio 9 to
 * get the cable type, 40 pin or 80 pin?
 ********************************************************/
-static void get_ide_dma66()
+static void get_ide_dma66(void)
 {
        u8 byte;
        /*u32 sm_dev, ide_dev; */
@@ -79,27 +84,29 @@ static void get_ide_dma66()
        sm_dev = dev_find_slot(0, PCI_DEVFN(0x14, 0));
 
        byte = pci_read_config8(sm_dev, 0xA9);
-       byte |= (1 << 4);       /* Set Gpio8 as input */
+       byte |= (1 << 5);       /* Set Gpio9 as input */
        pci_write_config8(sm_dev, 0xA9, byte);
 
        ide_dev = dev_find_slot(0, PCI_DEVFN(0x14, 1));
        byte = pci_read_config8(ide_dev, 0x56);
        byte &= ~(7 << 0);
-       if ((1 << 4) & pci_read_config8(sm_dev, 0xAA))
+       if ((1 << 5) & pci_read_config8(sm_dev, 0xAA))
                byte |= 2 << 0; /* mode 2 */
        else
                byte |= 5 << 0; /* mode 5 */
        pci_write_config8(ide_dev, 0x56, byte);
 }
+#endif /* get_ide_dma66() */
 
 /*************************************************
 * enable the dedicated function in mahogany board.
 * This function called early than rs780_enable.
 *************************************************/
-void mahogany_enable(device_t dev)
+static void mahogany_enable(device_t dev)
 {
-       struct mainboard_config *mainboard =
-           (struct mainboard_config *)dev->chip_info;
+       /* Leave it for furture use. */
+       /* struct mainboard_config *mainboard =
+          (struct mainboard_config *)dev->chip_info; */
 
        printk(BIOS_INFO, "Mainboard MAHOGANY Enable. dev=0x%p\n", dev);
 
@@ -158,6 +165,7 @@ int add_mainboard_resources(struct lb_memory *mem)
        lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base,
                            uma_memory_size);
 #endif
+       return 0;
 }
 
 struct chip_operations mainboard_ops = {

diff --git a/src/mainboard/amd/mahogany_fam10/romstage.c b/src/mainboard/amd/mahogany_fam10/romstage.c
index 2a147fea8af7715e141e36ee2901413857ef21f1..f6c862443a11812e1763dbd6fe553c498fe0c2d8 100644 (file)
--- a/src/mainboard/amd/mahogany_fam10/romstage.c
+++ b/src/mainboard/amd/mahogany_fam10/romstage.c
@@ -298,4 +298,3 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        post_cache_as_ram();    // BSP switch stack to ram, copy then execute LB.
        post_code(0x43);        // Should never see this post code.
 }
-