Replace while with do; while to avoid repetition

Cosmetic only; replaces some 'while' loops with 'do; while' loops to
avoid repetition.

Replacement performed by the Ruby expression:
t.gsub!(/^(\s*)([^\n\{]+)\n\1(while[^\n\{;]+)\n\s*\2/,
	"\\1do \\2\n\\1\\3;")

Change-Id: Ie0a4fa622df881edeaab08f59bb888a903b864fd
Signed-off-by: Noe Rubinstein <nrubinstein@proformatique.com>
Signed-off-by: Patrick Georgi <patrick@georgi-clan.de>
Reviewed-on: http://review.coreboot.org/183
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

diff --git a/src/northbridge/intel/e7520/raminit.c b/src/northbridge/intel/e7520/raminit.c
index 7a0661cbe3775d99a2f6d18330f3264e9169a007..e9a60f1e20c7df1768ccdc182c32c430a49c600a 100644 (file)
--- a/src/northbridge/intel/e7520/raminit.c
+++ b/src/northbridge/intel/e7520/raminit.c
@@ -1128,9 +1128,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 
                write32(BAR+0x100, (0x83000000 | (i<<20)));
 
-               data32 = read32(BAR+DCALCSR);
-               while(data32 & 0x80000000)
-                       data32 = read32(BAR+DCALCSR);
+               do data32 = read32(BAR+DCALCSR);
+               while(data32 & 0x80000000);
 
        }
 
@@ -1139,9 +1138,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 
        for(cs=0;cs<8;cs++) {
                write32(BAR + DCALCSR, (0x83000000 | (cs<<20)));
-               data32 = read32(BAR+DCALCSR);
-               while(data32 & 0x80000000)
-                       data32 = read32(BAR+DCALCSR);
+               do data32 = read32(BAR+DCALCSR);
+               while(data32 & 0x80000000);
        }
 
        /* Precharg all banks */
@@ -1152,9 +1150,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
                 else   /* DDR1  */
                         write32(BAR+DCALADDR, 0x00000000);
                write32(BAR+DCALCSR, (0x83000002 | (cs<<20)));
-               data32 = read32(BAR+DCALCSR);
-               while(data32 & 0x80000000)
-                       data32 = read32(BAR+DCALCSR);
+               do data32 = read32(BAR+DCALCSR);
+               while(data32 & 0x80000000);
        }
 
        /* EMRS dll's enabled */
@@ -1166,9 +1163,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
                 else   /* DDR1  */
                         write32(BAR+DCALADDR, 0x00000001);
                write32(BAR+DCALCSR, (0x83000003 | (cs<<20)));
-               data32 = read32(BAR+DCALCSR);
-               while(data32 & 0x80000000)
-                       data32 = read32(BAR+DCALCSR);
+               do data32 = read32(BAR+DCALCSR);
+               while(data32 & 0x80000000);
        }
        /* MRS reset dll's */
        do_delay();
@@ -1187,9 +1183,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
        for(cs=0;cs<8;cs++) {
                write32(BAR+DCALADDR, mode_reg);
                write32(BAR+DCALCSR, (0x83000003 | (cs<<20)));
-               data32 = read32(BAR+DCALCSR);
-               while(data32 & 0x80000000)
-                       data32 = read32(BAR+DCALCSR);
+               do data32 = read32(BAR+DCALCSR);
+               while(data32 & 0x80000000);
        }
 
        /* Precharg all banks */
@@ -1202,25 +1197,22 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
                 else   /* DDR1  */
                         write32(BAR+DCALADDR, 0x00000000);
                write32(BAR+DCALCSR, (0x83000002 | (cs<<20)));
-               data32 = read32(BAR+DCALCSR);
-               while(data32 & 0x80000000)
-                       data32 = read32(BAR+DCALCSR);
+               do data32 = read32(BAR+DCALCSR);
+               while(data32 & 0x80000000);
        }
 
        /* Do 2 refreshes */
        do_delay();
        for(cs=0;cs<8;cs++) {
                write32(BAR+DCALCSR, (0x83000001 | (cs<<20)));
-               data32 = read32(BAR+DCALCSR);
-               while(data32 & 0x80000000)
-                       data32 = read32(BAR+DCALCSR);
+               do data32 = read32(BAR+DCALCSR);
+               while(data32 & 0x80000000);
        }
        do_delay();
        for(cs=0;cs<8;cs++) {
                write32(BAR+DCALCSR, (0x83000001 | (cs<<20)));
-               data32 = read32(BAR+DCALCSR);
-               while(data32 & 0x80000000)
-                       data32 = read32(BAR+DCALCSR);
+               do data32 = read32(BAR+DCALCSR);
+               while(data32 & 0x80000000);
        }
        do_delay();
        /* for good luck do 6 more */
@@ -1253,9 +1245,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
        for(cs=0;cs<8;cs++) {
                write32(BAR+DCALADDR, (mode_reg & ~(1<<24)));
                write32(BAR+DCALCSR, (0x83000003 | (cs<<20)));
-               data32 = read32(BAR+DCALCSR);
-               while(data32 & 0x80000000)
-                       data32 = read32(BAR+DCALCSR);
+               do data32 = read32(BAR+DCALCSR);
+               while(data32 & 0x80000000);
        }
 
        /* Do only if DDR2  EMRS dll's enabled */
@@ -1264,9 +1255,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
                 for(cs=0;cs<8;cs++) {
                         write32(BAR+DCALADDR, (0x0b940001));
                         write32(BAR+DCALCSR, (0x83000003 | (cs<<20)));
-                       data32 = read32(BAR+DCALCSR);
-                       while(data32 & 0x80000000)
-                               data32 = read32(BAR+DCALCSR);
+                       do data32 = read32(BAR+DCALCSR);
+                       while(data32 & 0x80000000);
                 }
         }
 
@@ -1310,9 +1300,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 
        for(cs=0;cs<8;cs++) {
                write32(BAR+DCALCSR, (0x830831d8 | (cs<<20)));
-               data32 = read32(BAR+DCALCSR);
-               while(data32 & 0x80000000)
-                       data32 = read32(BAR+DCALCSR);
+               do data32 = read32(BAR+DCALCSR);
+               while(data32 & 0x80000000);
        }
 
        /* Bring memory subsystem on line */

diff --git a/src/northbridge/intel/e7525/raminit.c b/src/northbridge/intel/e7525/raminit.c
index 495a1421cba79b4e5b16454ad6c0676a6da6c5d7..e341596997c40a87df88164de6854be8bea96223 100644 (file)
--- a/src/northbridge/intel/e7525/raminit.c
+++ b/src/northbridge/intel/e7525/raminit.c
@@ -1104,9 +1104,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 
                write32(BAR+0x100, (0x83000000 | (i<<20)));
 
-               data32 = read32(BAR+DCALCSR);
-               while(data32 & 0x80000000)
-                       data32 = read32(BAR+DCALCSR);
+               do data32 = read32(BAR+DCALCSR);
+               while(data32 & 0x80000000);
 
        }
 
@@ -1115,9 +1114,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 
        for(cs=0;cs<8;cs++) {
                write32(BAR + DCALCSR, (0x83000000 | (cs<<20)));
-               data32 = read32(BAR+DCALCSR);
-               while(data32 & 0x80000000)
-                       data32 = read32(BAR+DCALCSR);
+               do data32 = read32(BAR+DCALCSR);
+               while(data32 & 0x80000000);
        }
 
        /* Precharg all banks */
@@ -1128,9 +1126,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
                 else   /* DDR1  */
                         write32(BAR+DCALADDR, 0x00000000);
                write32(BAR+DCALCSR, (0x83000002 | (cs<<20)));
-               data32 = read32(BAR+DCALCSR);
-               while(data32 & 0x80000000)
-                       data32 = read32(BAR+DCALCSR);
+               do data32 = read32(BAR+DCALCSR);
+               while(data32 & 0x80000000);
        }
 
        /* EMRS dll's enabled */
@@ -1142,9 +1139,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
                 else   /* DDR1  */
                         write32(BAR+DCALADDR, 0x00000001);
                write32(BAR+DCALCSR, (0x83000003 | (cs<<20)));
-               data32 = read32(BAR+DCALCSR);
-               while(data32 & 0x80000000)
-                       data32 = read32(BAR+DCALCSR);
+               do data32 = read32(BAR+DCALCSR);
+               while(data32 & 0x80000000);
        }
        /* MRS reset dll's */
        do_delay();
@@ -1163,9 +1159,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
        for(cs=0;cs<8;cs++) {
                write32(BAR+DCALADDR, mode_reg);
                write32(BAR+DCALCSR, (0x83000003 | (cs<<20)));
-               data32 = read32(BAR+DCALCSR);
-               while(data32 & 0x80000000)
-                       data32 = read32(BAR+DCALCSR);
+               do data32 = read32(BAR+DCALCSR);
+               while(data32 & 0x80000000);
        }
 
        /* Precharg all banks */
@@ -1178,25 +1173,22 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
                 else   /* DDR1  */
                         write32(BAR+DCALADDR, 0x00000000);
                write32(BAR+DCALCSR, (0x83000002 | (cs<<20)));
-               data32 = read32(BAR+DCALCSR);
-               while(data32 & 0x80000000)
-                       data32 = read32(BAR+DCALCSR);
+               do data32 = read32(BAR+DCALCSR);
+               while(data32 & 0x80000000);
        }
 
        /* Do 2 refreshes */
        do_delay();
        for(cs=0;cs<8;cs++) {
                write32(BAR+DCALCSR, (0x83000001 | (cs<<20)));
-               data32 = read32(BAR+DCALCSR);
-               while(data32 & 0x80000000)
-                       data32 = read32(BAR+DCALCSR);
+               do data32 = read32(BAR+DCALCSR);
+               while(data32 & 0x80000000);
        }
        do_delay();
        for(cs=0;cs<8;cs++) {
                write32(BAR+DCALCSR, (0x83000001 | (cs<<20)));
-               data32 = read32(BAR+DCALCSR);
-               while(data32 & 0x80000000)
-                       data32 = read32(BAR+DCALCSR);
+               do data32 = read32(BAR+DCALCSR);
+               while(data32 & 0x80000000);
        }
        do_delay();
        /* for good luck do 6 more */
@@ -1229,9 +1221,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
        for(cs=0;cs<8;cs++) {
                write32(BAR+DCALADDR, (mode_reg & ~(1<<24)));
                write32(BAR+DCALCSR, (0x83000003 | (cs<<20)));
-               data32 = read32(BAR+DCALCSR);
-               while(data32 & 0x80000000)
-                       data32 = read32(BAR+DCALCSR);
+               do data32 = read32(BAR+DCALCSR);
+               while(data32 & 0x80000000);
        }
 
        /* Do only if DDR2  EMRS dll's enabled */
@@ -1240,9 +1231,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
                 for(cs=0;cs<8;cs++) {
                         write32(BAR+DCALADDR, (0x0b940001));
                         write32(BAR+DCALCSR, (0x83000003 | (cs<<20)));
-                       data32 = read32(BAR+DCALCSR);
-                       while(data32 & 0x80000000)
-                               data32 = read32(BAR+DCALCSR);
+                       do data32 = read32(BAR+DCALCSR);
+                       while(data32 & 0x80000000);
                 }
         }
 
@@ -1283,9 +1273,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 
        for(cs=0;cs<8;cs++) {
                write32(BAR+DCALCSR, (0x830831d8 | (cs<<20)));
-               data32 = read32(BAR+DCALCSR);
-               while(data32 & 0x80000000)
-                       data32 = read32(BAR+DCALCSR);
+               do data32 = read32(BAR+DCALCSR);
+               while(data32 & 0x80000000);
        }
 
        /* Bring memory subsystem on line */

diff --git a/src/northbridge/intel/i3100/raminit.c b/src/northbridge/intel/i3100/raminit.c
index 86e610feb3e4ade319d5c7f929a46f362a9947f3..ced3de1e22cd407eee90e5f144b2438714e24865 100644 (file)
--- a/src/northbridge/intel/i3100/raminit.c
+++ b/src/northbridge/intel/i3100/raminit.c
@@ -1020,9 +1020,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
                write32(MCBAR+DCALCSR, (0x01000000 | (i<<20)));
                write32(MCBAR+DCALCSR, (0x81000000 | (i<<20)));
 
-               data32 = read32(MCBAR+DCALCSR);
-               while(data32 & 0x80000000)
-                       data32 = read32(MCBAR+DCALCSR);
+               do data32 = read32(MCBAR+DCALCSR);
+               while(data32 & 0x80000000);
        }
 
        /* Apply NOP */
@@ -1030,9 +1029,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 
        for(cs=0;cs<8;cs+=2) {
                write32(MCBAR + DCALCSR, (0x81000000 | (cs<<20)));
-               data32 = read32(MCBAR+DCALCSR);
-               while(data32 & 0x80000000)
-                       data32 = read32(MCBAR+DCALCSR);
+               do data32 = read32(MCBAR+DCALCSR);
+               while(data32 & 0x80000000);
        }
 
        /* Precharg all banks */
@@ -1040,9 +1038,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
        for(cs=0;cs<8;cs+=2) {
                write32(MCBAR+DCALADDR, 0x04000000);
                write32(MCBAR+DCALCSR, (0x81000002 | (cs<<20)));
-               data32 = read32(MCBAR+DCALCSR);
-               while(data32 & 0x80000000)
-                       data32 = read32(MCBAR+DCALCSR);
+               do data32 = read32(MCBAR+DCALCSR);
+               while(data32 & 0x80000000);
        }
 
        /* EMRS dll's enabled */
@@ -1051,9 +1048,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
                /* fixme hard code AL additive latency */
                write32(MCBAR+DCALADDR, 0x0b940001);
                write32(MCBAR+DCALCSR, (0x81000003 | (cs<<20)));
-               data32 = read32(MCBAR+DCALCSR);
-               while(data32 & 0x80000000)
-                       data32 = read32(MCBAR+DCALCSR);
+               do data32 = read32(MCBAR+DCALCSR);
+               while(data32 & 0x80000000);
        }
        /* MRS reset dll's */
        do_delay();
@@ -1064,9 +1060,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
        for(cs=0;cs<8;cs+=2) {
                write32(MCBAR+DCALADDR, mode_reg);
                write32(MCBAR+DCALCSR, (0x81000003 | (cs<<20)));
-               data32 = read32(MCBAR+DCALCSR);
-               while(data32 & 0x80000000)
-                       data32 = read32(MCBAR+DCALCSR);
+               do data32 = read32(MCBAR+DCALCSR);
+               while(data32 & 0x80000000);
        }
 
        /* Precharg all banks */
@@ -1076,25 +1071,22 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
        for(cs=0;cs<8;cs+=2) {
                write32(MCBAR+DCALADDR, 0x04000000);
                write32(MCBAR+DCALCSR, (0x81000002 | (cs<<20)));
-               data32 = read32(MCBAR+DCALCSR);
-               while(data32 & 0x80000000)
-                       data32 = read32(MCBAR+DCALCSR);
+               do data32 = read32(MCBAR+DCALCSR);
+               while(data32 & 0x80000000);
        }
 
        /* Do 2 refreshes */
        do_delay();
        for(cs=0;cs<8;cs+=2) {
                write32(MCBAR+DCALCSR, (0x81000001 | (cs<<20)));
-               data32 = read32(MCBAR+DCALCSR);
-               while(data32 & 0x80000000)
-                       data32 = read32(MCBAR+DCALCSR);
+               do data32 = read32(MCBAR+DCALCSR);
+               while(data32 & 0x80000000);
        }
        do_delay();
        for(cs=0;cs<8;cs+=2) {
                write32(MCBAR+DCALCSR, (0x81000001 | (cs<<20)));
-               data32 = read32(MCBAR+DCALCSR);
-               while(data32 & 0x80000000)
-                       data32 = read32(MCBAR+DCALCSR);
+               do data32 = read32(MCBAR+DCALCSR);
+               while(data32 & 0x80000000);
        }
        do_delay();
        /* for good luck do 6 more */
@@ -1127,9 +1119,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
        for(cs=0;cs<8;cs+=2) {
                write32(MCBAR+DCALADDR, (mode_reg & ~(1<<24)));
                write32(MCBAR+DCALCSR, (0x81000003 | (cs<<20)));
-               data32 = read32(MCBAR+DCALCSR);
-               while(data32 & 0x80000000)
-                       data32 = read32(MCBAR+DCALCSR);
+               do data32 = read32(MCBAR+DCALCSR);
+               while(data32 & 0x80000000);
        }
 
        /* Do only if DDR2  EMRS dll's enabled */
@@ -1137,9 +1128,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
        for(cs=0;cs<8;cs+=2) {
                write32(MCBAR+DCALADDR, (0x0b940001));
                write32(MCBAR+DCALCSR, (0x81000003 | (cs<<20)));
-               data32 = read32(MCBAR+DCALCSR);
-               while(data32 & 0x80000000)
-                       data32 = read32(MCBAR+DCALCSR);
+               do data32 = read32(MCBAR+DCALCSR);
+               while(data32 & 0x80000000);
        }
 
        do_delay();
@@ -1173,9 +1163,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
 
        for(cs=0;cs<8;cs+=2) {
                write32(MCBAR+DCALCSR, (0x810831d8 | (cs<<20)));
-               data32 = read32(MCBAR+DCALCSR);
-               while(data32 & 0x80000000)
-                       data32 = read32(MCBAR+DCALCSR);
+               do data32 = read32(MCBAR+DCALCSR);
+               while(data32 & 0x80000000);
        }
 
        /* Bring memory subsystem on line */

diff --git a/src/northbridge/intel/i3100/raminit_ep80579.c b/src/northbridge/intel/i3100/raminit_ep80579.c
index 8967594b5331383dc872a20822e08401eea92c95..de3ffcefa56d03764a08c0f9e5823142e1fece40 100644 (file)
--- a/src/northbridge/intel/i3100/raminit_ep80579.c
+++ b/src/northbridge/intel/i3100/raminit_ep80579.c
@@ -534,9 +534,8 @@ static void set_on_dimm_termination_enable(const struct mem_controller *ctrl)
 
                write32(BAR+DCALADDR, 0x0b840001);
                write32(BAR+DCALCSR, 0x80000003 | ((i+1)<<21));
-               data32 = read32(BAR+DCALCSR);
-               while (data32 & 0x80000000)
-                       data32 = read32(BAR+DCALCSR);
+               do data32 = read32(BAR+DCALCSR);
+               while (data32 & 0x80000000);
        }
 }
 
@@ -603,9 +602,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
                udelay(16);
                write32(BAR+DCALCSR, (0x00000000 | ((cs+1)<<21)));
                write32(BAR+DCALCSR, (0x80000000 | ((cs+1)<<21)));
-               data32 = read32(BAR+DCALCSR);
-               while (data32 & 0x80000000)
-                       data32 = read32(BAR+DCALCSR);
+               do data32 = read32(BAR+DCALCSR);
+               while (data32 & 0x80000000);
        }
 
        /* Apply NOP */
@@ -615,9 +613,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
                print_debug_hex8(cs);
                print_debug("\n");
                write32(BAR + DCALCSR, (0x80000000 | ((cs+1)<<21)));
-               data32 = read32(BAR+DCALCSR);
-               while (data32 & 0x80000000)
-                       data32 = read32(BAR+DCALCSR);
+               do data32 = read32(BAR+DCALCSR);
+               while (data32 & 0x80000000);
        }
 
        /* Precharge all banks */
@@ -628,9 +625,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
                print_debug("\n");
                write32(BAR+DCALADDR, 0x04000000);
                write32(BAR+DCALCSR, (0x80000002 | ((cs+1)<<21)));
-               data32 = read32(BAR+DCALCSR);
-               while (data32 & 0x80000000)
-                       data32 = read32(BAR+DCALCSR);
+               do data32 = read32(BAR+DCALCSR);
+               while (data32 & 0x80000000);
        }
 
        /* EMRS: Enable DLLs, set OCD calibration mode to default */
@@ -641,9 +637,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
                print_debug("\n");
                write32(BAR+DCALADDR, 0x0b840001);
                write32(BAR+DCALCSR, (0x80000003 | ((cs+1)<<21)));
-               data32 = read32(BAR+DCALCSR);
-               while (data32 & 0x80000000)
-                       data32 = read32(BAR+DCALCSR);
+               do data32 = read32(BAR+DCALCSR);
+               while (data32 & 0x80000000);
        }
        /* MRS: Reset DLLs */
        udelay(16);
@@ -653,9 +648,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
                print_debug("\n");
                write32(BAR+DCALADDR, mode_reg);
                write32(BAR+DCALCSR, (0x80000003 | ((cs+1)<<21)));
-               data32 = read32(BAR+DCALCSR);
-               while (data32 & 0x80000000)
-                       data32 = read32(BAR+DCALCSR);
+               do data32 = read32(BAR+DCALCSR);
+               while (data32 & 0x80000000);
        }
 
        /* Precharge all banks */
@@ -666,9 +660,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
                print_debug("\n");
                write32(BAR+DCALADDR, 0x04000000);
                write32(BAR+DCALCSR, (0x80000002 | ((cs+1)<<21)));
-               data32 = read32(BAR+DCALCSR);
-               while (data32 & 0x80000000)
-                       data32 = read32(BAR+DCALCSR);
+               do data32 = read32(BAR+DCALCSR);
+               while (data32 & 0x80000000);
        }
 
        /* Do 2 refreshes */
@@ -679,9 +672,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
                        print_debug_hex8(cs);
                        print_debug("\n");
                        write32(BAR+DCALCSR, (0x80000001 | ((cs+1)<<21)));
-                       data32 = read32(BAR+DCALCSR);
-                       while (data32 & 0x80000000)
-                               data32 = read32(BAR+DCALCSR);
+                       do data32 = read32(BAR+DCALCSR);
+                       while (data32 & 0x80000000);
                }
        }
 
@@ -693,9 +685,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
                print_debug("\n");
                write32(BAR+DCALADDR, (mode_reg & ~(1<<24)));
                write32(BAR+DCALCSR, (0x80000003 | ((cs+1)<<21)));
-               data32 = read32(BAR+DCALCSR);
-               while (data32 & 0x80000000)
-                       data32 = read32(BAR+DCALCSR);
+               do data32 = read32(BAR+DCALCSR);
+               while (data32 & 0x80000000);
        }
 
        /* EMRS: Enable DLLs */
@@ -706,9 +697,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
                print_debug("\n");
                write32(BAR+DCALADDR, 0x0b840001);
                write32(BAR+DCALCSR, (0x80000003 | ((cs+1)<<21)));
-               data32 = read32(BAR+DCALCSR);
-               while (data32 & 0x80000000)
-                       data32 = read32(BAR+DCALCSR);
+               do data32 = read32(BAR+DCALCSR);
+               while (data32 & 0x80000000);
         }
 
        udelay(16);
@@ -729,9 +719,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
                print_debug_hex8(cs);
                print_debug("\n");
                write32(BAR+DCALCSR, (0x8000000c | ((cs+1)<<21)));
-               data32 = read32(BAR+DCALCSR);
-               while (data32 & 0x80000000)
-                       data32 = read32(BAR+DCALCSR);
+               do data32 = read32(BAR+DCALCSR);
+               while (data32 & 0x80000000);
        }
 
        dump_dcal_regs();
@@ -756,9 +745,8 @@ static void sdram_enable(int controllers, const struct mem_controller *ctrl)
                print_debug_hex8(cs);
                print_debug("\n");
                write32(BAR+MBCSR, 0xa00000f0 | ((cs+1)<<20) | (0<<16));
-               data32 = read32(BAR+MBCSR);
-               while (data32 & 0x80000000)
-                       data32 = read32(BAR+MBCSR);
+               do data32 = read32(BAR+MBCSR);
+               while (data32 & 0x80000000);
                if (data32 & 0x40000000)
                        print_debug("failed!\n");
        }