Final fix for C7 boards, which are still using ROMCC, to be able to

build. As far as I know, no C7 boards currently in the tree use SPI
flash.

Signed-off-by: Corey Osgood <corey.osgood@gmail.com>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3665 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

diff --git a/src/southbridge/via/vt8237r/vt8237r_early_smbus.c b/src/southbridge/via/vt8237r/vt8237r_early_smbus.c
index af91707ec9f3961965edd89ef08217da70584562..7b85a1979af88e224bcfdf1ad1b06c53b6a7ea7b 100644 (file)
--- a/src/southbridge/via/vt8237r/vt8237r_early_smbus.c
+++ b/src/southbridge/via/vt8237r/vt8237r_early_smbus.c
@@ -336,6 +336,7 @@ void enable_rom_decode(void)
        pci_write_config8(dev, 0x41, 0x7f);
 }
 
+#if defined(__GNUC__)
 void vt8237_early_spi_init(void)
 {
        device_t dev;
@@ -358,6 +359,7 @@ void vt8237_early_spi_init(void)
        spireg = (u16 *) (VT8237S_SPI_MEM_BASE + 0x6c);
        (*spireg) &= 0xff00;
 }
+#endif
 
 /* This #if is special. ROMCC chokes on the (rom == NULL) comparison.
  * Since the whole function is only called for one target and that target