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(parent: 293b5f5) | patch
Following patch fixes VIA SPI (VT8237S). It needs to have opcodes
authorRudolf Marek <r.marek@assembler.cz>
Sun, 1 Feb 2009 18:40:50 +0000 (18:40 +0000)
committerRudolf Marek <r.marek@assembler.cz>
Sun, 1 Feb 2009 18:40:50 +0000 (18:40 +0000)
commite66c258f1baf668fee417b08494480ddedc00749
tree07e23172066e91eeffa0609d1da4dd880c70c07atree | snapshot
parent293b5f52253ec0e5edb38e9f7113afc7e8f8ba6ecommit | diff
 Following patch fixes VIA SPI (VT8237S). It needs to have opcodes
 initialized same way as ICH7.

Signed-off-by: Rudolf Marek <r.marek@assembler.cz>
Acked-by: Peter Stuge <peter@stuge.se>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3926 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
util/flashrom/chipset_enable.c diff | blob | history
my coreboot WIP stuff (asus m5a99x-evo board)