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(parent: 8a28188) | patch
Add AMD SR56x0 support.
authorZheng Bao <zheng.bao@amd.com>
Sun, 27 Mar 2011 16:39:58 +0000 (16:39 +0000)
committerZheng Bao <Zheng.Bao@amd.com>
Sun, 27 Mar 2011 16:39:58 +0000 (16:39 +0000)
commit98fcc09cf9955e24376d15f6fe13f02545547276
treef1acc0faa6bf962243778caa8132c805b2f77e68tree | snapshot
parent8a281880a36967361e7eb39056c4ff228f97c9a3commit | diff
Add AMD SR56x0 support.

Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Marc Jones <marcj303@gmail.com>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@6462 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
src/include/device/pci_ids.h diff | blob | history
src/southbridge/amd/sr5650/Kconfig [new file with mode: 0644] blob
src/southbridge/amd/sr5650/Makefile.inc [new file with mode: 0644] blob
src/southbridge/amd/sr5650/chip.h [new file with mode: 0644] blob
src/southbridge/amd/sr5650/cmn.h [new file with mode: 0644] blob
src/southbridge/amd/sr5650/early_setup.c [new file with mode: 0644] blob
src/southbridge/amd/sr5650/ht.c [new file with mode: 0644] blob
src/southbridge/amd/sr5650/pcie.c [new file with mode: 0644] blob
src/southbridge/amd/sr5650/rev.h [new file with mode: 0644] blob
src/southbridge/amd/sr5650/sr5650.c [new file with mode: 0644] blob
src/southbridge/amd/sr5650/sr5650.h [new file with mode: 0644] blob
my coreboot WIP stuff (asus m5a99x-evo board)