Fix a few whitespace and coding style issues.

[coreboot.git] / src / southbridge / intel / sch / ide.c

diff --git a/src/southbridge/intel/sch/ide.c b/src/southbridge/intel/sch/ide.c
index 0ca98e08e264c296734740dfc718f2f9a54e2e8f..471f17c692db18d7c7a42f15234f504696ee2ea2 100644 (file)
--- a/src/southbridge/intel/sch/ide.c
+++ b/src/southbridge/intel/sch/ide.c
@@ -5,8 +5,7 @@
  *
  * This program is free software; you can redistribute it and/or
  * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
+ * published by the Free Software Foundation; version 2 of the License.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
@@ -24,45 +23,39 @@
 #include <device/pci_ids.h>
 
 /* PCI Configuration Space (D31:F1): IDE */
-#define   INTR_LN                      0x3c
-#define   IDE_TIM_PRI          0x80    /* IDE timings, primary */
+#define INTR_LN                        0x3c
+#define IDE_TIM_PRI            0x80    /* IDE timings, primary */
+
+extern int sch_port_access_read(int port, int reg, int bytes);
 
-extern int sch_port_access_read(int port,int reg, int bytes);
 static void ide_init(struct device *dev)
 {
-       u32 ideTimingConfig;
-       u32 reg32;
+       u32 ideTimingConfig, reg32;
+
        printk(BIOS_DEBUG, "sch_ide: initializing... ");
 
        reg32 = pci_read_config32(dev, PCI_COMMAND);
-       pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_IO | PCI_COMMAND_MASTER);
-
-       /* Program the clock */
+       pci_write_config32(dev, PCI_COMMAND,
+                          reg32 | PCI_COMMAND_IO | PCI_COMMAND_MASTER);
 
-       if (sch_port_access_read(5,3,4) & (1<<3))
-       {
-               /*533MHz
-               Read PCI MC register*/
+       /* Program the clock. */
+       if (sch_port_access_read(5, 3, 4) & (1 << 3)) {
+               /* 533MHz, Read PCI MC register */
                reg32 = pci_read_config32(dev, 0x60);
-               pci_write_config32(dev,0x60,reg32 | 1);
-       }
-       else
-       {
-               /*400MHz*/
+               pci_write_config32(dev, 0x60, reg32 | 1);
+       } else {
+               /* 400MHz */
                reg32 = pci_read_config32(dev, 0x60);
-               reg32 &=~(1);
-               pci_write_config32(dev,0x60,reg32);
+               reg32 &= ~1;
+               pci_write_config32(dev, 0x60, reg32);
        }
 
-
-       /* Enable primary IDE interface.
-       80=04 81=00 82=02 83=80
-       */
+       /* Enable primary IDE interface. 80=04 81=00 82=02 83=80 */
        ideTimingConfig = 0x80020000;
        printk(BIOS_DEBUG, "IDE0 ");
        pci_write_config32(dev, IDE_TIM_PRI, ideTimingConfig);
 
-       /* Set Interrupt Line */
+       /* Set Interrupt Line. */
        /* Interrupt Pin is set by D31IP.PIP */
        printk(BIOS_DEBUG, "\n");
 }
@@ -71,7 +64,7 @@ static void ide_set_subsystem(device_t dev, unsigned vendor, unsigned device)
 {
        if (!vendor || !device) {
                pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
-                               pci_read_config32(dev, PCI_VENDOR_ID));
+                                  pci_read_config32(dev, PCI_VENDOR_ID));
        } else {
                pci_write_config32(dev, PCI_SUBSYSTEM_VENDOR_ID,
                                ((device & 0xffff) << 16) | (vendor & 0xffff));
@@ -79,7 +72,7 @@ static void ide_set_subsystem(device_t dev, unsigned vendor, unsigned device)
 }
 
 static struct pci_operations ide_pci_ops = {
-       .set_subsystem    = ide_set_subsystem,
+       .set_subsystem = ide_set_subsystem,
 };
 
 static struct device_operations ide_ops = {