#endif
}
+#if 0
static void rs780_nb_gfx_dev_table(device_t nb_dev, device_t dev)
{
/* NB_InitGFXStraps */
#if (CONFIG_GFXUMA == 1)
extern uint64_t uma_memory_size;
// bits 7-9: aperture size
- // 0-7: 128mb, 256mb, 64mb, 32mb, 512mb, 1g, 2g, 4g
+ // 0-7: 128mb, 256mb, 64mb, 32mb, 512mb, 1g, 2g, 4g
if (uma_memory_size == 0x02000000) romstrap2 |= 3 << 7;
if (uma_memory_size == 0x04000000) romstrap2 |= 2 << 7;
if (uma_memory_size == 0x08000000) romstrap2 |= 0 << 7;
printk(BIOS_INFO, "GC is accessible from now on.\n");
}
+#endif
/***********************************************
* 0:00.0 NBCFG :
case 1: /* bus0, dev1, APC. */
printk(BIOS_INFO, "Bus-0, Dev-1, Fun-0.\n");
+#if 0
rs780_nb_gfx_dev_table(nb_dev, dev);
+#endif
break;
case 2: /* bus0, dev2,3, two GFX */
case 3:
printk(BIOS_INFO, "Bus-0, Dev-2,3, Fun-0. enable=%d\n", dev->enabled);
set_nbmisc_enable_bits(nb_dev, 0x0c, 1 << dev_ind,
(dev->enabled ? 0 : 1) << dev_ind);
+#if 0
if (dev->enabled)
rs780_gfx_init(nb_dev, dev, dev_ind);
+#endif
break;
case 4: /* bus0, dev4-7, four GPPSB */
case 5:
default:
printk(BIOS_DEBUG, "unknown dev: %s\n", dev_path(dev));
}
+ printk(BIOS_INFO, "rs780_enable: done\n");
}
struct chip_operations southbridge_amd_rs780_ops = {