}
dev = alloc_dev(bus, &dummy.path);
} else {
- printk(BIOS_INFO, "%s: ohai, non-dummy stuff!\n", __func__);
/*
* Enable/disable the device. Once we have found the device-
* specific operations this operations we will disable the
* it may be absent and enable_dev() must cope.
*/
/* Run the magic enable sequence for the device. */
- printk(BIOS_INFO, "%s: before enable! 0x%08x\n", __func__, (unsigned int) dev->chip_ops->enable_dev);
- if (dev->chip_ops && dev->chip_ops->enable_dev) {
- printk(BIOS_INFO, "%s: we're going to call enable stuff?\n", __func__);
+ if (dev->chip_ops && dev->chip_ops->enable_dev)
dev->chip_ops->enable_dev(dev);
- }
- printk(BIOS_INFO, "%s: before read!\n", __func__);
/* Now read the vendor and device ID. */
id = pci_read_config32(dev, PCI_VENDOR_ID);
- printk(BIOS_INFO, "%s: after read: 0x%08x\n", __func__, id);
/*
* If the device does not have a PCI ID disable it. Possibly
"found, disabling it.\n", dev_path(dev));
dev->enabled = 0;
}
- printk(BIOS_INFO, "%s: non-static stuff!\n", __func__);
return dev;
}
}
"devfn %x\n", min_devfn, max_devfn);
printk(BIOS_ERR, "PCI: pci_scan_bus upper limit too big. "
"Using 0xff.\n");
- max_devfn=0xff;
+ max_devfn=0x08;
}
old_devices = bus->children;
if ((PCI_FUNC(devfn) == 0x00) && (!dev
|| (dev->enabled && ((dev->hdr_type & 0x80) != 0x80)))) {
devfn += 0x07;
- printk(BIOS_INFO, "%s: ohai, +7\n", __func__);
}
- printk(BIOS_INFO, "\n");
}
post_code(0x25);
void set_pcie_reset(void);
void enable_int_gfx(void);
+/* GPIO6. */
+void enable_int_gfx(void)
+{
+ volatile u8 *gpio_reg;
+
+#ifdef UNUSED_CODE
+ RWPMIO(SB_PMIOA_REGEA, AccWidthUint8, ~(BIT0), BIT0); /* Disable the PCIB */
+ RWPMIO(SB_PMIOA_REGF6, AccWidthuint8, ~(BIT0), BIT0); /* Disable Gec */
+#endif
+ /* make sure the MMIO(fed80000) is accessible */
+ RWPMIO(SB_PMIOA_REG24, AccWidthUint8, ~(BIT0), BIT0);
+
+ gpio_reg = (volatile u8 *)ACPI_MMIO_BASE + 0xD00; /* IoMux Register */
+
+ *(gpio_reg + 0x6) = 0x1; /* Int_vga_en */
+ *(gpio_reg + 170) = 0x1; /* gpio_gate */
+
+ gpio_reg = (volatile u8 *)ACPI_MMIO_BASE + 0x100; /* GPIO Registers */
+
+ *(gpio_reg + 0x6) = 0x8;
+ *(gpio_reg + 170) = 0x0;
+}
void set_pcie_dereset()
{
printk(BIOS_INFO, "Mainboard ASUS M5A99X-EVO Enable. dev=0x%p\n", dev);
+#if (CONFIG_GFXUMA == 1)
+ msr_t msr, msr2;
+
+ /* TOP_MEM: the top of DRAM below 4G */
+ msr = rdmsr(TOP_MEM);
+ printk
+ (BIOS_INFO, "%s, TOP MEM: msr.lo = 0x%08x, msr.hi = 0x%08x\n",
+ __func__, msr.lo, msr.hi);
+
+ /* TOP_MEM2: the top of DRAM above 4G */
+ msr2 = rdmsr(TOP_MEM2);
+ printk
+ (BIOS_INFO, "%s, TOP MEM2: msr2.lo = 0x%08x, msr2.hi = 0x%08x\n",
+ __func__, msr2.lo, msr2.hi);
+
+ /* refer to UMA Size Consideration in 780 BDG. */
+ switch (msr.lo) {
+ case 0x10000000: /* 256M system memory */
+ uma_memory_size = 0x4000000; /* 64M recommended UMA */
+ break;
+
+ case 0x20000000: /* 512M system memory */
+ uma_memory_size = 0x8000000; /* 128M recommended UMA */
+ break;
+
+ default: /* 1GB and above system memory */
+ uma_memory_size = 0x10000000; /* 256M recommended UMA */
+ break;
+ }
+
+ uma_memory_base = msr.lo - uma_memory_size; /* TOP_MEM1 */
+ printk(BIOS_INFO, "%s: uma size 0x%08llx, memory start 0x%08llx\n",
+ __func__, uma_memory_size, uma_memory_base);
+
+ /* TODO: TOP_MEM2 */
+#else
uma_memory_size = 0x8000000; /* 128M recommended UMA */
uma_memory_base = 0x38000000; /* 1GB system memory supposed */
+#endif
+ printk (BIOS_INFO, "%s, w00t?!\n", __func__);
+
+ set_pcie_dereset();
+#if 0
+ enable_int_gfx();
+#endif
+ printk (BIOS_INFO, "%s, cya enable?!\n", __func__);
}
int add_mainboard_resources(struct lb_memory *mem)
{
+ /* UMA is removed from system memory in the northbridge code, but
+ * in some circumstances we want the memory mentioned as reserved.
+ */
+#if (CONFIG_GFXUMA == 1)
+ printk(BIOS_INFO, "uma_memory_start=0x%llx, uma_memory_size=0x%llx \n",
+ uma_memory_base, uma_memory_size);
+ lb_add_memory_range(mem, LB_MEM_RESERVED, uma_memory_base,
+ uma_memory_size);
+#endif
return 0;
}