#endif
#include <cpu/amd/amdfam10_sysconf.h>
+#if CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800
+#include <sb_cimx.h>
+#elif CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900
+#include <SbEarly.h>
+#endif
struct amdfam10_sysconf_t sysconf;
#endif
}
-#include "amdfam10_conf.c"
+#include "conf.c"
static void set_vga_enable_reg(u32 nodeid, u32 linkn)
{
{
// I want to put sb chain in bus 0 can I?
+ printk(BIOS_INFO, "%s: starting...\n", __func__);
u32 link_type;
int i;
link->cap = 0x80 + ((link_num&3) *0x20);
do {
link_type = pci_read_config32(devx, link->cap + 0x18);
+ printk(BIOS_INFO, "%s: link_type: 0x%08x\n", __func__, link_type);
} while(link_type & ConnectionPending);
if (!(link_type & LinkConnected)) {
return max;
}
do {
link_type = pci_read_config32(devx, link->cap + 0x18);
+ printk(BIOS_INFO, "%s: link_type: 0x%08x\n", __func__, link_type);
} while(!(link_type & InitComplete));
if (!(link_type & NonCoherent)) {
return max;
/* See if there is an available configuration space mapping
* register in function 1.
*/
+ printk(BIOS_INFO, "%s: before get_ht_c_index\n", __func__);
ht_c_index = get_ht_c_index(nodeid, link_num, &sysconf);
+ printk(BIOS_INFO, "%s: after get_ht_c_index\n", __func__);
#if CONFIG_EXT_CONF_SUPPORT == 0
if(ht_c_index>=4) return max;
/* set the config map space */
+ printk(BIOS_INFO, "%s: before set_config_map_reg\n", __func__);
set_config_map_reg(nodeid, link_num, ht_c_index, link->secondary, link->subordinate, sysconf.segbit, sysconf.nodes);
+ printk(BIOS_INFO, "%s: after set_config_map_reg\n", __func__);
/* Now we can scan all of the subordinate busses i.e. the
* chain on the hypertranport link
else
max_devfn = (0x1f<<3) | 7;
+ printk(BIOS_INFO, "%s: before hypertransport_scan_chain\n", __func__);
+ /* HERE. ZOMG */
max = hypertransport_scan_chain(link, 0, max_devfn, max, ht_unitid_base, offset_unitid);
+ printk(BIOS_INFO, "%s: after hypertransport_scan_chain\n", __func__);
/* We know the number of busses behind this bridge. Set the
* subordinate bus number to it's real value
*/
if(ht_c_index>3) { // clear the extend reg
+ printk(BIOS_INFO, "%s: before clear_config_map_reg\n", __func__);
clear_config_map_reg(nodeid, link_num, ht_c_index, (max+1)>>sysconf.segbit, (link->subordinate)>>sysconf.segbit, sysconf.nodes);
+ printk(BIOS_INFO, "%s: after clear_config_map_reg\n", __func__);
}
link->subordinate = max;
+ printk(BIOS_INFO, "%s: before set_config_map_reg\n", __func__);
set_config_map_reg(nodeid, link_num, ht_c_index, link->secondary, link->subordinate, sysconf.segbit, sysconf.nodes);
+ printk(BIOS_INFO, "%s: after set_config_map_reg\n", __func__);
sysconf.ht_c_num++;
{
sysconf.hcdn_reg[ht_c_index] = temp;
}
+ printk(BIOS_INFO, "%s: before store_ht_c_conf_bus\n", __func__);
store_ht_c_conf_bus(nodeid, link_num, ht_c_index, link->secondary, link->subordinate, &sysconf);
+ printk(BIOS_INFO, "%s: after store_ht_c_conf_bus\n", __func__);
+ printk(BIOS_INFO, "%s: done.\n", __func__);
return max;
}
unsigned sblink = sysconf.sblk;
unsigned offset_unitid = 0;
+ printk(BIOS_INFO, "%s: starting...\n", __func__);
+
nodeid = amdfam10_nodeid(dev);
// Put sb chain in bus 0
#if ((CONFIG_HT_CHAIN_UNITID_BASE != 1) || (CONFIG_HT_CHAIN_END_UNITID_BASE != 0x20))
offset_unitid = 1;
#endif
- for (link = dev->link_list; link; link = link->next)
+ for (link = dev->link_list; link; link = link->next) {
+ printk(BIOS_INFO, "%s: link: %p\n", __func__, link);
if (link->link_num == sblink)
max = amdfam10_scan_chain(dev, nodeid, link, sblink, sblink, max, offset_unitid ); // do sb ht chain at first, in case s2885 put sb chain (8131/8111) on link2, but put 8151 on link0
+ }
}
#endif
#endif
for(link = dev->link_list; link; link = link->next) {
+ printk(BIOS_INFO, "%s: link2: %p\n", __func__, link);
#if CONFIG_SB_HT_CHAIN_ON_BUS0 > 0
if( (nodeid == 0) && (sblink == link->link_num) ) continue; //already done
#endif
max = amdfam10_scan_chain(dev, nodeid, link, link->link_num, sblink, max, offset_unitid);
}
+ printk(BIOS_INFO, "%s: done.\n", __func__);
return max;
}
}
/**
- *
* I tried to reuse the resource allocation code in amdfam10_set_resource()
- * but it is too diffcult to deal with the resource allocation magic.
+ * but it is too difficult to deal with the resource allocation magic.
*/
-#if CONFIG_CONSOLE_VGA_MULTI == 1
-extern device_t vga_pri; // the primary vga device, defined in device.c
-#endif
static void amdfam10_create_vga_resource(device_t dev, unsigned nodeid)
{
* we only deal with the 'first' vga card */
for (link = dev->link_list; link; link = link->next) {
if (link->bridge_ctrl & PCI_BRIDGE_CTL_VGA) {
-#if CONFIG_CONSOLE_VGA_MULTI == 1
+#if CONFIG_MULTIPLE_VGA_ADAPTERS == 1
+ extern device_t vga_pri; // the primary vga device, defined in device.c
printk(BIOS_DEBUG, "VGA: vga_pri bus num = %d bus range [%d,%d]\n", vga_pri->bus->secondary,
link->secondary,link->subordinate);
/* We need to make sure the vga_pri is under the link */
resource->flags = IORESOURCE_MEM;
}
#endif
+#if CONFIG_MMCONF_SUPPORT
+ struct resource *res = new_resource(dev, 0xc0010058);
+ res->base = CONFIG_MMCONF_BASE_ADDRESS;
+ res->size = CONFIG_MMCONF_BUS_NUMBER * 4096*256;
+ res->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
+ IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
+#endif
}
-static void ram_resource(device_t dev, unsigned long index,
- resource_t basek, resource_t sizek)
-{
- struct resource *resource;
-
- if (!sizek) {
- return;
- }
- resource = new_resource(dev, index);
- resource->base = basek << 10;
- resource->size = sizek << 10;
- resource->flags = IORESOURCE_MEM | IORESOURCE_CACHEABLE | \
- IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
-}
-
-static void tolm_test(void *gp, struct device *dev, struct resource *new)
-{
- struct resource **best_p = gp;
- struct resource *best;
- best = *best_p;
- if (!best || (best->base > new->base)) {
- best = new;
- }
- *best_p = best;
-}
-
-static u32 find_pci_tolm(struct bus *bus, u32 tolm)
+static u32 my_find_pci_tolm(struct bus *bus, u32 tolm)
{
struct resource *min;
min = 0;
#endif
#if CONFIG_WRITE_HIGH_TABLES==1
-#define HIGH_TABLES_SIZE 64 // maximum size of high tables in KB
-extern uint64_t high_tables_base, high_tables_size;
+#include <cbmem.h>
+#endif
+
+#if CONFIG_GFXUMA == 1
+extern uint64_t uma_memory_base, uma_memory_size;
+
+static void add_uma_resource(struct device *dev, int index)
+{
+ struct resource *resource;
+
+ printk(BIOS_DEBUG, "Adding UMA memory area\n");
+ resource = new_resource(dev, index);
+ resource->base = (resource_t) uma_memory_base;
+ resource->size = (resource_t) uma_memory_size;
+ resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
+ IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
+}
#endif
static void amdfam10_domain_set_resources(device_t dev)
pci_tolm = 0xffffffffUL;
for(link = dev->link_list; link; link = link->next) {
- pci_tolm = find_pci_tolm(link, pci_tolm);
+ pci_tolm = my_find_pci_tolm(link, pci_tolm);
}
// FIXME handle interleaved nodes. If you fix this here, please fix
#if CONFIG_WRITE_HIGH_TABLES==1
if (high_tables_base==0) {
/* Leave some space for ACPI, PIRQ and MP tables */
- high_tables_base = (mmio_basek - HIGH_TABLES_SIZE) * 1024;
- high_tables_size = HIGH_TABLES_SIZE * 1024;
- printk(BIOS_DEBUG, " split: %dK table at =%08llx\n", HIGH_TABLES_SIZE,
- high_tables_base);
+#if CONFIG_GFXUMA == 1
+ high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE;
+#else
+ high_tables_base = (mmio_basek * 1024) - HIGH_MEMORY_SIZE;
+#endif
+ high_tables_size = HIGH_MEMORY_SIZE;
+ printk(BIOS_DEBUG, " split: %dK table at =%08llx\n",
+ HIGH_MEMORY_SIZE / 1024, high_tables_base);
}
#endif
}
sizek -= (4*1024*1024 - mmio_basek);
}
}
+
+#if CONFIG_GFXUMA == 1
+ /* Deduct uma memory before reporting because
+ * this is what the mtrr code expects */
+ sizek -= uma_memory_size / 1024;
+#endif
ram_resource(dev, (idx | i), basek, sizek);
idx += 0x10;
#if CONFIG_WRITE_HIGH_TABLES==1
i, mmio_basek, basek, limitk);
if (high_tables_base==0) {
/* Leave some space for ACPI, PIRQ and MP tables */
- high_tables_base = (limitk - HIGH_TABLES_SIZE) * 1024;
- high_tables_size = HIGH_TABLES_SIZE * 1024;
+#if CONFIG_GFXUMA == 1
+ high_tables_base = uma_memory_base - HIGH_MEMORY_SIZE;
+#else
+ high_tables_base = (limitk * 1024) - HIGH_MEMORY_SIZE;
+#endif
+ high_tables_size = HIGH_MEMORY_SIZE;
}
#endif
}
+#if CONFIG_GFXUMA == 1
+ add_uma_resource(dev, 7);
+#endif
+
for(link = dev->link_list; link; link = link->next) {
if (link->children) {
assign_resources(link);
int disable_siblings;
unsigned ApicIdCoreIdSize;
+ printk(BIOS_INFO, "%s: starting...\n", __func__);
nb_cfg_54 = 0;
ApicIdCoreIdSize = (cpuid_ecx(0x80000008)>>12 & 0xf);
if(ApicIdCoreIdSize) {
} //j
}
+ printk(BIOS_INFO, "%s: done.\n", __func__);
return max;
}
static void cpu_bus_init(device_t dev)
{
initialize_cpus(dev->link_list);
+#if CONFIG_SOUTHBRIDGE_AMD_CIMX_SB800 || CONFIG_SOUTHBRIDGE_AMD_CIMX_SB900
+ sb_After_Pci_Init();
+ sb_Mid_Post_Init();
+#endif
}
static void cpu_bus_noop(device_t dev)
static void cpu_bus_read_resources(device_t dev)
{
-#if CONFIG_MMCONF_SUPPORT
- struct resource *resource = new_resource(dev, 0xc0010058);
- resource->base = CONFIG_MMCONF_BASE_ADDRESS;
- resource->size = CONFIG_MMCONF_BUS_NUMBER * 4096*256;
- resource->flags = IORESOURCE_MEM | IORESOURCE_RESERVE |
- IORESOURCE_FIXED | IORESOURCE_STORED | IORESOURCE_ASSIGNED;
-#endif
}
static void cpu_bus_set_resources(device_t dev)
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