This patch unifies the use of config options in v2 to all start with CONFIG_

[coreboot.git] / src / mainboard / supermicro / h8dme / cache_as_ram_auto.c

diff --git a/src/mainboard/supermicro/h8dme/cache_as_ram_auto.c b/src/mainboard/supermicro/h8dme/cache_as_ram_auto.c
index a71de8428c5a47f0297336312e897f0c0d994f51..606556ba73c246cf9eed9520de4cfa643c6925bc 100644 (file)
--- a/src/mainboard/supermicro/h8dme/cache_as_ram_auto.c
+++ b/src/mainboard/supermicro/h8dme/cache_as_ram_auto.c
@@ -35,7 +35,7 @@
 //if we want to wait for core1 done before DQS training, set it to 0
 #define K8_SET_FIDVID_CORE0_ONLY 1
 
-#if K8_REV_F_SUPPORT == 1
+#if CONFIG_K8_REV_F_SUPPORT == 1
 #define K8_REV_F_SUPPORT_F0_F1_WORKAROUND 0
 #endif
 
@@ -53,7 +53,7 @@
 // for enable the FAN
 #include "southbridge/nvidia/mcp55/mcp55_early_smbus.c"
 
-#if USE_FAILOVER_IMAGE==0
+#if CONFIG_USE_FAILOVER_IMAGE==0
 #include "pc80/serial.c"
 #include "arch/i386/lib/console.c"
 #include "ram/ramtest.c"
@@ -72,7 +72,7 @@
 #include "superio/winbond/w83627hf/w83627hf_early_serial.c"
 #include "superio/winbond/w83627hf/w83627hf_early_init.c"
 
-#if USE_FAILOVER_IMAGE==0
+#if CONFIG_USE_FAILOVER_IMAGE==0
 
 #include "cpu/x86/bist.h"
 
@@ -194,7 +194,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 
 #endif
 
-#if ((HAVE_FAILOVER_BOOT==1) && (USE_FAILOVER_IMAGE == 1)) || ((HAVE_FAILOVER_BOOT==0) && (USE_FALLBACK_IMAGE == 1))
+#if ((CONFIG_HAVE_FAILOVER_BOOT==1) && (CONFIG_USE_FAILOVER_IMAGE == 1)) || ((CONFIG_HAVE_FAILOVER_BOOT==0) && (CONFIG_USE_FALLBACK_IMAGE == 1))
 
 #include "southbridge/nvidia/mcp55/mcp55_enable_rom.c"
 #include "northbridge/amd/amdk8/early_ht.c"
@@ -263,7 +263,7 @@ normal_image:
            );
 
       fallback_image:
-#if HAVE_FAILOVER_BOOT==1
+#if CONFIG_HAVE_FAILOVER_BOOT==1
        __asm__ volatile ("jmp __fallback_image":       /* outputs */
                          :"a" (bist), "b"(cpu_init_detectedx)  /* inputs */
            )
@@ -275,14 +275,14 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
 
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
-#if HAVE_FAILOVER_BOOT==1
-#if USE_FAILOVER_IMAGE==1
+#if CONFIG_HAVE_FAILOVER_BOOT==1
+#if CONFIG_USE_FAILOVER_IMAGE==1
        failover_process(bist, cpu_init_detectedx);
 #else
        real_main(bist, cpu_init_detectedx);
 #endif
 #else
-#if USE_FALLBACK_IMAGE == 1
+#if CONFIG_USE_FALLBACK_IMAGE == 1
        failover_process(bist, cpu_init_detectedx);
 #endif
        real_main(bist, cpu_init_detectedx);
@@ -293,7 +293,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 #define RC0 (2<<8)
 #define RC1 (1<<8)
 
-#if USE_FAILOVER_IMAGE==0
+#if CONFIG_USE_FAILOVER_IMAGE==0
 
 void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
@@ -315,7 +315,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
        };
 
        struct sys_info *sysinfo =
-           (DCACHE_RAM_BASE + DCACHE_RAM_SIZE - DCACHE_RAM_GLOBAL_VAR_SIZE);
+           (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE - CONFIG_DCACHE_RAM_GLOBAL_VAR_SIZE);
 
        int needs_reset = 0;
        unsigned bsp_apicid = 0;
@@ -326,7 +326,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
        pnp_enter_ext_func_mode(SERIAL_DEV);
        pnp_write_config(SERIAL_DEV, 0x24, 0x84 | (1 << 6));
-       w83627hf_enable_dev(SERIAL_DEV, TTYS0_BASE);
+       w83627hf_enable_dev(SERIAL_DEV, CONFIG_TTYS0_BASE);
        pnp_exit_ext_func_mode(SERIAL_DEV);
 
        uart_init();
@@ -347,7 +347,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
        print_debug_hex8(bsp_apicid);
        print_debug("\r\n");
 
-#if MEM_TRAIN_SEQ == 1
+#if CONFIG_MEM_TRAIN_SEQ == 1
        set_sysinfo_in_ram(0);  // in BSP so could hold all ap until sysinfo is in ram
 #endif
 /*     dump_smbus_registers(); */