This patch unifies the use of config options in v2 to all start with CONFIG_

[coreboot.git] / src / mainboard / newisys / khepri / cache_as_ram_auto.c

diff --git a/src/mainboard/newisys/khepri/cache_as_ram_auto.c b/src/mainboard/newisys/khepri/cache_as_ram_auto.c
index 6adb906e336e344561dbd003d169dc532733d679..2affa7fbb58e458c62484f56763959bbce8b726d 100644 (file)
--- a/src/mainboard/newisys/khepri/cache_as_ram_auto.c
+++ b/src/mainboard/newisys/khepri/cache_as_ram_auto.c
@@ -108,7 +108,7 @@ static inline int spd_read_byte(unsigned device, unsigned address)
 #include "cpu/amd/model_fxx/init_cpus.c"
 
 
-#if USE_FALLBACK_IMAGE == 1
+#if CONFIG_USE_FALLBACK_IMAGE == 1
 
 #include "southbridge/amd/amd8111/amd8111_enable_rom.c"
 #include "northbridge/amd/amdk8/early_ht.c"
@@ -164,7 +164,7 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx);
 void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
 {
 
-#if USE_FALLBACK_IMAGE == 1
+#if CONFIG_USE_FALLBACK_IMAGE == 1
         failover_process(bist, cpu_init_detectedx);
 #endif
         real_main(bist, cpu_init_detectedx);
@@ -194,11 +194,11 @@ void real_main(unsigned long bist, unsigned long cpu_init_detectedx)
 
 //     post_code(0x32);
        
-       w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
+       w83627hf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
         uart_init();
         console_init();
 
-//     dump_mem(DCACHE_RAM_BASE+DCACHE_RAM_SIZE-0x200, DCACHE_RAM_BASE+DCACHE_RAM_SIZE);
+//     dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
        
        /* Halt if there was a built in self test failure */
        report_bist_failure(bist);