We define IO_APIC_ADDR in <arch/ioapic.h>, let's use it.

[coreboot.git] / src / mainboard / emulation / qemu-x86 / northbridge.c

diff --git a/src/mainboard/emulation/qemu-x86/northbridge.c b/src/mainboard/emulation/qemu-x86/northbridge.c
index cca56204ab5ab36e353e11687e5932456ba62525..7a73ecff694cbbfa2006fd69fb692d8ce2015bdb 100644 (file)
--- a/src/mainboard/emulation/qemu-x86/northbridge.c
+++ b/src/mainboard/emulation/qemu-x86/northbridge.c
@@ -1,5 +1,6 @@
 #include <console/console.h>
 #include <arch/io.h>
+#include <arch/ioapic.h>
 #include <stdint.h>
 #include <device/device.h>
 #include <device/pci.h>
@@ -64,7 +65,7 @@ static void cpu_pci_domain_read_resources(struct device *dev)
        /* Reserve space for the IOAPIC.  This should be in the Southbridge,
         * but I couldn't tell which device to put it in. */
        res = new_resource(dev, 2);
-       res->base = 0xfec00000UL;
+       res->base = IO_APIC_ADDR;
        res->size = 0x100000UL;
        res->limit = 0xffffffffUL;
        res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED |