#include "cpu/x86/mtrr/earlymtrr.c"
#include <cpu/amd/mtrr.h>
#include "northbridge/amd/amdfam10/setup_resource_map.c"
-#include "southbridge/amd/rs780/early_setup.c"
+#include "nb_cimx.h"
#include <southbridge/amd/cimx/sb900/SbEarly.h>
#include <southbridge/amd/cimx/sb900/SbPlatform.h> /* SB OEM constants */
#include <southbridge/amd/cimx/sb900/smbus.h>
post_code(0x32);
- enable_rs780_dev8();
- // sb800_clk_output_48Mhz();
-
it8721f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
console_init();
printk(BIOS_DEBUG, "\n");
+ printk(BIOS_DEBUG, "zomg1\n");
+ sr56x0_rd890_disable_pcie_bridge();
+
+ printk(BIOS_DEBUG, "zomg2\n");
+ nb_Poweron_Init();
+ printk(BIOS_DEBUG, "zomg3\n");
+ nb_Ht_Init();
+ printk(BIOS_DEBUG, "zomg4\n");
+
// dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
post_code(0x38);
/* run _early_setup before soft-reset. */
+#if 0
rs780_early_setup();
+#endif
#if CONFIG_SET_FIDVID == 1
msr = rdmsr(0xc0010071);
printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
#endif
+#if 0
rs780_htinit();
+#endif
/* Reset for HT, FIDVID, PLL and errata changes to take affect. */
if (!warm_reset_detect(0)) {
// die("After MCT init before CAR disabled.");
+#if 0
rs780_before_pci_init();
+#endif
post_code(0x42);
post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.