select DIMM_REGISTERED
select QRANK_DIMM_SUPPORT
select NORTHBRIDGE_AMD_AMDFAM10
- select SOUTHBRIDGE_AMD_RS780
+ select NORTHBRIDGE_AMD_CIMX_RD890
select SOUTHBRIDGE_AMD_CIMX_SB900
select SUPERIO_ITE_IT8721F
select HAVE_BUS_CONFIG
+romstage-y += rd890_cfg.c
+
+ramstage-y += rd890_cfg.c
ramstage-y += reset.c
#SB800 CIMx share AGESA V5 lib code
AGESA_INC := -I$(AGESA_ROOT)/ \
-I$(AGESA_ROOT)/Include \
+ -I$(AGESA_ROOT)/Lib \
-I$(AGESA_ROOT)/Proc/IDS/ \
-I$(AGESA_ROOT)/Proc/CPU/ \
-I$(AGESA_ROOT)/Proc/CPU/Family
device pci_domain 0 on
subsystemid 0x1043 0x843e inherit #TODO: Set the correctly subsystem id.
chip northbridge/amd/amdfam10
- device pci 18.0 on # northbridge
- chip southbridge/amd/rs780
- device pci 0.0 on end # HT 0x9600
- device pci 2.0 on end # PCIE P2P bridge (external graphics) 0x9603
- device pci 3.0 off end # PCIE P2P bridge 0x960b
- device pci 4.0 on end # PCIE P2P bridge 0x9604 wireless
- device pci 5.0 off end # PCIE P2P bridge 0x9605
- device pci 6.0 off end # PCIE P2P bridge 0x9606
- device pci 7.0 off end # PCIE P2P bridge 0x9607
- device pci 8.0 off end # NB/SB Link P2P bridge
- device pci 9.0 on end # Ethernet
- device pci a.0 on end # Ethernet
- register "gppsb_configuration" = "4" # Configuration E
- register "gpp_configuration" = "3" # Configuration D
- register "port_enable" = "0x6f6"
- register "gfx_dev2_dev3" = "0"
- register "gfx_dual_slot" = "0"
- register "gfx_lane_reversal" = "0"
- register "gfx_compliance" = "0"
- register "gfx_reconfiguration" = "1"
- register "gfx_link_width" = "0"
- register "gfx_tmds" = "1"
- register "gfx_pcie_config" = "3" # 1x8 GFX on Lanes 8-15
- register "gfx_ddi_config" = "1" # Lanes 0-3 DDI_SL
- end
+
+ device pci 18.0 on end # Link 0
+ device pci 18.0 on # Link 1, IO-HUB on socket0 link 2(internal Node0 Link 1)
+ chip northbridge/amd/cimx/rd890 # North Bridge PCI side of HT Root complex
+ device pci 0.0 on end # HT Root Complex
+ device pci 0.1 off end # CLKCONFIG
+ device pci 2.0 on end # GPP1 Port0
+ device pci 3.0 off end # GPP1 Port1
+ device pci 4.0 off end # GPP3a Port0
+ device pci 5.0 off end # GPP3a Port1
+ device pci 6.0 off end # GPP3a Port2
+ device pci 7.0 off end # GPP3a Port3
+ device pci 8.0 off end # NB/SB Link P2P bridge, should be hidden at boot time
+ device pci 9.0 off end # GPP3a Port4
+ device pci a.0 off end # GPP3a Port5
+ device pci b.0 off end # GPP2 Port0 (Not for sr5650)
+ device pci c.0 off end # GPP2 Port1 (Not for sr5650/sr5670)
+ device pci d.0 on end # GPP3b Port0 (Not for sr5650/sr5670) 0x5A1E, Intel 82576
+ register "gpp1_configuration" = "0" # Configuration 16:0 default
+ register "gpp2_configuration" = "1" # Configuration 8:8
+ register "gpp3a_configuration" = "2" # 2 Configuration 4:1:1:0:0:0, 11 Configuration 1:1:1:1:1:1
+ register "port_enable" = "0x2104"
+ end # northbridge/amd/cimx/rd890
chip southbridge/amd/cimx/sb900 # it is under NB/SB Link, but on the same pci bus
device pci 11.0 on end # SATA
device pci 12.0 on end # USB
* @brief South Bridge CIMx configuration
*
*/
+
+
+// RD890 stuff
+#define MAX_NB_COUNT 1
+#define IOMMU_SUPPORT_DISABLE // TODO: enable it
+
+/* TODO: hrm, that's dirty */
+#ifdef _AMD_SBPLATFORM_H_
void sb900_cimx_config(AMDSBCFG *sb_cfg);
void SbPowerOnInit_Config(AMDSBCFG *sb_cfg);
*
*/
u32 sb900_callout_entry(u32 func, u32 data, void* sb_cfg);
-
-
-
#endif
+#endif
+
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include "NbPlatform.h"
+#include "rd890_cfg.h"
+#include "northbridge/amd/cimx/rd890/chip.h"
+#include "nbInitializer.h"
+#include <string.h>
+#include <arch/ioapic.h>
+
+#ifndef __PRE_RAM__
+#include <device/device.h>
+extern void set_pcie_reset(void *config);
+extern void set_pcie_dereset(void *config);
+
+/**
+ * Platform dependent configuration at ramstage
+ */
+static void nb_platform_config(device_t nb_dev, AMD_NB_CONFIG *NbConfigPtr)
+{
+ u16 i;
+ PCIE_CONFIG *pPcieConfig = NbConfigPtr->pPcieConfig;
+ //AMD_NB_CONFIG_BLOCK *ConfigPtr = GET_BLOCK_CONFIG_PTR(NbConfigPtr);
+ struct northbridge_amd_cimx_rd890_config *rd890_info = NULL;
+ DEFAULT_PLATFORM_CONFIG(platform_config);
+
+ /* update the platform depentent configuration by devicetree */
+ rd890_info = nb_dev->chip_info;
+ platform_config.PortEnableMap = rd890_info->port_enable;
+ if (rd890_info->gpp1_configuration == 0) {
+ platform_config.Gpp1Config = GFX_CONFIG_AAAA;
+ } else if (rd890_info->gpp1_configuration == 1) {
+ platform_config.Gpp1Config = GFX_CONFIG_AABB;
+ }
+ if (rd890_info->gpp2_configuration == 0) {
+ platform_config.Gpp2Config = GFX_CONFIG_AAAA;
+ } else if (rd890_info->gpp2_configuration == 1) {
+ platform_config.Gpp2Config = GFX_CONFIG_AABB;
+ }
+ platform_config.Gpp3aConfig = rd890_info->gpp3a_configuration;
+
+ if (platform_config.Gpp1Config != 0) {
+ pPcieConfig->CoreConfiguration[0] = platform_config.Gpp1Config;
+ }
+ if (platform_config.Gpp2Config != 0) {
+ pPcieConfig->CoreConfiguration[1] = platform_config.Gpp2Config;
+ }
+ if (platform_config.Gpp3aConfig != 0) {
+ pPcieConfig->CoreConfiguration[2] = platform_config.Gpp3aConfig;
+ }
+
+ pPcieConfig->TempMmioBaseAddress = (UINT16)(platform_config.TemporaryMmio >> 20);
+ for (i = 0; i <= MAX_CORE_ID; i++) {
+ NbConfigPtr->pPcieConfig->CoreSetting[i].SkipConfiguration = OFF;
+ NbConfigPtr->pPcieConfig->CoreSetting[i].PerformanceMode = OFF;
+ }
+ for (i = MIN_PORT_ID; i <= MAX_PORT_ID; i++) {
+ NbConfigPtr->pPcieConfig->PortConfiguration[i].PortLinkMode = PcieLinkModeGen2;
+ }
+
+ for (i = MIN_PORT_ID; i <= MAX_PORT_ID; i++) {
+ if ((platform_config.PortEnableMap & (1 << i)) != 0) {
+ pPcieConfig->PortConfiguration[i].PortPresent = ON;
+ if ((platform_config.PortGen1Map & (1 << i)) != 0) {
+ pPcieConfig->PortConfiguration[i].PortLinkMode = PcieLinkModeGen1;
+ }
+ if ((platform_config.PortHotplugMap & (1 << i)) != 0) {
+ u16 j;
+ pPcieConfig->PortConfiguration[j].PortHotplug = ON; /* Enable Hotplug */
+ /* Set Hotplug descriptor info */
+ for (j = 0; j < 8; j++) {
+ u32 PortDescriptor;
+ PortDescriptor = platform_config.PortHotplugDescriptors[j];
+ if ((PortDescriptor & 0xF) == j) {
+ pPcieConfig->ExtPortConfiguration[j].PortHotplugDevMap = (PortDescriptor >> 4) & 3;
+ pPcieConfig->ExtPortConfiguration[j].PortHotplugByteMap = (PortDescriptor >> 6) & 1;
+ break;
+ }
+ }
+ }
+ }
+ }
+}
+#endif // __PRE_RAM__
+
+/**
+ * @brief Entry point of Northbridge CIMx callout/CallBack
+ *
+ * prototype AGESA_STATUS (*CALLOUT_ENTRY) (UINT32 Param1, UINTN Param2, VOID* ConfigPtr);
+ *
+ * @param[in] u32 func Northbridge CIMx CallBackId
+ * @param[in] u32 data Northbridge Input Data.
+ * @param[in] AMD_NB_CONFIG *config Northbridge configuration structure pointer.
+ *
+ */
+static u32 rd890_callout_entry(u32 func, u32 data, void *config)
+{
+ u32 ret = 0;
+#ifndef __PRE_RAM__
+ device_t nb_dev = (device_t)data;
+#endif
+ AMD_NB_CONFIG *nbConfigPtr = (AMD_NB_CONFIG*)config;
+
+ switch (func) {
+ case PHCB_AmdPortTrainingCompleted:
+ break;
+
+ case PHCB_AmdPortResetDeassert:
+#ifndef __PRE_RAM__
+ set_pcie_dereset(config);
+#endif
+ break;
+
+ case PHCB_AmdPortResetAssert:
+#ifndef __PRE_RAM__
+ set_pcie_reset(config);
+#endif
+ break;
+
+ case PHCB_AmdPortResetSupported:
+ break;
+ case PHCB_AmdGeneratePciReset:
+ break;
+ case PHCB_AmdGetExclusionTable:
+ break;
+ case PHCB_AmdAllocateBuffer:
+ break;
+ case PHCB_AmdUpdateApicInterruptMapping:
+ break;
+ case PHCB_AmdFreeBuffer:
+ break;
+ case PHCB_AmdLocateBuffer:
+ break;
+ case PHCB_AmdReportEvent:
+ break;
+ case PHCB_AmdPcieAsmpInfo:
+ break;
+
+ case CB_AmdSetNbPorConfig:
+ break;
+ case CB_AmdSetHtConfig:
+ /*TODO: different HT path and deempasis for each NB */
+ nbConfigPtr->pHtConfig->NbTransmitterDeemphasis = DEFAULT_HT_DEEMPASIES;
+
+ break;
+ case CB_AmdSetPcieEarlyConfig:
+#ifndef __PRE_RAM__
+ nb_platform_config(nb_dev, nbConfigPtr);
+#endif
+ break;
+
+ case CB_AmdSetEarlyPostConfig:
+ break;
+
+ case CB_AmdSetMidPostConfig:
+ nbConfigPtr->pNbConfig->IoApicBaseAddress = RD890_IOAPIC_ADDR;
+#ifndef IOMMU_SUPPORT_DISABLE //TODO enable iommu
+ /* SBIOS must alloc 16K memory for IOMMU MMIO */
+ UINT32 MmcfgBarAddress; //using default IOmmuBaseAddress
+ LibNbPciRead(nbConfigPtr->NbPciAddress.AddressValue | 0x1C,
+ AccessWidth32,
+ &MmcfgBarAddress,
+ nbConfigPtr);
+ MmcfgBarAddress &= ~0xf;
+ if (MmcfgBarAddress != 0) {
+ nbConfigPtr->IommuBaseAddress = MmcfgBarAddress;
+ }
+ nbConfigPtr->IommuBaseAddress = 0; //disable iommu
+#endif
+ break;
+
+ case CB_AmdSetLatePostConfig:
+ break;
+
+ case CB_AmdSetRecoveryConfig:
+ break;
+ }
+
+ return ret;
+}
+
+
+/**
+ * @brief North Bridge CIMx configuration
+ *
+ * should be called before exeucte CIMx function.
+ * this function will be called in romstage and ramstage.
+ */
+void rd890_cimx_config(AMD_NB_CONFIG_BLOCK *pConfig, NB_CONFIG *nbConfig, HT_CONFIG *htConfig, PCIE_CONFIG *pcieConfig)
+{
+ u16 i = 0;
+ PCI_ADDR PciAddress;
+ u32 val, sbNode, sbLink;
+
+ if (!pConfig) {
+ return;
+ }
+
+ memset(pConfig, 0, sizeof(AMD_NB_CONFIG_BLOCK));
+ for (i = 0; i < MAX_NB_COUNT; i++) {
+ pConfig->Northbridges[i].pNbConfig = &nbConfig[i];
+ pConfig->Northbridges[i].pHtConfig = &htConfig[i];
+ pConfig->Northbridges[i].pPcieConfig = &pcieConfig[i];
+ pConfig->Northbridges[i].ConfigPtr = &pConfig;
+ }
+
+ /* Initialize all NB structures */
+ AmdInitializer(pConfig);
+
+ pConfig->NumberOfNorthbridges = MAX_NB_COUNT - 1; /* Support limited to primary NB only located at 0:0:0 */
+ //pConfig->StandardHeader.ImageBasePtr = CIMX_B2_IMAGE_BASE_ADDRESS;
+ pConfig->StandardHeader.PcieBasePtr = (VOID *)PCIEX_BASE_ADDRESS;
+ pConfig->StandardHeader.CalloutPtr = &rd890_callout_entry;
+
+ /*
+ * PCI Address to Access NB. Depends on HT topology and configuration for multi NB platform.
+ * Always 0:0:0 on single NB platform.
+ */
+ pConfig->Northbridges[0].NbPciAddress.AddressValue = MAKE_SBDFO(0, 0x0, 0x0, 0x0, 0x0);
+
+ /* Set HT path to NB by SbNode and SbLink */
+ PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB, FUNC_0, 0x60);
+ LibNbPciRead(PciAddress.AddressValue, AccessWidth32, &val, &(pConfig->Northbridges[0]));
+ sbNode = (val >> 8) & 0x07;
+ PciAddress.AddressValue = MAKE_SBDFO(0, 0, CONFIG_CDB, FUNC_0, 0x64);
+ LibNbPciRead(PciAddress.AddressValue, AccessWidth32, &val, &(pConfig->Northbridges[0]));
+ sbLink = (val >> 8) & 0x07; //assum ganged
+ pConfig->Northbridges[0].NbHtPath.NodeID = sbNode;
+ pConfig->Northbridges[0].NbHtPath.LinkID = sbLink;
+ //TODO: other NBs
+
+#ifndef __PRE_RAM__
+ /* If temporrary MMIO enable set up CPU MMIO */
+ for (i = 0; i <= pConfig->NumberOfNorthbridges; i++) {
+ UINT32 MmioBase;
+ UINT32 LinkId;
+ UINT32 SubLinkId;
+ MmioBase = pConfig->Northbridges[i].pPcieConfig->TempMmioBaseAddress;
+ if (MmioBase != 0) {
+ LinkId = pConfig->Northbridges[i].NbHtPath.LinkID & 0xf;
+ SubLinkId = ((pConfig->Northbridges[i].NbHtPath.LinkID & 0xF0) == 0x20) ? 1 : 0;
+ /* Set Limit */
+ LibNbPciRMW(MAKE_SBDFO (0, 0, 0x18, 0x1, (i * 4) + 0x84),
+ AccessWidth32,
+ 0x0,
+ ((MmioBase << 12) + 0xF00) | (LinkId << 4) | (SubLinkId << 6),
+ &(pConfig->Northbridges[i]));
+ /* Set Base */
+ LibNbPciRMW(MAKE_SBDFO (0, 0, 0x18, 0x1, (i * 4) + 0x80),
+ AccessWidth32,
+ 0x0,
+ (MmioBase << 12) | 0x3,
+ &(pConfig->Northbridges[i]));
+ }
+ }
+#endif
+}
+
--- /dev/null
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2012 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef _RD890_CFG_H_
+#define _RD890_CFG_H_
+
+#include "NbPlatform.h"
+
+#define RD890_IOAPIC_ADDR 0xC8000000
+/* platform dependent configuration default value */
+
+/**
+ * Path from CPU to NB
+ * [0..7] - Node (0..8)
+ * [8..11] - Link (0..3)
+ * [12..15] - Sublink (1..2), If NB connected to full link than Sublink should be set to 0.
+ */
+#ifndef DEFAULT_HT_PATH
+#if CONFIG_CPU_AMD_AGESA_FAMILY10 == 1
+#define DEFAULT_HT_PATH {0x0, 0x3}
+#endif
+#if CONFIG_CPU_AMD_AGESA_FAMILY15 == 1
+#define DEFAULT_HT_PATH {0x0, 0x1}
+#endif
+#endif
+
+/**
+ * Bitmap of enabled ports on NB #0/1/2/3
+ * Bit[0] - Reserved
+ * Bit[1] - Reserved
+ * Bit[2] - Enable PCIe port 2
+ * Bit[3] - Enable PCIe port 3
+ * Bit[4] - Enable PCIe port 4
+ * Bit[5] - Enable PCIe port 5
+ * Bit[6] - Enable PCIe port 2
+ * Bit[7] - Enable PCIe port 7
+ * Bit[8] - Reserved
+ * Bit[9] - Enable PCIe port 9
+ * Bit[10]- Enable PCIe port 10
+ * Bit[11]- Enable PCIe port 11
+ * Bit[12]- Enable PCIe port 12
+ * Bit[13]- Enable PCIe port 13
+ * Example:
+ * port_enable = 0x14
+ * Port 2 and 4 enabled for training/initialization
+ */
+#ifndef DEFAULT_PORT_ENABLE_MAP
+#define DEFAULT_PORT_ENABLE_MAP 0x0014
+#endif
+
+/**
+ * Bitmap of ports that have slot or onboard device connected.
+ * Example force PCIe Gen1 supporton port 2 and 4 (DEFAULT_PORT_ENABLE_MAP = BIT2 | BIT4)
+ * #define DEFAULT_PORT_FORCE_GEN1 0x604
+ */
+#ifndef DEFAULT_PORT_FORCE_GEN1
+#define DEFAULT_PORT_FORCE_GEN1 0x0
+#endif
+
+/**
+ * Bitmap of ports that have server hotplug support
+ */
+#ifndef DEFAULT_HOTPLUG_SUPPORT
+#define DEFAULT_HOTPLUG_SUPPORT 0x0
+#endif
+
+#ifndef DEFAULT_HOTPLUG_DESCRIPTOR
+#define DEFAULT_HOTPLUG_DESCRIPTOR {0, 0, 0, 0, 0, 0, 0, 0}
+#endif
+
+#ifndef DEFAULT_TEMPMMIO_BASE_ADDRESS
+#define DEFAULT_TEMPMMIO_BASE_ADDRESS 0xD0000000
+#endif
+
+/**
+ * Default GPP1 core configuraton on NB #0/1/2/3.
+ * 2 x8 slot, GFX_CONFIG_AABB
+ * 1 x16 slot, GFX_CONFIG_AAAA
+ */
+#ifndef DEFAULT_GPP1_CONFIG
+#define DEFAULT_GPP1_CONFIG GFX_CONFIG_AABB
+#endif
+
+/**
+ * Default GPP2 core configuraton on NB #0/1/2/3.
+ * 2 x8 slot, GFX_CONFIG_AABB
+ * 1 x16 slot, GFX_CONFIG_AAAA
+ */
+#ifndef DEFAULT_GPP2_CONFIG
+#define DEFAULT_GPP2_CONFIG GFX_CONFIG_AABB
+#endif
+
+/**
+ * Default GPP3a core configuraton on NB #0/1/2/3.
+ * 4:2:0:0:0:0 - GPP_CONFIG_GPP420000, 0x1
+ * 4:1:1:0:0:0 - GPP_CONFIG_GPP411000, 0x2
+ * 2:2:2:0:0:0 - GPP_CONFIG_GPP222000, 0x3
+ * 2:2:1:1:0:0 - GPP_CONFIG_GPP221100, 0x4
+ * 2:1:1:1:1:0 - GPP_CONFIG_GPP211110, 0x5
+ * 1:1:1:1:1:1 - GPP_CONFIG_GPP111111, 0x6
+ */
+#ifndef DEFAULT_GPP3A_CONFIG
+#define DEFAULT_GPP3A_CONFIG GPP_CONFIG_GPP111111
+#endif
+
+
+/**
+ * Default HT Transmitter de-emphasis setting
+ */
+#ifndef DEFAULT_HT_DEEMPASIES
+#define DEFAULT_HT_DEEMPASIES 0x3
+#endif
+
+/**
+ * Default APIC nterrupt base for IOAPIC
+ */
+#ifndef DEFAULT_APIC_INTERRUPT_BASE
+#define DEFAULT_APIC_INTERRUPT_BASE 24
+#endif
+
+
+#define DEFAULT_PLATFORM_CONFIG(name) \
+ NB_PLATFORM_CONFIG name = { \
+ DEFAULT_PORT_ENABLE_MAP, \
+ DEFAULT_PORT_FORCE_GEN1, \
+ DEFAULT_HOTPLUG_SUPPORT, \
+ DEFAULT_HOTPLUG_DESCRIPTOR, \
+ DEFAULT_TEMPMMIO_BASE_ADDRESS, \
+ DEFAULT_GPP1_CONFIG, \
+ DEFAULT_GPP2_CONFIG, \
+ DEFAULT_GPP3A_CONFIG, \
+ DEFAULT_HT_DEEMPASIES, \
+ /*DEFAULT_HT_PATH,*/ \
+ DEFAULT_APIC_INTERRUPT_BASE, \
+ }
+
+/**
+ * Platform configuration
+ */
+typedef struct {
+ UINT16 PortEnableMap; ///< Bitmap of enabled ports
+ UINT16 PortGen1Map; ///< Bitmap of ports to disable Gen2
+ UINT16 PortHotplugMap; ///< Bitmap of ports support hotplug
+ UINT8 PortHotplugDescriptors[8];///< Ports Hotplug descriptors
+ UINT32 TemporaryMmio; ///< Temporary MMIO
+ UINT32 Gpp1Config; ///< Default PCIe GFX core configuration
+ UINT32 Gpp2Config; ///< Default PCIe GPP2 core configuration
+ UINT32 Gpp3aConfig; ///< Default PCIe GPP3a core configuration
+ UINT8 NbTransmitterDeemphasis; ///< HT transmitter de-emphasis level
+ // HT_PATH NbHtPath; ///< HT path to NB
+ UINT8 GlobalApicInterruptBase; ///< Global APIC interrupt base that is used in MADT table for IO APIC.
+} NB_PLATFORM_CONFIG;
+
+/**
+ * Bridge CIMx configuration
+ */
+void rd890_cimx_config(AMD_NB_CONFIG_BLOCK *pConfig, NB_CONFIG *nbConfig, HT_CONFIG *htConfig, PCIE_CONFIG *pcieConfig);
+
+#endif //_RD890_CFG_H_
#include "cpu/x86/mtrr/earlymtrr.c"
#include <cpu/amd/mtrr.h>
#include "northbridge/amd/amdfam10/setup_resource_map.c"
-#include "southbridge/amd/rs780/early_setup.c"
+#include "nb_cimx.h"
#include <southbridge/amd/cimx/sb900/SbEarly.h>
#include <southbridge/amd/cimx/sb900/SbPlatform.h> /* SB OEM constants */
#include <southbridge/amd/cimx/sb900/smbus.h>
post_code(0x32);
- enable_rs780_dev8();
- // sb800_clk_output_48Mhz();
-
it8721f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
uart_init();
console_init();
printk(BIOS_DEBUG, "\n");
+ printk(BIOS_DEBUG, "zomg1\n");
+ sr56x0_rd890_disable_pcie_bridge();
+
+ printk(BIOS_DEBUG, "zomg2\n");
+ nb_Poweron_Init();
+ printk(BIOS_DEBUG, "zomg3\n");
+ nb_Ht_Init();
+ printk(BIOS_DEBUG, "zomg4\n");
+
// dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);
post_code(0x38);
/* run _early_setup before soft-reset. */
+#if 0
rs780_early_setup();
+#endif
#if CONFIG_SET_FIDVID == 1
msr = rdmsr(0xc0010071);
printk(BIOS_DEBUG, "End FIDVIDMSR 0xc0010071 0x%08x 0x%08x \n", msr.hi, msr.lo);
#endif
+#if 0
rs780_htinit();
+#endif
/* Reset for HT, FIDVID, PLL and errata changes to take affect. */
if (!warm_reset_detect(0)) {
// die("After MCT init before CAR disabled.");
+#if 0
rs780_before_pci_init();
+#endif
post_code(0x42);
post_cache_as_ram(); // BSP switch stack to ram, copy then execute LB.
projects / coreboot.git / commitdiff