* Set USBDEBUG_DEFAULT_PORT in all southbridges and use that value

[coreboot.git] / src / mainboard / asrock / 939a785gmh / romstage.c

diff --git a/src/mainboard/asrock/939a785gmh/romstage.c b/src/mainboard/asrock/939a785gmh/romstage.c
index ce79e0d204ddf450bcd71577d180322fba11ccea..25822d9e566df75adb51744db707ec6c2e985570 100644 (file)
--- a/src/mainboard/asrock/939a785gmh/romstage.c
+++ b/src/mainboard/asrock/939a785gmh/romstage.c
@@ -160,11 +160,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        w83627dhg_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
        uart_init();
 
-#if CONFIG_USBDEBUG
-       sb7xx_51xx_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
-       early_usbdebug_init();
-#endif
-
        console_init();
 
        /* Halt if there was a built in self test failure */