* Set USBDEBUG_DEFAULT_PORT in all southbridges and use that value

[coreboot.git] / src / mainboard / amd / tilapia_fam10 / romstage.c

diff --git a/src/mainboard/amd/tilapia_fam10/romstage.c b/src/mainboard/amd/tilapia_fam10/romstage.c
index fc9d611bbaefef6c411aa51b2ee69d8444b2ef81..ce24f03f715ac05439254dfc7886e6272458ebd4 100644 (file)
--- a/src/mainboard/amd/tilapia_fam10/romstage.c
+++ b/src/mainboard/amd/tilapia_fam10/romstage.c
@@ -105,13 +105,7 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
        it8718f_enable_serial(0, CONFIG_TTYS0_BASE);
        uart_init();
 
-#if CONFIG_USBDEBUG
-       sb7xx_51xx_enable_usbdebug(CONFIG_USBDEBUG_DEFAULT_PORT);
-       early_usbdebug_init();
-#endif
-
        console_init();
-       printk(BIOS_DEBUG, "\n");
 
 //     dump_mem(CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE-0x200, CONFIG_DCACHE_RAM_BASE+CONFIG_DCACHE_RAM_SIZE);