* Set USBDEBUG_DEFAULT_PORT in all southbridges and use that value

[coreboot.git] / src / mainboard / amd / pistachio / romstage.c

diff --git a/src/mainboard/amd/pistachio/romstage.c b/src/mainboard/amd/pistachio/romstage.c
index 08cf32775ef6a9104a571043ee1b16194c464f6e..6627d747e2502231a0cf038de0bf76b6c9cda39c 100644 (file)
--- a/src/mainboard/amd/pistachio/romstage.c
+++ b/src/mainboard/amd/pistachio/romstage.c
@@ -91,11 +91,6 @@ void cache_as_ram_main(unsigned long bist, unsigned long cpu_init_detectedx)
         * and it doesn't require any special setup. */
        uart_init();
 
-#if CONFIG_USBDEBUG
-       sb600_enable_usbdebug(0);
-       early_usbdebug_init();
-#endif
-
        console_init();
 
        post_code(0x03);