Remove whitespace.

[coreboot.git] / src / lib / uart8250.c

diff --git a/src/lib/uart8250.c b/src/lib/uart8250.c
index 8c8eed8a119460675c7487d9492aa2b7228e7262..261b90f2b219549ce81d729519433af1a2f376f8 100644 (file)
--- a/src/lib/uart8250.c
+++ b/src/lib/uart8250.c
@@ -21,35 +21,48 @@
 #include <arch/io.h>
 #include <uart8250.h>
 #include <pc80/mc146818rtc.h>
+#include <trace.h>
+
 #if CONFIG_USE_OPTION_TABLE
 #include "option_table.h"
 #endif
 
-
 /* Should support 8250, 16450, 16550, 16550A type UARTs */
 
+/* Expected character delay at 1200bps is 9ms for a working UART
+ * and no flow-control. Assume UART as stuck if shift register
+ * or FIFO takes more than 50ms per character to appear empty.
+ *
+ * Estimated that inb() from UART takes 1 microsecond.
+ */
+#define SINGLE_CHAR_TIMEOUT    (50 * 1000)
+#define FIFO_TIMEOUT           (16 * SINGLE_CHAR_TIMEOUT)
+
 static inline int uart8250_can_tx_byte(unsigned base_port)
 {
-       return inb(base_port + UART_LSR) & UART_MSR_DSR;
+       return inb(base_port + UART_LSR) & UART_LSR_THRE;
 }
 
 static inline void uart8250_wait_to_tx_byte(unsigned base_port)
 {
-       while(!uart8250_can_tx_byte(base_port))
-               ;
+       unsigned long int i = SINGLE_CHAR_TIMEOUT;
+       while (i-- && !uart8250_can_tx_byte(base_port));
 }
 
 static inline void uart8250_wait_until_sent(unsigned base_port)
 {
-       while(!(inb(base_port + UART_LSR) & UART_LSR_TEMT))
-               ;
+       unsigned long int i = FIFO_TIMEOUT;
+       while (i-- && !(inb(base_port + UART_LSR) & UART_LSR_TEMT));
 }
 
 void uart8250_tx_byte(unsigned base_port, unsigned char data)
 {
        uart8250_wait_to_tx_byte(base_port);
        outb(data, base_port + UART_TBR);
-       /* Make certain the data clears the fifos */
+}
+
+void uart8250_tx_flush(unsigned base_port)
+{
        uart8250_wait_until_sent(base_port);
 }
 
@@ -60,13 +73,18 @@ int uart8250_can_rx_byte(unsigned base_port)
 
 unsigned char uart8250_rx_byte(unsigned base_port)
 {
-       while(!uart8250_can_rx_byte(base_port))
-               ;
-       return inb(base_port + UART_RBR);
+       unsigned long int i = SINGLE_CHAR_TIMEOUT;
+       while (i-- && !uart8250_can_rx_byte(base_port));
+
+       if (i)
+               return inb(base_port + UART_RBR);
+       else
+               return 0x0;
 }
 
 void uart8250_init(unsigned base_port, unsigned divisor)
 {
+       DISABLE_TRACE;
        /* Disable interrupts */
        outb(0x0, base_port + UART_IER);
        /* Enable FIFOs */
@@ -78,27 +96,38 @@ void uart8250_init(unsigned base_port, unsigned divisor)
        /* DLAB on */
        outb(UART_LCR_DLAB | CONFIG_TTYS0_LCS, base_port + UART_LCR);
 
-       /* Set Baud Rate Divisor. 12 ==> 115200 Baud */
+       /* Set Baud Rate Divisor. 12 ==> 9600 Baud */
        outb(divisor & 0xFF,   base_port + UART_DLL);
        outb((divisor >> 8) & 0xFF,    base_port + UART_DLM);
 
        /* Set to 3 for 8N1 */
        outb(CONFIG_TTYS0_LCS, base_port + UART_LCR);
+       ENABLE_TRACE;
 }
 
-#if defined(__PRE_RAM__) || defined(__SMM__)
 void uart_init(void)
 {
-#if CONFIG_USE_OPTION_TABLE && !defined(__SMM__)
-        static const unsigned char divisor[] = { 1, 2, 3, 6, 12, 24, 48, 96 };
-        unsigned ttys0_div, ttys0_index;
-        ttys0_index = read_option(CMOS_VSTART_baud_rate, CMOS_VLEN_baud_rate, 0);
-        ttys0_index &= 7;
-        ttys0_div = divisor[ttys0_index];
-
-       uart8250_init(CONFIG_TTYS0_BASE, ttys0_div);
+       /* TODO the divisor calculation is hard coded to standard UARTs. Some
+        * UARTs won't work with these values. This should be a property of the
+        * UART used, worst case a Kconfig variable. For now live with hard
+        * codes as the only devices that might be different are the iWave
+        * iRainbowG6 and the OXPCIe952 card (and the latter is memory mapped)
+        */
+       unsigned int div = (115200 / CONFIG_TTYS0_BAUD);
+
+#if !defined(__SMM__) && CONFIG_USE_OPTION_TABLE
+       static const unsigned char divisor[8] = { 1, 2, 3, 6, 12, 24, 48, 96 };
+       unsigned b_index = 0;
+#if defined(__PRE_RAM__)
+       b_index = read_option(baud_rate, 0);
+       b_index &= 7;
+       div = divisor[b_index];
 #else
-       uart8250_init(CONFIG_TTYS0_BASE, CONFIG_TTYS0_DIV);
+       if (get_option(&b_index, "baud_rate") == 0) {
+               div = divisor[b_index];
+       }
 #endif
-}
 #endif
+
+       uart8250_init(CONFIG_TTYS0_BASE, div);
+}