Add an option to keep the ROM cached after romstage

[coreboot.git] / src / include / cpu / x86 / lapic.h

diff --git a/src/include/cpu/x86/lapic.h b/src/include/cpu/x86/lapic.h
index de99deebfe6691bf1e563e3592b165ee95f08b42..2215ec7ee5e28b4d31f67d33b6bcbb82893669f1 100644 (file)
--- a/src/include/cpu/x86/lapic.h
+++ b/src/include/cpu/x86/lapic.h
@@ -27,8 +27,6 @@ static inline __attribute__((always_inline)) void lapic_wait_icr_idle(void)
        do { } while ( lapic_read( LAPIC_ICR ) & LAPIC_ICR_BUSY );
 }
 
-
-
 static inline void enable_lapic(void)
 {
 
@@ -53,7 +51,7 @@ static inline __attribute__((always_inline)) unsigned long lapicid(void)
        return lapic_read(LAPIC_ID) >> 24;
 }
 
-
+#ifndef __ROMCC__
 #if CONFIG_AP_IN_SIPI_WAIT != 1
 /* If we need to go back to sipi wait, we use the long non-inlined version of
  * this function in lapic_cpu_init.c
@@ -69,7 +67,7 @@ static inline __attribute__((always_inline)) void stop_this_cpu(void)
 void stop_this_cpu(void);
 #endif
 
-#if ! defined (__ROMCC__) && !defined(__PRE_RAM__)
+#if !defined(__PRE_RAM__)
 
 #define xchg(ptr,v) ((__typeof__(*(ptr)))__xchg((unsigned long)(v),(ptr),sizeof(*(ptr))))
 
@@ -106,10 +104,9 @@ static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int siz
        return x;
 }
 
-
 static inline void lapic_write_atomic(unsigned long reg, unsigned long v)
 {
-       xchg((volatile unsigned long *)(LAPIC_DEFAULT_BASE+reg), v);
+       (void)xchg((volatile unsigned long *)(LAPIC_DEFAULT_BASE+reg), v);
 }
 
 
@@ -150,14 +147,14 @@ static inline int lapic_remote_read(int apicid, int reg, unsigned long *pvalue)
 
 void setup_lapic(void);
 
-
 #if CONFIG_SMP == 1
 struct device;
 int start_cpu(struct device *cpu);
-
 #endif /* CONFIG_SMP */
 
+#endif /* !__PRE_RAM__ */
 
-#endif /* !__ROMCC__ && !__PRE_RAM__ */
+int boot_cpu(void);
+#endif
 
 #endif /* CPU_X86_LAPIC_H */