void acpi_jump_to_wakeup(void *wakeup_addr);
int acpi_get_sleep_type(void);
-
+#else
+#define acpi_slp_type 0
#endif
/* northbridge/amd/amdfam10/amdfam10_acpi.c */
#else // CONFIG_GENERATE_ACPI_TABLES
#define write_acpi_tables(start) (start)
+#define acpi_slp_type 0
#endif
#include <cpu/x86/msr.h>
#include <cpu/x86/mtrr.h>
#include <cpu/x86/cache.h>
+#include <cpu/x86/lapic.h>
#include <arch/cpu.h>
+#include <arch/acpi.h>
#if CONFIG_GFXUMA
extern uint64_t uma_memory_base, uma_memory_size;
MTRRfix4K_E0000_MSR, MTRRfix4K_E8000_MSR, MTRRfix4K_F0000_MSR, MTRRfix4K_F8000_MSR,
};
-
void enable_fixed_mtrr(void)
{
msr_t msr;
while(var_state.reg < MTRRS) {
set_var_mtrr(var_state.reg++, 0, 0, 0, var_state.address_bits);
}
+
+#if CONFIG_CACHE_ROM
+ /* Enable Caching and speculative Reads for the
+ * complete ROM now that we actually have RAM.
+ */
+ if (boot_cpu() && (acpi_slp_type != 3)) {
+ set_var_mtrr(7, (4096-4)*1024, 4*1024,
+ MTRR_TYPE_WRPROT, address_bits);
+ }
+#endif
+
printk(BIOS_SPEW, "call enable_var_mtrr()\n");
enable_var_mtrr();
printk(BIOS_SPEW, "Leave %s\n", __func__);
do { } while ( lapic_read( LAPIC_ICR ) & LAPIC_ICR_BUSY );
}
-
-
static inline void enable_lapic(void)
{
return lapic_read(LAPIC_ID) >> 24;
}
-
+#ifndef __ROMCC__
#if CONFIG_AP_IN_SIPI_WAIT != 1
/* If we need to go back to sipi wait, we use the long non-inlined version of
* this function in lapic_cpu_init.c
#endif /* !__PRE_RAM__ */
+int boot_cpu(void);
+#endif
+
#endif /* CPU_X86_LAPIC_H */