Add an option to keep the ROM cached after romstage

[coreboot.git] / src / include / cpu / x86 / lapic.h

diff --git a/src/include/cpu/x86/lapic.h b/src/include/cpu/x86/lapic.h
index 8b44a6cb662ff752d45677e66fdf3d99de7a63a0..2215ec7ee5e28b4d31f67d33b6bcbb82893669f1 100644 (file)
--- a/src/include/cpu/x86/lapic.h
+++ b/src/include/cpu/x86/lapic.h
@@ -27,8 +27,6 @@ static inline __attribute__((always_inline)) void lapic_wait_icr_idle(void)
        do { } while ( lapic_read( LAPIC_ICR ) & LAPIC_ICR_BUSY );
 }
 
-
-
 static inline void enable_lapic(void)
 {
 
@@ -53,7 +51,7 @@ static inline __attribute__((always_inline)) unsigned long lapicid(void)
        return lapic_read(LAPIC_ID) >> 24;
 }
 
-
+#ifndef __ROMCC__
 #if CONFIG_AP_IN_SIPI_WAIT != 1
 /* If we need to go back to sipi wait, we use the long non-inlined version of
  * this function in lapic_cpu_init.c
@@ -108,7 +106,7 @@ static inline unsigned long __xchg(unsigned long x, volatile void * ptr, int siz
 
 static inline void lapic_write_atomic(unsigned long reg, unsigned long v)
 {
-       xchg((volatile unsigned long *)(LAPIC_DEFAULT_BASE+reg), v);
+       (void)xchg((volatile unsigned long *)(LAPIC_DEFAULT_BASE+reg), v);
 }
 
 
@@ -156,4 +154,7 @@ int start_cpu(struct device *cpu);
 
 #endif /* !__PRE_RAM__ */
 
+int boot_cpu(void);
+#endif
+
 #endif /* CPU_X86_LAPIC_H */