Add an option to keep the ROM cached after romstage

[coreboot.git] / src / cpu / x86 / mtrr / mtrr.c

diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c
index 8e7beea76e77d310ee59e8924ed343e690d8a63e..9015ad4d97c9dd96a99333b784e6bbea71a58593 100644 (file)
--- a/src/cpu/x86/mtrr/mtrr.c
+++ b/src/cpu/x86/mtrr/mtrr.c
@@ -36,6 +36,9 @@
 #include <cpu/x86/msr.h>
 #include <cpu/x86/mtrr.h>
 #include <cpu/x86/cache.h>
+#include <cpu/x86/lapic.h>
+#include <arch/cpu.h>
+#include <arch/acpi.h>
 
 #if CONFIG_GFXUMA
 extern uint64_t uma_memory_base, uma_memory_size;
@@ -47,7 +50,6 @@ static unsigned int mtrr_msr[] = {
        MTRRfix4K_E0000_MSR, MTRRfix4K_E8000_MSR, MTRRfix4K_F0000_MSR, MTRRfix4K_F8000_MSR,
 };
 
-
 void enable_fixed_mtrr(void)
 {
        msr_t msr;
@@ -455,6 +457,17 @@ void x86_setup_var_mtrrs(unsigned int address_bits, unsigned int above4gb)
        while(var_state.reg < MTRRS) {
                set_var_mtrr(var_state.reg++, 0, 0, 0, var_state.address_bits);
        }
+
+#if CONFIG_CACHE_ROM
+       /* Enable Caching and speculative Reads for the
+        * complete ROM now that we actually have RAM.
+        */
+       if (boot_cpu() && (acpi_slp_type != 3)) {
+               set_var_mtrr(7, (4096-4)*1024, 4*1024,
+                       MTRR_TYPE_WRPROT, address_bits);
+       }
+#endif
+
        printk(BIOS_SPEW, "call enable_var_mtrr()\n");
        enable_var_mtrr();
        printk(BIOS_SPEW, "Leave %s\n", __func__);
@@ -462,10 +475,13 @@ void x86_setup_var_mtrrs(unsigned int address_bits, unsigned int above4gb)
 }
 
 
-void x86_setup_mtrrs(unsigned address_bits)
+void x86_setup_mtrrs(void)
 {
+       int address_size;
        x86_setup_fixed_mtrrs();
-       x86_setup_var_mtrrs(address_bits, 1);
+       address_size = cpu_phys_address_size();
+       printk(BIOS_DEBUG, "CPU physical address size: %d bits\n", address_size);
+       x86_setup_var_mtrrs(address_size, 1);
 }