remove trailing whitespace

[coreboot.git] / src / cpu / x86 / lapic / lapic_cpu_init.c

diff --git a/src/cpu/x86/lapic/lapic_cpu_init.c b/src/cpu/x86/lapic/lapic_cpu_init.c
index 87452653cad5ec95f0f0553a4d2811142356b643..fc22ea4adf9a9e7fd5b8996475f485b518a283b6 100644 (file)
--- a/src/cpu/x86/lapic/lapic_cpu_init.c
+++ b/src/cpu/x86/lapic/lapic_cpu_init.c
@@ -16,8 +16,6 @@
 #include <cpu/cpu.h>
 
 #if CONFIG_SMP == 1
-
-#if CONFIG_RAMBASE >= 0x100000
 /* This is a lot more paranoid now, since Linux can NOT handle
  * being told there is a CPU when none exists. So any errors
  * will return 0, meaning no CPU.
@@ -29,7 +27,6 @@ static unsigned long get_valid_start_eip(unsigned long orig_start_eip)
 {
        return (unsigned long)orig_start_eip & 0xffff; // 16 bit to avoid 0xa0000
 }
-#endif
 
 #if CONFIG_HAVE_ACPI_RESUME == 1
 char *lowmem_backup;
@@ -41,7 +38,6 @@ extern char _secondary_start[];
 
 static void copy_secondary_start_to_1m_below(void)
 {
-#if CONFIG_RAMBASE >= 0x100000
        extern char _secondary_start_end[];
        unsigned long code_size;
        unsigned long start_eip;
@@ -67,7 +63,6 @@ static void copy_secondary_start_to_1m_below(void)
        memcpy((unsigned char *)start_eip, (unsigned char *)_secondary_start, code_size);
 
        printk(BIOS_DEBUG, "start_eip=0x%08lx, offset=0x%08lx, code_size=0x%08lx\n", start_eip, ((unsigned long)_secondary_start - start_eip), code_size);
-#endif
 }
 
 static int lapic_start_cpu(unsigned long apicid)
@@ -113,7 +108,9 @@ static int lapic_start_cpu(unsigned long apicid)
                }
                return 0;
        }
+#if !defined (CONFIG_CPU_AMD_MODEL_10XXX) && !defined (CONFIG_CPU_AMD_MODEL_14XXX)
        mdelay(10);
+#endif
 
        printk(BIOS_SPEW, "Deasserting INIT.\n");
 
@@ -137,13 +134,13 @@ static int lapic_start_cpu(unsigned long apicid)
                return 0;
        }
 
-#if CONFIG_RAMBASE >= 0x100000
        start_eip = get_valid_start_eip((unsigned long)_secondary_start);
-#else
-       start_eip = (unsigned long)_secondary_start;
-#endif
 
+#if !defined (CONFIG_CPU_AMD_MODEL_10XXX) && !defined (CONFIG_CPU_AMD_MODEL_14XXX)
        num_starts = 2;
+#else
+       num_starts = 1;
+#endif
 
        /*
         * Run STARTUP IPI loop.
@@ -265,7 +262,7 @@ int start_cpu(device_t cpu)
 
        if (result) {
                result = 0;
-               /* Wait 1s or until the new the new cpu calls in */
+               /* Wait 1s or until the new cpu calls in */
                for(count = 0; count < 100000 ; count++) {
                        if (secondary_stack == 0) {
                                result = 1;
@@ -341,6 +338,26 @@ void stop_this_cpu(void)
 }
 #endif
 
+#ifdef __SSE3__
+static __inline__ __attribute__((always_inline)) unsigned long readcr4(void)
+{
+       unsigned long value;
+       __asm__ __volatile__ (
+                       "mov %%cr4, %[value]"
+                       : [value] "=a" (value));
+       return value;
+}
+
+static __inline__ __attribute__((always_inline)) void writecr4(unsigned long Data)
+{
+       __asm__ __volatile__ (
+                       "mov %%eax, %%cr4"
+                       :
+                       : "a" (Data)
+                       );
+}
+#endif
+
 /* C entry point of secondary cpus */
 void secondary_cpu_init(void)
 {
@@ -350,6 +367,17 @@ void secondary_cpu_init(void)
        spin_lock(&start_cpu_lock);
   #endif
 #endif
+
+#ifdef __SSE3__
+       /*
+        * Seems that CR4 was cleared when AP start via lapic_start_cpu()
+        * Turn on CR4.OSFXSR and CR4.OSXMMEXCPT when SSE options enabled
+        */
+       u32 cr4_val;
+       cr4_val = readcr4();
+       cr4_val |= (1 << 9 | 1 << 10);
+       writecr4(cr4_val);
+#endif
        cpu_initialize();
 #if CONFIG_SERIAL_CPU_INIT == 1
   #if CONFIG_MAX_CPUS>2