#include <cpu/cpu.h>
#if CONFIG_SMP == 1
-
-#if CONFIG_RAMBASE >= 0x100000
/* This is a lot more paranoid now, since Linux can NOT handle
- * being told there is a CPU when none exists. So any errors
- * will return 0, meaning no CPU.
+ * being told there is a CPU when none exists. So any errors
+ * will return 0, meaning no CPU.
*
* We actually handling that case by noting which cpus startup
* and not telling anyone about the ones that dont.
- */
+ */
static unsigned long get_valid_start_eip(unsigned long orig_start_eip)
{
- return (unsigned long)orig_start_eip & 0xffff; // 16 bit to avoid 0xa0000
+ return (unsigned long)orig_start_eip & 0xffff; // 16 bit to avoid 0xa0000
}
-#endif
#if CONFIG_HAVE_ACPI_RESUME == 1
char *lowmem_backup;
int lowmem_backup_size;
#endif
-static void copy_secondary_start_to_1m_below(void)
+extern char _secondary_start[];
+
+static void copy_secondary_start_to_1m_below(void)
{
-#if CONFIG_RAMBASE >= 0x100000
- extern char _secondary_start[];
- extern char _secondary_start_end[];
- unsigned long code_size;
- unsigned long start_eip;
-
- /* _secondary_start need to be masked 20 above bit, because 16 bit code in secondary.S
- Also We need to copy the _secondary_start to the below 1M region
- */
- start_eip = get_valid_start_eip((unsigned long)_secondary_start);
- code_size = (unsigned long)_secondary_start_end - (unsigned long)_secondary_start;
+ extern char _secondary_start_end[];
+ unsigned long code_size;
+ unsigned long start_eip;
+
+ /* _secondary_start need to be masked 20 above bit, because 16 bit code in secondary.S
+ Also We need to copy the _secondary_start to the below 1M region
+ */
+ start_eip = get_valid_start_eip((unsigned long)_secondary_start);
+ code_size = (unsigned long)_secondary_start_end - (unsigned long)_secondary_start;
#if CONFIG_HAVE_ACPI_RESUME == 1
/* need to save it for RAM resume */
lowmem_backup_size = code_size;
lowmem_backup = malloc(code_size);
- lowmem_backup_ptr = (unsigned char *)start_eip;
-
+ lowmem_backup_ptr = (char *)start_eip;
+
if (lowmem_backup == NULL)
die("Out of backup memory\n");
- memcpy(lowmem_backup, lowmem_backup_ptr, lowmem_backup_size);
+ memcpy(lowmem_backup, lowmem_backup_ptr, lowmem_backup_size);
#endif
- /* copy the _secondary_start to the ram below 1M*/
- memcpy((unsigned char *)start_eip, (unsigned char *)_secondary_start, code_size);
+ /* copy the _secondary_start to the ram below 1M*/
+ memcpy((unsigned char *)start_eip, (unsigned char *)_secondary_start, code_size);
- printk_debug("start_eip=0x%08lx, offset=0x%08lx, code_size=0x%08lx\n", start_eip, ((unsigned long)_secondary_start - start_eip), code_size);
-#endif
+ printk(BIOS_DEBUG, "start_eip=0x%08lx, offset=0x%08lx, code_size=0x%08lx\n", start_eip, ((unsigned long)_secondary_start - start_eip), code_size);
}
static int lapic_start_cpu(unsigned long apicid)
int timeout;
unsigned long send_status, accept_status, start_eip;
int j, num_starts, maxlvt;
- extern char _secondary_start[];
-
+
/*
* Starting actual IPI sequence...
*/
- printk_spew("Asserting INIT.\n");
+ printk(BIOS_SPEW, "Asserting INIT.\n");
/*
* Turn INIT on target chip
/*
* Send IPI
*/
-
+
lapic_write_around(LAPIC_ICR, LAPIC_INT_LEVELTRIG | LAPIC_INT_ASSERT
| LAPIC_DM_INIT);
- printk_spew("Waiting for send to finish...\n");
+ printk(BIOS_SPEW, "Waiting for send to finish...\n");
timeout = 0;
do {
- printk_spew("+");
+ printk(BIOS_SPEW, "+");
udelay(100);
send_status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY;
} while (send_status && (timeout++ < 1000));
if (timeout >= 1000) {
- printk_err("CPU %ld: First apic write timed out. Disabling\n",
+ printk(BIOS_ERR, "CPU %ld: First apic write timed out. Disabling\n",
apicid);
- // too bad.
- printk_err("ESR is 0x%lx\n", lapic_read(LAPIC_ESR));
+ // too bad.
+ printk(BIOS_ERR, "ESR is 0x%lx\n", lapic_read(LAPIC_ESR));
if (lapic_read(LAPIC_ESR)) {
- printk_err("Try to reset ESR\n");
+ printk(BIOS_ERR, "Try to reset ESR\n");
lapic_write_around(LAPIC_ESR, 0);
- printk_err("ESR is 0x%lx\n", lapic_read(LAPIC_ESR));
+ printk(BIOS_ERR, "ESR is 0x%lx\n", lapic_read(LAPIC_ESR));
}
return 0;
}
+#if !defined (CONFIG_CPU_AMD_MODEL_10XXX) && !defined (CONFIG_CPU_AMD_MODEL_14XXX)
mdelay(10);
+#endif
- printk_spew("Deasserting INIT.\n");
+ printk(BIOS_SPEW, "Deasserting INIT.\n");
/* Target chip */
lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(apicid));
/* Send IPI */
lapic_write_around(LAPIC_ICR, LAPIC_INT_LEVELTRIG | LAPIC_DM_INIT);
-
- printk_spew("Waiting for send to finish...\n");
+
+ printk(BIOS_SPEW, "Waiting for send to finish...\n");
timeout = 0;
do {
- printk_spew("+");
+ printk(BIOS_SPEW, "+");
udelay(100);
send_status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY;
} while (send_status && (timeout++ < 1000));
if (timeout >= 1000) {
- printk_err("CPU %ld: Second apic write timed out. Disabling\n",
+ printk(BIOS_ERR, "CPU %ld: Second apic write timed out. Disabling\n",
apicid);
- // too bad.
+ // too bad.
return 0;
}
-#if CONFIG_RAMBASE >= 0x100000
start_eip = get_valid_start_eip((unsigned long)_secondary_start);
-#else
- start_eip = (unsigned long)_secondary_start;
-#endif
+#if !defined (CONFIG_CPU_AMD_MODEL_10XXX) && !defined (CONFIG_CPU_AMD_MODEL_14XXX)
num_starts = 2;
+#else
+ num_starts = 1;
+#endif
/*
* Run STARTUP IPI loop.
*/
- printk_spew("#startup loops: %d.\n", num_starts);
+ printk(BIOS_SPEW, "#startup loops: %d.\n", num_starts);
maxlvt = 4;
for (j = 1; j <= num_starts; j++) {
- printk_spew("Sending STARTUP #%d to %lu.\n", j, apicid);
+ printk(BIOS_SPEW, "Sending STARTUP #%d to %lu.\n", j, apicid);
lapic_read_around(LAPIC_SPIV);
lapic_write(LAPIC_ESR, 0);
lapic_read(LAPIC_ESR);
- printk_spew("After apic_write.\n");
+ printk(BIOS_SPEW, "After apic_write.\n");
/*
* STARTUP IPI
*/
udelay(300);
- printk_spew("Startup point 1.\n");
+ printk(BIOS_SPEW, "Startup point 1.\n");
- printk_spew("Waiting for send to finish...\n");
+ printk(BIOS_SPEW, "Waiting for send to finish...\n");
timeout = 0;
do {
- printk_spew("+");
+ printk(BIOS_SPEW, "+");
udelay(100);
send_status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY;
} while (send_status && (timeout++ < 1000));
if (send_status || accept_status)
break;
}
- printk_spew("After Startup.\n");
+ printk(BIOS_SPEW, "After Startup.\n");
if (send_status)
- printk_warning("APIC never delivered???\n");
+ printk(BIOS_WARNING, "APIC never delivered???\n");
if (accept_status)
- printk_warning("APIC delivery error (%lx).\n", accept_status);
+ printk(BIOS_WARNING, "APIC delivery error (%lx).\n", accept_status);
if (send_status || accept_status)
return 0;
return 1;
/* Get an index for the new processor */
index = ++last_cpu_index;
-
+
/* Find end of the new processors stack */
-#if (CONFIG_LB_MEM_TOPK>1024) && (CONFIG_RAMBASE < 0x100000) && ((CONFIG_CONSOLE_VGA==1) || (CONFIG_PCI_ROM_RUN == 1))
- if(index<1) { // only keep bsp on low
- stack_end = ((unsigned long)_estack) - (CONFIG_STACK_SIZE*index) - sizeof(struct cpu_info);
- } else {
- // for all APs, let use stack after pgtbl, 20480 is the pgtbl size for every cpu
- stack_end = 0x100000+(20480 + CONFIG_STACK_SIZE)*CONFIG_MAX_CPUS - (CONFIG_STACK_SIZE*index);
-#if (0x100000+(20480 + CONFIG_STACK_SIZE)*CONFIG_MAX_CPUS) > (CONFIG_LB_MEM_TOPK<<10)
- #warning "We may need to increase CONFIG_LB_MEM_TOPK, it need to be more than (0x100000+(20480 + CONFIG_STACK_SIZE)*CONFIG_MAX_CPUS)\n"
-#endif
- if(stack_end > (CONFIG_LB_MEM_TOPK<<10)) {
- printk_debug("start_cpu: Please increase the CONFIG_LB_MEM_TOPK more than %luK\n", stack_end>>10);
- die("Can not go on\n");
- }
- stack_end -= sizeof(struct cpu_info);
- }
-#else
stack_end = ((unsigned long)_estack) - (CONFIG_STACK_SIZE*index) - sizeof(struct cpu_info);
-#endif
-
/* Record the index and which cpu structure we are using */
info = (struct cpu_info *)stack_end;
info->index = index;
if (result) {
result = 0;
- /* Wait 1s or until the new the new cpu calls in */
+ /* Wait 1s or until the new cpu calls in */
for(count = 0; count < 100000 ; count++) {
if (secondary_stack == 0) {
result = 1;
id = lapic_read(LAPIC_ID) >> 24;
- printk_debug("CPU %ld going down...\n", id);
+ printk(BIOS_DEBUG, "CPU %ld going down...\n", id);
/* send an LAPIC INIT to myself */
lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(id));
/* wait for the ipi send to finish */
#if 0
- // When these two printk_spew calls are not removed, the
+ // When these two printk(BIOS_SPEW, ...) calls are not removed, the
// machine will hang when log level is SPEW. Why?
- printk_spew("Waiting for send to finish...\n");
+ printk(BIOS_SPEW, "Waiting for send to finish...\n");
#endif
timeout = 0;
do {
#if 0
- printk_spew("+");
+ printk(BIOS_SPEW, "+");
#endif
udelay(100);
send_status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY;
} while (send_status && (timeout++ < 1000));
if (timeout >= 1000) {
- printk_err("timed out\n");
+ printk(BIOS_ERR, "timed out\n");
}
mdelay(10);
- printk_spew("Deasserting INIT.\n");
+ printk(BIOS_SPEW, "Deasserting INIT.\n");
/* Deassert the LAPIC INIT */
- lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(id));
+ lapic_write_around(LAPIC_ICR2, SET_LAPIC_DEST_FIELD(id));
lapic_write_around(LAPIC_ICR, LAPIC_INT_LEVELTRIG | LAPIC_DM_INIT);
- printk_spew("Waiting for send to finish...\n");
+ printk(BIOS_SPEW, "Waiting for send to finish...\n");
timeout = 0;
do {
- printk_spew("+");
+ printk(BIOS_SPEW, "+");
udelay(100);
send_status = lapic_read(LAPIC_ICR) & LAPIC_ICR_BUSY;
} while (send_status && (timeout++ < 1000));
if (timeout >= 1000) {
- printk_err("timed out\n");
+ printk(BIOS_ERR, "timed out\n");
}
while(1) {
}
#endif
+#ifdef __SSE3__
+static __inline__ __attribute__((always_inline)) unsigned long readcr4(void)
+{
+ unsigned long value;
+ __asm__ __volatile__ (
+ "mov %%cr4, %[value]"
+ : [value] "=a" (value));
+ return value;
+}
+
+static __inline__ __attribute__((always_inline)) void writecr4(unsigned long Data)
+{
+ __asm__ __volatile__ (
+ "mov %%eax, %%cr4"
+ :
+ : "a" (Data)
+ );
+}
+#endif
+
/* C entry point of secondary cpus */
void secondary_cpu_init(void)
{
spin_lock(&start_cpu_lock);
#endif
#endif
+
+#ifdef __SSE3__
+ /*
+ * Seems that CR4 was cleared when AP start via lapic_start_cpu()
+ * Turn on CR4.OSFXSR and CR4.OSXMMEXCPT when SSE options enabled
+ */
+ u32 cr4_val;
+ cr4_val = readcr4();
+ cr4_val |= (1 << 9 | 1 << 10);
+ writecr4(cr4_val);
+#endif
cpu_initialize();
#if CONFIG_SERIAL_CPU_INIT == 1
#if CONFIG_MAX_CPUS>2
}
#if CONFIG_SERIAL_CPU_INIT == 0
if(cpu==bsp_cpu) {
- continue;
+ continue;
}
#endif
if (!start_cpu(cpu)) {
/* Record the error in cpu? */
- printk_err("CPU 0x%02x would not start!\n",
+ printk(BIOS_ERR, "CPU 0x%02x would not start!\n",
cpu->path.apic.apic_id);
}
#if CONFIG_SERIAL_CPU_INIT == 1
active_count = atomic_read(&active_cpus);
while(active_count > 1) {
if (active_count != old_active_count) {
- printk_info("Waiting for %d CPUS to stop\n", active_count - 1);
+ printk(BIOS_INFO, "Waiting for %d CPUS to stop\n", active_count - 1);
old_active_count = active_count;
}
udelay(10);
continue;
}
if (!cpu->initialized) {
- printk_err("CPU 0x%02x did not initialize!\n",
+ printk(BIOS_ERR, "CPU 0x%02x did not initialize!\n",
cpu->path.apic.apic_id);
}
}
- printk_debug("All AP CPUs stopped\n");
+ printk(BIOS_DEBUG, "All AP CPUs stopped\n");
}
#else /* CONFIG_SMP */
#define initialize_other_cpus(root) do {} while(0)
#endif /* CONFIG_SMP */
-#if CONFIG_WAIT_BEFORE_CPUS_INIT==0
- #define cpus_ready_for_init() do {} while(0)
-#else
- void cpus_ready_for_init(void);
-#endif
-
-#if CONFIG_HAVE_SMI_HANDLER
-void smm_init(void);
-#endif
-
void initialize_cpus(struct bus *cpu_bus)
{
struct device_path cpu_path;
smm_init();
#endif
- cpus_ready_for_init();
+ cpus_ready_for_init();
#if CONFIG_SMP == 1
#if CONFIG_SERIAL_CPU_INIT == 0
/* start all aps at first, so we can init ECC all together */
- start_other_cpus(cpu_bus, info->cpu);
+ start_other_cpus(cpu_bus, info->cpu);
#endif
#endif
- /* Initialize the bootstrap processor */
- cpu_initialize();
+ /* Initialize the bootstrap processor */
+ cpu_initialize();
#if CONFIG_SMP == 1
- #if CONFIG_SERIAL_CPU_INIT == 1
- start_other_cpus(cpu_bus, info->cpu);
- #endif
+ #if CONFIG_SERIAL_CPU_INIT == 1
+ start_other_cpus(cpu_bus, info->cpu);
+ #endif
/* Now wait the rest of the cpus stop*/
wait_other_cpus_stop(cpu_bus);
projects / coreboot.git / blobdiff