Add an option to keep the ROM cached after romstage

[coreboot.git] / src / cpu / x86 / lapic / boot_cpu.c

diff --git a/src/cpu/x86/lapic/boot_cpu.c b/src/cpu/x86/lapic/boot_cpu.c
index bca73e137ef38b03988204259f3330f275e74a2f..0fb9d5d35c587cc28a02b9c0a58b48347dfd1dd6 100644 (file)
--- a/src/cpu/x86/lapic/boot_cpu.c
+++ b/src/cpu/x86/lapic/boot_cpu.c
@@ -1,6 +1,8 @@
+#include <cpu/x86/lapic.h>
 #include <cpu/x86/msr.h>
 
-static int boot_cpu(void)
+#if CONFIG_SMP
+int boot_cpu(void)
 {
        int bsp;
        msr_t msr;
@@ -8,3 +10,7 @@ static int boot_cpu(void)
        bsp = !!(msr.lo & (1 << 8));
        return bsp;
 }
+#else
+#define boot_cpu(x) 1
+#endif
+