Add an option to keep the ROM cached after romstage

[coreboot.git] / src / cpu / x86 / lapic / boot_cpu.c

diff --git a/src/cpu/x86/lapic/boot_cpu.c b/src/cpu/x86/lapic/boot_cpu.c
index 87418d0883ac076f064679e4436bd1bc8354bb29..0fb9d5d35c587cc28a02b9c0a58b48347dfd1dd6 100644 (file)
--- a/src/cpu/x86/lapic/boot_cpu.c
+++ b/src/cpu/x86/lapic/boot_cpu.c
@@ -1,7 +1,8 @@
+#include <cpu/x86/lapic.h>
 #include <cpu/x86/msr.h>
 
 #if CONFIG_SMP
-static int boot_cpu(void)
+int boot_cpu(void)
 {
        int bsp;
        msr_t msr;