Add an option to keep the ROM cached after romstage

[coreboot.git] / src / cpu / x86 / lapic / Makefile.inc

diff --git a/src/cpu/x86/lapic/Makefile.inc b/src/cpu/x86/lapic/Makefile.inc
index af20956a9a9f50846fa79ce5ef168e1356dd3e64..f3fcadc0a7a6845c0e6711d33734b28f4d7c9cc2 100644 (file)
--- a/src/cpu/x86/lapic/Makefile.inc
+++ b/src/cpu/x86/lapic/Makefile.inc
@@ -2,3 +2,4 @@ ramstage-y += lapic.c
 ramstage-y += lapic_cpu_init.c
 ramstage-y += secondary.S
 ramstage-$(CONFIG_UDELAY_LAPIC) += apic_timer.c
+ramstage-y += boot_cpu.c