Add an option to keep the ROM cached after romstage

[coreboot.git] / src / cpu / x86 / Kconfig

diff --git a/src/cpu/x86/Kconfig b/src/cpu/x86/Kconfig
index c4ee9fa271ddc9b92f2a80333a745643a10bdb05..68946227b96a30967a5ca935ab460b371feb2683 100644 (file)
--- a/src/cpu/x86/Kconfig
+++ b/src/cpu/x86/Kconfig
@@ -2,18 +2,44 @@ config SERIAL_CPU_INIT
        bool
        default y
 
+config WAIT_BEFORE_CPUS_INIT
+       bool
+       default n
+
+config UDELAY_IO
+       bool
+       default y if !UDELAY_LAPIC && !UDELAY_TSC
+       default n
+
+config UDELAY_LAPIC
+       bool
+       default n
+
 config UDELAY_TSC
        bool
        default n
 
-config TSC_X86RDTSC_CALIBRATE_WITH_TIMER2
+config UDELAY_TIMER2
        bool
        default n
 
-config XIP_ROM_BASE
-       hex
-       default 0xfffe0000
+config TSC_CALIBRATE_WITH_IO
+       bool
+       default n
 
 config XIP_ROM_SIZE
        hex
-       default 0x20000
+       default ROM_SIZE if ROMCC
+       default 0x10000
+
+config CPU_ADDR_BITS
+       int
+       default 36
+
+config LOGICAL_CPUS
+       bool
+       default y
+
+config CACHE_ROM
+       bool
+       default n