* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
-#define CacheSize CONFIG_DCACHE_RAM_SIZE
-#define CacheBase CONFIG_DCACHE_RAM_BASE
-
-
+#include <cpu/x86/stack.h>
#include <cpu/x86/mtrr.h>
+#include <console/post_codes.h>
- /* Save the BIST result */
+#define CacheSize CONFIG_DCACHE_RAM_SIZE
+#define CacheBase CONFIG_DCACHE_RAM_BASE
+
+ /* Save the BIST result. */
movl %eax, %ebp
CacheAsRam:
- /* disable cache */
+ /* Disable cache. */
movl %cr0, %eax
- orl $(0x1<<30),%eax
- movl %eax,%cr0
+ orl $(1 << 30), %eax
+ movl %eax, %cr0
invd
- /* Set the default memory type and enable fixed and variable MTRRs */
+ /* Set the default memory type and enable fixed and variable MTRRs. */
movl $MTRRdefType_MSR, %ecx
xorl %edx, %edx
- /* Enable Variable and Fixed MTRRs */
- movl $0x00000c00, %eax
+ movl $(MTRRdefTypeEn | MTRRdefTypeFixEn), %eax
wrmsr
- /* Clear all MTRRs */
+ /* Clear all MTRRs. */
xorl %edx, %edx
- movl $fixed_mtrr_msr, %esi
+ movl $all_mtrr_msrs, %esi
clear_fixed_var_mtrr:
lodsl (%esi), %eax
jmp clear_fixed_var_mtrr
-fixed_mtrr_msr:
- .long 0x250, 0x258, 0x259
- .long 0x268, 0x269, 0x26A
- .long 0x26B, 0x26C, 0x26D
- .long 0x26E, 0x26F
-
-var_mtrr_msr:
- .long 0x200, 0x201, 0x202, 0x203
- .long 0x204, 0x205, 0x206, 0x207
- .long 0x208, 0x209, 0x20A, 0x20B
- .long 0x20C, 0x20D, 0x20E, 0x20F
+all_mtrr_msrs:
+ /* fixed MTRR MSRs */
+ .long MTRRfix64K_00000_MSR
+ .long MTRRfix16K_80000_MSR
+ .long MTRRfix16K_A0000_MSR
+ .long MTRRfix4K_C0000_MSR
+ .long MTRRfix4K_C8000_MSR
+ .long MTRRfix4K_D0000_MSR
+ .long MTRRfix4K_D8000_MSR
+ .long MTRRfix4K_E0000_MSR
+ .long MTRRfix4K_E8000_MSR
+ .long MTRRfix4K_F0000_MSR
+ .long MTRRfix4K_F8000_MSR
+
+ /* var MTRR MSRs */
+ .long MTRRphysBase_MSR(0)
+ .long MTRRphysMask_MSR(0)
+ .long MTRRphysBase_MSR(1)
+ .long MTRRphysMask_MSR(1)
+ .long MTRRphysBase_MSR(2)
+ .long MTRRphysMask_MSR(2)
+ .long MTRRphysBase_MSR(3)
+ .long MTRRphysMask_MSR(3)
+ .long MTRRphysBase_MSR(4)
+ .long MTRRphysMask_MSR(4)
+ .long MTRRphysBase_MSR(5)
+ .long MTRRphysMask_MSR(5)
+ .long MTRRphysBase_MSR(6)
+ .long MTRRphysMask_MSR(6)
+ .long MTRRphysBase_MSR(7)
+ .long MTRRphysMask_MSR(7)
+
.long 0x000 /* NULL, end of table */
clear_fixed_var_mtrr_out:
- /* MTRRPhysBase */
- movl $0x200, %ecx
+ movl $MTRRphysBase_MSR(0), %ecx
xorl %edx, %edx
- movl $(CacheBase|MTRR_TYPE_WRBACK),%eax
+ movl $(CacheBase | MTRR_TYPE_WRBACK), %eax
wrmsr
- /* MTRRPhysMask */
- movl $0x201, %ecx
+ movl $MTRRphysMask_MSR(0), %ecx
/* This assumes we never access addresses above 2^36 in CAR. */
- movl $0x0000000f,%edx
- movl $(~(CacheSize-1)|0x800),%eax
+ movl $0x0000000f, %edx
+ movl $(~(CacheSize - 1) | MTRRphysMaskValid), %eax
wrmsr
- /* enable write base caching so we can do execute in place
- * on the flash rom.
+ /*
+ * Enable write base caching so we can do execute in place (XIP)
+ * on the flash ROM.
*/
- /* MTRRPhysBase */
- movl $0x202, %ecx
+ movl $MTRRphysBase_MSR(1), %ecx
xorl %edx, %edx
-#if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK
-#define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE
-#else
-#define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE
-#endif
- movl $REAL_XIP_ROM_BASE, %eax
- orl $MTRR_TYPE_WRBACK, %eax
+ /*
+ * IMPORTANT: The following calculation _must_ be done at runtime. See
+ * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
+ */
+ movl $copy_and_run, %eax
+ andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax
+ orl $MTRR_TYPE_WRBACK, %eax
wrmsr
- /* MTRRPhysMask */
- movl $0x203, %ecx
+ movl $MTRRphysMask_MSR(1), %ecx
movl $0x0000000f, %edx
- movl $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax
+ movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
wrmsr
+ /* Set the default memory type and enable fixed and variable MTRRs. */
+ /* TODO: Or also enable fixed MTRRs? Bug in the code? */
movl $MTRRdefType_MSR, %ecx
xorl %edx, %edx
- /* Enable Variable and Fixed MTRRs */
- movl $0x00000800, %eax
+ movl $(MTRRdefTypeEn), %eax
wrmsr
+ /* Enable cache. */
movl %cr0, %eax
- andl $0x9fffffff, %eax
+ andl $(~((1 << 30) | (1 << 29))), %eax
movl %eax, %cr0
- /* Read the range with lodsl*/
+ /* Read the range with lodsl. */
cld
movl $CacheBase, %esi
movl %esi, %edi
- movl $(CacheSize>>2), %ecx
+ movl $(CacheSize >> 2), %ecx
rep lodsl
movl $CacheBase, %esi
movl %esi, %edi
movl $(CacheSize >> 2), %ecx
- /* 0x5c5c5c5c is a memory test pattern.
- * TODO: Check if everything works with the zero pattern as well. */
- /*xorl %eax, %eax*/
- xorl $0x5c5c5c5c,%eax
+ /*
+ * 0x5c5c5c5c is a memory test pattern.
+ * TODO: Check if everything works with the zero pattern as well.
+ */
+ /* xorl %eax, %eax */
+ xorl $0x5c5c5c5c, %eax
rep stosl
- movl REAL_XIP_ROM_BASE, %esi
+#ifdef CARTEST
+ /*
+ * IMPORTANT: The following calculation _must_ be done at runtime. See
+ * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
+ */
+ movl $copy_and_run, %esi
+ andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %ei
movl %esi, %edi
- movl $(CONFIG_XIP_ROM_SIZE>>2), %ecx
+ movl $(CONFIG_XIP_ROM_SIZE >> 2), %ecx
rep lodsl
+#endif
- /* The key point of this CAR code is C7 cache does not turn into
+ /*
+ * The key point of this CAR code is C7 cache does not turn into
* "no fill" mode, which is not compatible with general CAR code.
*/
movl %eax, %esp
#ifdef CARTEST
-testok: movb $0x40,%al
- outb %al, $0x80
+testok:
+ post_code(0x40)
xorl %edx, %edx
xorl %eax, %eax
- movl $0x5c5c,%edx
- pushl %edx
- pushl %edx
- pushl %edx
- pushl %edx
- pushl %edx
+ movl $0x5c5c, %edx
+ pushl %edx
+ pushl %edx
+ pushl %edx
+ pushl %edx
+ pushl %edx
popl %esi
popl %esi
popl %eax
popl %eax
popl %eax
- cmpl %edx,%eax
- jne stackerr
+ cmpl %edx, %eax
+ jne stackerr
#endif
- /* Restore the BIST result */
+ /* Restore the BIST result. */
movl %ebp, %eax
- /* We need to set ebp ? No need */
+ /* We need to set EBP? No need. */
movl %esp, %ebp
- pushl %eax /* bist */
+ pushl %eax /* BIST */
call main
- /*
+ /*
* TODO: Backup stack in CACHE_AS_RAM into MMX and SSE and after we
* get STACK up, we restore that. It is only needed if we
* want to go back.
*/
-
- /* We don't need cache as ram for now on */
- /* disable cache */
- movl %cr0, %eax
- orl $(0x1<<30),%eax
- movl %eax, %cr0
-
- /* Set the default memory type and disable fixed and enable variable MTRRs */
- movl $0x2ff, %ecx
- //movl $MTRRdefType_MSR, %ecx
- xorl %edx, %edx
+ /* We don't need CAR from now on. */
- /* Enable Variable and Disable Fixed MTRRs */
- movl $0x00000800, %eax
- wrmsr
+ /* Disable cache. */
+ movl %cr0, %eax
+ orl $(1 << 30), %eax
+ movl %eax, %cr0
- /* enable caching for first 1M using variable mtrr */
- movl $0x200, %ecx
- xorl %edx, %edx
- movl $(0 | 6), %eax
- //movl $(0 | MTRR_TYPE_WRBACK), %eax
+ /* Set the default memory type and enable variable MTRRs. */
+ /* TODO: Or also enable fixed MTRRs? Bug in the code? */
+ movl $MTRRdefType_MSR, %ecx
+ xorl %edx, %edx
+ movl $(MTRRdefTypeEn), %eax
wrmsr
-
- /* enable cache for 0-7ffff, 80000-9ffff, e0000-fffff;
- * If 1M cacheable, then when S3 resume, there is stange color on
- * screen for 2 sec. suppose problem of a0000-dfffff and cache.
- * And in x86_setup_fixed_mtrrs()(mtrr.c), 0-256M is set cacheable.
- */
- movl $0x201, %ecx
- movl $0x0000000f, %edx /* AMD 40 bit 0xff*/
- movl $((~(( 0 + 0x80000) - 1)) | 0x800), %eax
- wrmsr
-
- movl $0x202, %ecx
- xorl %edx, %edx
- movl $(0x80000 | 6), %eax
- orl $(0 | 6), %eax
+ /* Enable caching for CONFIG_RAMBASE..CONFIG_RAMTOP. */
+ movl $MTRRphysBase_MSR(0), %ecx
+ xorl %edx, %edx
+ movl $(CONFIG_RAMBASE | MTRR_TYPE_WRBACK), %eax
wrmsr
- movl $0x203, %ecx
- movl $0x0000000f, %edx /* AMD 40 bit 0xff*/
- movl $((~(( 0 + 0x20000) - 1)) | 0x800), %eax
- wrmsr
-
- movl $0x204, %ecx
- xorl %edx, %edx
- movl $(0xc0000 | 6), %eax
- orl $(0 | 6), %eax
+ movl $MTRRphysMask_MSR(0), %ecx
+ movl $0x0000000f, %edx /* AMD 40 bit 0xff */
+ movl $(~(CONFIG_RAMTOP - CONFIG_RAMBASE - 1) | MTRRphysMaskValid), %eax
wrmsr
- movl $0x205, %ecx
- movl $0x0000000f, %edx /* AMD 40 bit 0xff*/
- movl $((~(( 0 + 0x40000) - 1)) | 0x800), %eax
- wrmsr
-
- /* cache XIP_ROM_BASE-SIZE to speedup coreboot code */
- movl $0x206, %ecx
- xorl %edx, %edx
- movl $REAL_XIP_ROM_BASE,%eax
- orl $(0 | 6), %eax
+ /* Cache XIP_ROM area to speedup coreboot code. */
+ movl $MTRRphysBase_MSR(1), %ecx
+ xorl %edx, %edx
+ /*
+ * IMPORTANT: The following calculation _must_ be done at runtime. See
+ * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
+ */
+ movl $copy_and_run, %eax
+ andl $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax
+ orl $MTRR_TYPE_WRBACK, %eax
wrmsr
- movl $0x207, %ecx
- xorl %edx, %edx
- movl $CONFIG_XIP_ROM_SIZE,%eax
- decl %eax
- notl %eax
- orl $(0 | 0x800), %eax
+ movl $MTRRphysMask_MSR(1), %ecx
+ xorl %edx, %edx
+ movl $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
wrmsr
- /* enable cache */
- movl %cr0, %eax
- andl $0x9fffffff,%eax
- movl %eax, %cr0
+ /* Enable cache. */
+ movl %cr0, %eax
+ andl $(~((1 << 30) | (1 << 29))), %eax
+ movl %eax, %cr0
invd
- /* clear boot_complete flag */
+ /* Clear boot_complete flag. */
xorl %ebp, %ebp
__main:
- post_code(0x11)
- cld /* clear direction flag */
-
- movl %ebp, %esi
+ post_code(POST_PREPARE_RAMSTAGE)
+ cld /* Clear direction flag. */
- /* For now: use CONFIG_RAMBASE + 1MB - 64K (counting downwards) as stack. This
- * makes sure that we stay completely within the 1M-64K of memory that we
- * preserve for suspend/resume.
- */
+ movl %ebp, %esi
-#ifndef HIGH_MEMORY_SAVE
-#warning Need a central place for HIGH_MEMORY_SAVE
-#define HIGH_MEMORY_SAVE ( (1024 - 64) * 1024 )
-#endif
- movl $(CONFIG_RAMBASE + HIGH_MEMORY_SAVE), %esp
+ movl $ROMSTAGE_STACK, %esp
movl %esp, %ebp
- pushl %esi
- call copy_and_run
+ pushl %esi
+ call copy_and_run
-.Lhlt:
- post_code(0xee)
+.Lhlt:
+ post_code(POST_DEAD_CODE)
hlt
jmp .Lhlt
projects / coreboot.git / blobdiff