This patch unifies the use of config options in v2 to all start with CONFIG_

[coreboot.git] / src / cpu / intel / model_6fx / cache_as_ram_disable.c

diff --git a/src/cpu/intel/model_6fx/cache_as_ram_disable.c b/src/cpu/intel/model_6fx/cache_as_ram_disable.c
index 981aac1399bb9778c116d0b797f360872daba54e..ce508676e5a68f02920f14ba822b03e86d19e943 100644 (file)
--- a/src/cpu/intel/model_6fx/cache_as_ram_disable.c
+++ b/src/cpu/intel/model_6fx/cache_as_ram_disable.c
@@ -27,7 +27,7 @@ void stage1_main(unsigned long bist)
 {
        unsigned int cpu_reset = 0;
 
-#if USE_FALLBACK_IMAGE == 1
+#if CONFIG_USE_FALLBACK_IMAGE == 1
         /* Is this a deliberate reset by the bios */
         if (bios_reset_detected() && last_boot_normal()) {
                 goto normal_image;
@@ -87,10 +87,10 @@ cpu_reset_x:
        }
 
        __asm__ volatile (
-                /* set new esp */ /* before _RAMBASE */
+                /* set new esp */ /* before CONFIG_RAMBASE */
                 "subl   %0, %%ebp\n\t"
                 "subl   %0, %%esp\n\t"
-                ::"a"( (DCACHE_RAM_BASE + DCACHE_RAM_SIZE)- _RAMBASE )
+                ::"a"( (CONFIG_DCACHE_RAM_BASE + CONFIG_DCACHE_RAM_SIZE)- CONFIG_RAMBASE )
        );
 
        {