Remove whitespace.

[coreboot.git] / src / cpu / amd / car / cache_as_ram.inc

diff --git a/src/cpu/amd/car/cache_as_ram.inc b/src/cpu/amd/car/cache_as_ram.inc
index f43febe0d4aea53ac0db8f42705b9164cff5e69d..4625da1ca09165fedf3cd29bd0e933ceadb7c225 100644 (file)
--- a/src/cpu/amd/car/cache_as_ram.inc
+++ b/src/cpu/amd/car/cache_as_ram.inc
@@ -77,7 +77,7 @@ cache_as_ram_setup:
        /* Check if cpu_init_detected. */
        movl    $MTRRdefType_MSR, %ecx
        rdmsr
-       andl    $(1 << 11), %eax
+       andl    $MTRRdefTypeEn, %eax
        movl    %eax, %ebx      /* We store the status. */
 
        jmp_if_k8(CAR_FAM10_out_post_errata)
@@ -135,14 +135,34 @@ CAR_FAM10_out:
        wrmsr
 
 #if CONFIG_MMCONF_SUPPORT
-       /* Set MMIO config space BAR. */
-       movl    $MSR_MCFG_BASE, %ecx
-       rdmsr
-       andl    $(~(0xfff00000 | (0xf << 2))), %eax
-       orl     $((CONFIG_MMCONF_BASE_ADDRESS & 0xfff00000), %eax
-       orl     $((8 << 2) | (1 << 0)), %eax
-       andl    $(~(0x0000ffff)), %edx
-       orl     $(CONFIG_MMCONF_BASE_ADDRESS >> 32), %edx
+   #if (CONFIG_MMCONF_BASE_ADDRESS > 0xFFFFFFFF)
+   #error "MMCONF_BASE_ADDRESS too big"
+   #elif (CONFIG_MMCONF_BASE_ADDRESS & 0xFFFFF)
+   #error "MMCONF_BASE_ADDRESS not 1MB aligned"
+   #endif
+       movl    $0, %edx
+       movl    $((CONFIG_MMCONF_BASE_ADDRESS) | (1 << 0)), %eax
+   #if (CONFIG_MMCONF_BUS_NUMBER == 1)
+   #elif (CONFIG_MMCONF_BUS_NUMBER == 2)
+       orl     $(1 << 2), %eax
+   #elif (CONFIG_MMCONF_BUS_NUMBER == 4)
+       orl     $(2 << 2), %eax
+   #elif (CONFIG_MMCONF_BUS_NUMBER == 8)
+       orl     $(3 << 2), %eax
+   #elif (CONFIG_MMCONF_BUS_NUMBER == 16)
+       orl     $(4 << 2), %eax
+   #elif (CONFIG_MMCONF_BUS_NUMBER == 32)
+       orl     $(5 << 2), %eax
+   #elif (CONFIG_MMCONF_BUS_NUMBER == 64)
+       orl     $(6 << 2), %eax
+   #elif (CONFIG_MMCONF_BUS_NUMBER == 128)
+       orl     $(7 << 2), %eax
+   #elif (CONFIG_MMCONF_BUS_NUMBER == 256)
+       orl     $(8 << 2), %eax
+   #else
+       #error "bad MMCONF_BUS_NUMBER value"
+   #endif
+       movl    $(0xc0010058), %ecx
        wrmsr
 #endif
 
@@ -158,7 +178,7 @@ enable_fixed_mtrr_dram_modify:
 
        /* Clear all MTRRs. */
        xorl    %edx, %edx
-       movl    $fixed_mtrr_msr, %esi
+       movl    $all_mtrr_msrs, %esi
 
 clear_fixed_var_mtrr:
        lodsl   (%esi), %eax
@@ -259,20 +279,19 @@ clear_fixed_var_mtrr_out:
        movl    $(((CONFIG_RAMTOP) + TOP_MEM_MASK) & ~TOP_MEM_MASK) , %eax
        wrmsr
 
-#if defined(CONFIG_XIP_ROM_SIZE) && defined(CONFIG_XIP_ROM_BASE)
-
-#if defined(CONFIG_TINY_BOOTBLOCK) && CONFIG_TINY_BOOTBLOCK
-#define REAL_XIP_ROM_BASE AUTO_XIP_ROM_BASE
-#else
-#define REAL_XIP_ROM_BASE CONFIG_XIP_ROM_BASE
-#endif
+#if CONFIG_XIP_ROM_SIZE
 
        /* Enable write base caching so we can do execute in place (XIP)
         * on the flash ROM.
         */
        movl    $MTRRphysBase_MSR(1), %ecx
        xorl    %edx, %edx
-       movl    $REAL_XIP_ROM_BASE, %eax
+       /*
+        * IMPORTANT: The following calculation _must_ be done at runtime. See
+        * http://www.coreboot.org/pipermail/coreboot/2010-October/060855.html
+        */
+       movl    $copy_and_run, %eax
+       andl    $(~(CONFIG_XIP_ROM_SIZE - 1)), %eax
        orl     $MTRR_TYPE_WRBACK, %eax
        wrmsr
 
@@ -281,9 +300,9 @@ clear_fixed_var_mtrr_out:
        jmp_if_k8(wbcache_post_fam10_setup)
        movl    $0xffff, %edx /* (1 << (CONFIG_CPU_ADDR_BITS - 32)) - 1 for FAM10 (CONFIG_CPU_ADDR_BITS = 48) */
 wbcache_post_fam10_setup:
-       movl    $(~(CONFIG_XIP_ROM_SIZE - 1) | 0x800), %eax
+       movl    $(~(CONFIG_XIP_ROM_SIZE - 1) | MTRRphysMaskValid), %eax
        wrmsr
-#endif /* CONFIG_XIP_ROM_SIZE && CONFIG_XIP_ROM_BASE */
+#endif /* CONFIG_XIP_ROM_SIZE */
 
        /* Set the default memory type and enable fixed and variable MTRRs. */
        movl    $MTRRdefType_MSR, %ecx
@@ -401,23 +420,48 @@ CAR_FAM10_ap_out:
 
        post_code(0xaf)         /* Should never see this POST code. */
 
-fixed_mtrr_msr:
-       .long   0x250, 0x258, 0x259
-       .long   0x268, 0x269, 0x26A
-       .long   0x26B, 0x26C, 0x26D
-       .long   0x26E, 0x26F
-
-var_mtrr_msr:
-       .long   0x200, 0x201, 0x202, 0x203
-       .long   0x204, 0x205, 0x206, 0x207
-       .long   0x208, 0x209, 0x20A, 0x20B
-       .long   0x20C, 0x20D, 0x20E, 0x20F
-
-var_iorr_msr:
-       .long   0xC0010016, 0xC0010017, 0xC0010018, 0xC0010019
+all_mtrr_msrs:
+       /* fixed MTRR MSRs */
+       .long   MTRRfix64K_00000_MSR
+       .long   MTRRfix16K_80000_MSR
+       .long   MTRRfix16K_A0000_MSR
+       .long   MTRRfix4K_C0000_MSR
+       .long   MTRRfix4K_C8000_MSR
+       .long   MTRRfix4K_D0000_MSR
+       .long   MTRRfix4K_D8000_MSR
+       .long   MTRRfix4K_E0000_MSR
+       .long   MTRRfix4K_E8000_MSR
+       .long   MTRRfix4K_F0000_MSR
+       .long   MTRRfix4K_F8000_MSR
+
+       /* var MTRR MSRs */
+       .long   MTRRphysBase_MSR(0)
+       .long   MTRRphysMask_MSR(0)
+       .long   MTRRphysBase_MSR(1)
+       .long   MTRRphysMask_MSR(1)
+       .long   MTRRphysBase_MSR(2)
+       .long   MTRRphysMask_MSR(2)
+       .long   MTRRphysBase_MSR(3)
+       .long   MTRRphysMask_MSR(3)
+       .long   MTRRphysBase_MSR(4)
+       .long   MTRRphysMask_MSR(4)
+       .long   MTRRphysBase_MSR(5)
+       .long   MTRRphysMask_MSR(5)
+       .long   MTRRphysBase_MSR(6)
+       .long   MTRRphysMask_MSR(6)
+       .long   MTRRphysBase_MSR(7)
+       .long   MTRRphysMask_MSR(7)
+
+       /* Variable IORR MTRR MSRs */
+       .long   IORRBase_MSR(0)
+       .long   IORRMask_MSR(0)
+       .long   IORRBase_MSR(1)
+       .long   IORRMask_MSR(1)
+
+       /* Top of memory MTRR MSRs */
+       .long   TOP_MEM_MSR
+       .long   TOP_MEM2_MSR
 
-mem_top:
-       .long   0xC001001A, 0xC001001D
        .long   0x000 /* NULL, end of table */
 
 cache_as_ram_setup_out: