1 /****************************************************************************
3 * Realmode X86 Emulator Library
5 * Copyright (C) 1996-1999 SciTech Software, Inc.
6 * Copyright (C) David Mosberger-Tang
7 * Copyright (C) 1999 Egbert Eich
9 * ========================================================================
11 * Permission to use, copy, modify, distribute, and sell this software and
12 * its documentation for any purpose is hereby granted without fee,
13 * provided that the above copyright notice appear in all copies and that
14 * both that copyright notice and this permission notice appear in
15 * supporting documentation, and that the name of the authors not be used
16 * in advertising or publicity pertaining to distribution of the software
17 * without specific, written prior permission. The authors makes no
18 * representations about the suitability of this software for any purpose.
19 * It is provided "as is" without express or implied warranty.
21 * THE AUTHORS DISCLAIMS ALL WARRANTIES WITH REGARD TO THIS SOFTWARE,
22 * INCLUDING ALL IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS, IN NO
23 * EVENT SHALL THE AUTHORS BE LIABLE FOR ANY SPECIAL, INDIRECT OR
24 * CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER RESULTING FROM LOSS OF
25 * USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, NEGLIGENCE OR
26 * OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE USE OR
27 * PERFORMANCE OF THIS SOFTWARE.
29 * ========================================================================
33 * Developer: Kendall Bennett
35 * Description: Header file for x86 register definitions.
37 ****************************************************************************/
38 /* $XFree86: xc/extras/x86emu/include/x86emu/regs.h,v 1.3 2001/10/28 03:32:25 tsi Exp $ */
40 #ifndef __X86EMU_REGS_H
41 #define __X86EMU_REGS_H
43 /*---------------------- Macros and type definitions ----------------------*/
48 * General EAX, EBX, ECX, EDX type registers. Note that for
49 * portability, and speed, the issue of byte swapping is not addressed
50 * in the registers. All registers are stored in the default format
51 * available on the host machine. The only critical issue is that the
52 * registers should line up EXACTLY in the same manner as they do in
58 * etc. The result is that alot of the calculations can then be
59 * done using the native instruction set fully.
73 u8 filler0, filler1, h_reg, l_reg;
76 #else /* !__BIG_ENDIAN__ */
90 #endif /* BIG_ENDIAN */
96 } i386_general_register;
98 struct i386_general_regs {
99 i386_general_register A, B, C, D;
102 typedef struct i386_general_regs Gen_reg_t;
104 struct i386_special_regs {
105 i386_general_register SP, BP, SI, DI, IP;
110 * Segment registers here represent the 16 bit quantities
114 struct i386_segment_regs {
115 u16 CS, DS, SS, ES, FS, GS;
118 /* 8 bit registers */
119 #define R_AH gen.A.I8_reg.h_reg
120 #define R_AL gen.A.I8_reg.l_reg
121 #define R_BH gen.B.I8_reg.h_reg
122 #define R_BL gen.B.I8_reg.l_reg
123 #define R_CH gen.C.I8_reg.h_reg
124 #define R_CL gen.C.I8_reg.l_reg
125 #define R_DH gen.D.I8_reg.h_reg
126 #define R_DL gen.D.I8_reg.l_reg
128 /* 16 bit registers */
129 #define R_AX gen.A.I16_reg.x_reg
130 #define R_BX gen.B.I16_reg.x_reg
131 #define R_CX gen.C.I16_reg.x_reg
132 #define R_DX gen.D.I16_reg.x_reg
134 /* 32 bit extended registers */
135 #define R_EAX gen.A.I32_reg.e_reg
136 #define R_EBX gen.B.I32_reg.e_reg
137 #define R_ECX gen.C.I32_reg.e_reg
138 #define R_EDX gen.D.I32_reg.e_reg
140 /* special registers */
141 #define R_SP spc.SP.I16_reg.x_reg
142 #define R_BP spc.BP.I16_reg.x_reg
143 #define R_SI spc.SI.I16_reg.x_reg
144 #define R_DI spc.DI.I16_reg.x_reg
145 #define R_IP spc.IP.I16_reg.x_reg
146 #define R_FLG spc.FLAGS
148 /* special registers */
149 #define R_SP spc.SP.I16_reg.x_reg
150 #define R_BP spc.BP.I16_reg.x_reg
151 #define R_SI spc.SI.I16_reg.x_reg
152 #define R_DI spc.DI.I16_reg.x_reg
153 #define R_IP spc.IP.I16_reg.x_reg
154 #define R_FLG spc.FLAGS
156 /* special registers */
157 #define R_ESP spc.SP.I32_reg.e_reg
158 #define R_EBP spc.BP.I32_reg.e_reg
159 #define R_ESI spc.SI.I32_reg.e_reg
160 #define R_EDI spc.DI.I32_reg.e_reg
161 #define R_EIP spc.IP.I32_reg.e_reg
162 #define R_EFLG spc.FLAGS
164 /* segment registers */
172 /* flag conditions */
173 #define FB_CF 0x0001 /* CARRY flag */
174 #define FB_PF 0x0004 /* PARITY flag */
175 #define FB_AF 0x0010 /* AUX flag */
176 #define FB_ZF 0x0040 /* ZERO flag */
177 #define FB_SF 0x0080 /* SIGN flag */
178 #define FB_TF 0x0100 /* TRAP flag */
179 #define FB_IF 0x0200 /* INTERRUPT ENABLE flag */
180 #define FB_DF 0x0400 /* DIR flag */
181 #define FB_OF 0x0800 /* OVERFLOW flag */
183 /* 80286 and above always have bit#1 set */
184 #define F_ALWAYS_ON (0x0002) /* flag bits always on */
187 * Define a mask for only those flag bits we will ever pass back
190 #define F_MSK (FB_CF|FB_PF|FB_AF|FB_ZF|FB_SF|FB_TF|FB_IF|FB_DF|FB_OF)
192 /* following bits masked in to a 16bit quantity */
194 #define F_CF 0x0001 /* CARRY flag */
195 #define F_PF 0x0004 /* PARITY flag */
196 #define F_AF 0x0010 /* AUX flag */
197 #define F_ZF 0x0040 /* ZERO flag */
198 #define F_SF 0x0080 /* SIGN flag */
199 #define F_TF 0x0100 /* TRAP flag */
200 #define F_IF 0x0200 /* INTERRUPT ENABLE flag */
201 #define F_DF 0x0400 /* DIR flag */
202 #define F_OF 0x0800 /* OVERFLOW flag */
204 #define TOGGLE_FLAG(flag) (M.x86.R_FLG ^= (flag))
205 #define SET_FLAG(flag) (M.x86.R_FLG |= (flag))
206 #define CLEAR_FLAG(flag) (M.x86.R_FLG &= ~(flag))
207 #define ACCESS_FLAG(flag) (M.x86.R_FLG & (flag))
208 #define CLEARALL_FLAG(m) (M.x86.R_FLG = 0)
210 #define CONDITIONAL_SET_FLAG(COND,FLAG) \
211 if (COND) SET_FLAG(FLAG); else CLEAR_FLAG(FLAG)
213 #define F_PF_CALC 0x010000 /* PARITY flag has been calced */
214 #define F_ZF_CALC 0x020000 /* ZERO flag has been calced */
215 #define F_SF_CALC 0x040000 /* SIGN flag has been calced */
217 #define F_ALL_CALC 0xff0000 /* All have been calced */
220 * Emulator machine state.
221 * Segment usage control.
223 #define SYSMODE_SEG_DS_SS 0x00000001
224 #define SYSMODE_SEGOVR_CS 0x00000002
225 #define SYSMODE_SEGOVR_DS 0x00000004
226 #define SYSMODE_SEGOVR_ES 0x00000008
227 #define SYSMODE_SEGOVR_FS 0x00000010
228 #define SYSMODE_SEGOVR_GS 0x00000020
229 #define SYSMODE_SEGOVR_SS 0x00000040
230 #define SYSMODE_PREFIX_REPE 0x00000080
231 #define SYSMODE_PREFIX_REPNE 0x00000100
232 #define SYSMODE_PREFIX_DATA 0x00000200
233 #define SYSMODE_PREFIX_ADDR 0x00000400
234 //phueper: for REP(E|NE) Instructions, we need to decide wether it should be using
235 //the 32bit ECX register as or the 16bit CX register as count register
236 #define SYSMODE_32BIT_REP 0x00000800
237 #define SYSMODE_INTR_PENDING 0x10000000
238 #define SYSMODE_EXTRN_INTR 0x20000000
239 #define SYSMODE_HALTED 0x40000000
241 #define SYSMODE_SEGMASK (SYSMODE_SEG_DS_SS | \
242 SYSMODE_SEGOVR_CS | \
243 SYSMODE_SEGOVR_DS | \
244 SYSMODE_SEGOVR_ES | \
245 SYSMODE_SEGOVR_FS | \
246 SYSMODE_SEGOVR_GS | \
248 #define SYSMODE_CLRMASK (SYSMODE_SEG_DS_SS | \
249 SYSMODE_SEGOVR_CS | \
250 SYSMODE_SEGOVR_DS | \
251 SYSMODE_SEGOVR_ES | \
252 SYSMODE_SEGOVR_FS | \
253 SYSMODE_SEGOVR_GS | \
254 SYSMODE_SEGOVR_SS | \
255 SYSMODE_PREFIX_DATA | \
256 SYSMODE_PREFIX_ADDR | \
259 #define INTR_SYNCH 0x1
260 #define INTR_ASYNCH 0x2
261 #define INTR_HALTED 0x4
264 struct i386_general_regs gen;
265 struct i386_special_regs spc;
266 struct i386_segment_regs seg;
268 * MODE contains information on:
269 * REPE prefix 2 bits repe,repne
270 * SEGMENT overrides 5 bits normal,DS,SS,CS,ES
271 * Delayed flag set 3 bits (zero, signed, parity)
273 * interrupt # 8 bits instruction raised interrupt
274 * BIOS video segregs 4 bits
275 * Interrupt Pending 1 bits
276 * Extern interrupt 1 bits
280 volatile int intr; /* mask of pending interrupts */
282 #if CONFIG_X86EMU_DEBUG
288 char decode_buf[32]; /* encoded byte stream */
289 char decoded_buf[256]; /* disassembled strings */
295 /****************************************************************************
297 Structure maintaining the emulator machine state.
300 mem_base - Base real mode memory for the emulator
301 abseg - Base for the absegment
302 mem_size - Size of the real mode memory block for the emulator
303 private - private data pointer
305 ****************************************************************************/
307 unsigned long mem_base;
308 unsigned long mem_size;
316 /*----------------------------- Global Variables --------------------------*/
319 extern "C" { /* Use "C" linkage when in C++ mode */
322 /* Global emulator machine state.
324 * We keep it global to avoid pointer dereferences in the code for speed.
327 extern X86EMU_sysEnv _X86EMU_env;
328 #define M _X86EMU_env
330 #define X86_EAX M.x86.R_EAX
331 #define X86_EBX M.x86.R_EBX
332 #define X86_ECX M.x86.R_ECX
333 #define X86_EDX M.x86.R_EDX
334 #define X86_ESI M.x86.R_ESI
335 #define X86_EDI M.x86.R_EDI
336 #define X86_EBP M.x86.R_EBP
337 #define X86_EIP M.x86.R_EIP
338 #define X86_ESP M.x86.R_ESP
339 #define X86_EFLAGS M.x86.R_EFLG
341 #define X86_FLAGS M.x86.R_FLG
342 #define X86_AX M.x86.R_AX
343 #define X86_BX M.x86.R_BX
344 #define X86_CX M.x86.R_CX
345 #define X86_DX M.x86.R_DX
346 #define X86_SI M.x86.R_SI
347 #define X86_DI M.x86.R_DI
348 #define X86_BP M.x86.R_BP
349 #define X86_IP M.x86.R_IP
350 #define X86_SP M.x86.R_SP
351 #define X86_CS M.x86.R_CS
352 #define X86_DS M.x86.R_DS
353 #define X86_ES M.x86.R_ES
354 #define X86_SS M.x86.R_SS
355 #define X86_FS M.x86.R_FS
356 #define X86_GS M.x86.R_GS
358 #define X86_AL M.x86.R_AL
359 #define X86_BL M.x86.R_BL
360 #define X86_CL M.x86.R_CL
361 #define X86_DL M.x86.R_DL
363 #define X86_AH M.x86.R_AH
364 #define X86_BH M.x86.R_BH
365 #define X86_CH M.x86.R_CH
366 #define X86_DH M.x86.R_DH
369 } /* End of "C" linkage for C++ */
372 #endif /* __X86EMU_REGS_H */