1 #define HAVE_STRING_SUPPORT 0
2 #define HAVE_CAST_SUPPORT 0
3 #define HAVE_STATIC_ARRAY_SUPPORT 0
4 #define HAVE_POINTER_SUPPORT 0
5 #define HAVE_CONSTANT_PROPOGATION 0
7 void outb(unsigned char value, unsigned short port)
9 __builtin_outb(value, port);
12 void outw(unsigned short value, unsigned short port)
14 __builtin_outw(value, port);
17 void outl(unsigned int value, unsigned short port)
19 __builtin_outl(value, port);
22 unsigned char inb(unsigned short port)
24 return __builtin_inb(port);
27 unsigned char inw(unsigned short port)
29 return __builtin_inw(port);
32 unsigned char inl(unsigned short port)
34 return __builtin_inl(port);
37 static unsigned int config_cmd(unsigned char bus, unsigned devfn, unsigned where)
39 return 0x80000000 | (bus << 16) | (devfn << 8) | (where & ~3);
42 static unsigned char pcibios_read_config_byte(
43 unsigned char bus, unsigned devfn, unsigned where)
45 outl(config_cmd(bus, devfn, where), 0xCF8);
46 return inb(0xCFC + (where & 3));
49 static unsigned short pcibios_read_config_word(
50 unsigned char bus, unsigned devfn, unsigned where)
52 outl(config_cmd(bus, devfn, where), 0xCF8);
53 return inw(0xCFC + (where & 2));
56 static unsigned int pcibios_read_config_dword(
57 unsigned char bus, unsigned devfn, unsigned where)
59 outl(config_cmd(bus, devfn, where), 0xCF8);
64 static void pcibios_write_config_byte(
65 unsigned char bus, unsigned devfn, unsigned where, unsigned char value)
67 outl(config_cmd(bus, devfn, where), 0xCF8);
68 outb(value, 0xCFC + (where & 3));
71 static void pcibios_write_config_word(
72 unsigned char bus, unsigned devfn, unsigned where, unsigned short value)
74 outl(config_cmd(bus, devfn, where), 0xCF8);
75 outw(value, 0xCFC + (where & 2));
78 static void pcibios_write_config_dword(
79 unsigned char bus, unsigned devfn, unsigned where, unsigned int value)
81 outl(config_cmd(bus, devfn, where), 0xCF8);
87 /* __builtin_bsr is a exactly equivalent to the x86 machine
88 * instruction with the exception that it returns -1
89 * when the value presented to it is zero.
90 * Otherwise __builtin_bsr returns the zero based index of
91 * the highest bit set.
93 return __builtin_bsr(value);
96 #define PIIX4_DEVFN 0x90
97 #define SMBUS_MEM_DEVICE_START 0x50
98 #define SMBUS_MEM_DEVICE_END 0x53
99 #define SMBUS_MEM_DEVICE_INC 1
103 #define PM_DEVFN (PIIX4_DEVFN+3)
105 #if HAVE_CONSTANT_PROPOGATION
106 #define SMBUS_IO_BASE 0x1000
115 static void smbus_wait_until_ready(void)
117 while((inb(SMBUS_IO_BASE + SMBHSTSTAT) & 1) == 1) {
122 static void smbus_wait_until_done(void)
126 byte = inb(SMBUS_IO_BASE + SMBHSTSTAT);
127 }while((byte &1) == 1);
128 while( (byte & ~1) == 0) {
129 byte = inb(SMBUS_IO_BASE + SMBHSTSTAT);
133 int smbus_read_byte(unsigned device, unsigned address)
135 unsigned char host_status_register;
139 smbus_wait_until_ready();
141 /* setup transaction */
142 /* disable interrupts */
143 outb(inb(SMBUS_IO_BASE + SMBHSTCTL) & (~1), SMBUS_IO_BASE + SMBHSTCTL);
144 /* set the device I'm talking too */
145 outb(((device & 0x7f) << 1) | 1, SMBUS_IO_BASE + SMBHSTADD);
146 /* set the command/address... */
147 outb(address & 0xFF, SMBUS_IO_BASE + SMBHSTCMD);
148 /* set up for a byte data read */
149 outb((inb(SMBUS_IO_BASE + SMBHSTCTL) & 0xE3) | (0x2 << 2), SMBUS_IO_BASE + SMBHSTCTL);
151 /* clear any lingering errors, so the transaction will run */
152 outb(inb(SMBUS_IO_BASE + SMBHSTSTAT), SMBUS_IO_BASE + SMBHSTSTAT);
154 /* clear the data byte...*/
155 outb(0, SMBUS_IO_BASE + SMBHSTDAT0);
157 /* start the command */
158 outb((inb(SMBUS_IO_BASE + SMBHSTCTL) | 0x40), SMBUS_IO_BASE + SMBHSTCTL);
160 /* poll for transaction completion */
161 smbus_wait_until_done();
163 host_status_register = inb(SMBUS_IO_BASE + SMBHSTSTAT);
165 /* read results of transaction */
166 byte = inb(SMBUS_IO_BASE + SMBHSTDAT0);
169 if (host_status_register != 0x02) {
175 #else /* !HAVE_CONSTANT_PROPOGATION */
177 #define SMBUS_IO_HSTSTAT 0x1000
178 #define SMBUS_IO_HSTCTL 0x1002
179 #define SMBUS_IO_HSTCMD 0x1003
180 #define SMBUS_IO_HSTADD 0x1004
181 #define SMBUS_IO_HSTDAT0 0x1005
182 #define SMBUS_IO_HSTDAT1 0x1006
183 #define SMBUS_IO_HSTBLKDAT 0x1007
186 static void smbus_wait_until_ready(void)
188 while((inb(SMBUS_IO_HSTSTAT) & 1) == 1) {
193 static void smbus_wait_until_done(void)
197 byte = inb(SMBUS_IO_HSTSTAT);
198 }while((byte &1) == 1);
199 while( (byte & ~1) == 0) {
200 byte = inb(SMBUS_IO_HSTSTAT);
204 int smbus_read_byte(unsigned device, unsigned address)
206 unsigned char host_status_register;
209 smbus_wait_until_ready();
211 /* setup transaction */
212 /* disable interrupts */
213 outb(inb(SMBUS_IO_HSTCTL) & (~1), SMBUS_IO_HSTCTL);
214 /* set the device I'm talking too */
215 outb(((device & 0x7f) << 1) | 1, SMBUS_IO_HSTADD);
216 /* set the command/address... */
217 outb(address & 0xFF, SMBUS_IO_HSTCMD);
218 /* set up for a byte data read */
219 outb((inb(SMBUS_IO_HSTCTL) & 0xE3) | 8, SMBUS_IO_HSTCTL);
221 /* clear any lingering errors, so the transaction will run */
222 outb(inb(SMBUS_IO_HSTSTAT), SMBUS_IO_HSTSTAT);
224 /* clear the data byte...*/
225 outb(0, SMBUS_IO_HSTDAT0);
227 /* start the command */
228 outb((inb(SMBUS_IO_HSTCTL) | 0x40), SMBUS_IO_HSTCTL);
230 /* poll for transaction completion */
231 smbus_wait_until_done();
233 host_status_register = inb(SMBUS_IO_HSTSTAT);
235 /* read results of transaction */
236 result = inb(SMBUS_IO_HSTDAT0);
238 if (host_status_register != 0x02) {
243 #endif /* HAVE_CONSTANT_PROPOGATION */
247 #define I440GX_DEVFN ((0x00 << 3) + 0)
249 void sdram_no_memory(void)
251 #if HAVE_STRING_SUPPORT
252 print_err("No memory!!\n");
257 static void spd_enable_refresh(void)
260 * Effects: Uses serial presence detect to set the
261 * refresh rate in the DRAMC register.
262 * see spd_set_dramc for the other values.
263 * FIXME: Check for illegal/unsupported ram configurations and abort
265 #if HAVE_STATIC_ARRAY_SUPPORT
266 static const unsigned char refresh_rates[] = {
267 0x01, /* Normal 15.625 us -> 15.6 us */
268 0x05, /* Reduced(.25X) 3.9 us -> 7.8 us */
269 0x05, /* Reduced(.5X) 7.8 us -> 7.8 us */
270 0x02, /* Extended(2x) 31.3 us -> 31.2 us */
271 0x03, /* Extended(4x) 62.5 us -> 62.4 us */
272 0x04, /* Extended(8x) 125 us -> 124.8 us */
275 /* Find the first dimm and assume the rest are the same */
279 unsigned refresh_rate;
282 device = SMBUS_MEM_DEVICE_START;
283 while ((byte < 0) && (device <= SMBUS_MEM_DEVICE_END)) {
284 byte = smbus_read_byte(device, 12);
285 device += SMBUS_MEM_DEVICE_INC;
288 /* We couldn't find anything we must have no memory */
292 /* Default refresh rate be conservative */
294 /* see if the ram refresh is a supported one */
296 #if HAVE_STATIC_ARRAY_SUPPORT
297 refresh_rate = refresh_rates[byte];
300 byte = pcibios_read_config_byte(I440GX_BUS, I440GX_DEVFN, 0x57);
302 byte |= refresh_rate;
303 pcibios_write_config_byte(I440GX_BUS, I440GX_DEVFN, 0x57, byte);
306 void sdram_enable_refresh(void)
308 spd_enable_refresh();