aef936a8ff3b9eb616b3f28da025af3f3b215a71
[coreboot.git] / util / romcc / tests / simple_test2.c
1 void outl(unsigned int value, unsigned short port)
2 {
3         __builtin_outl(value, port);
4 }
5
6 #define PIIX4_DEVFN 0x90
7 #define SMBUS_MEM_DEVICE_START 0x50
8 #define SMBUS_MEM_DEVICE_END 0x53
9 #define SMBUS_MEM_DEVICE_INC 1
10
11
12 static void spd_set_drb(void)
13 {
14         /*
15          * Effects:     Uses serial presence detect to set the
16          *              DRB registers which holds the ending memory address assigned
17          *              to each DIMM.
18          */
19         unsigned end_of_memory;
20         unsigned device;
21         
22         end_of_memory = 0; /* in multiples of 8MiB */
23         device = SMBUS_MEM_DEVICE_START;
24         while (device <= SMBUS_MEM_DEVICE_END) {
25                 unsigned side1_bits;
26
27                 side1_bits =  -1;
28
29                 /* Compute the end address for the DRB register */
30                 /* Only process dimms < 2GB (2^8 * 8MB) */
31                 if (side1_bits < 8) {
32                         end_of_memory += (1 << side1_bits);
33                 }
34                 outl(end_of_memory, 0x1234);
35         }
36 }