1 #include "linux_syscall.h"
2 #include "linux_console.h"
5 static void setup_coherent_ht_domain(void)
7 static const unsigned int register_values[] = {
9 ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x40) & 0xFF)), 0xfff0f0f0, 0x00010101,
10 ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x44) & 0xFF)), 0xfff0f0f0, 0x00010101,
11 ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x48) & 0xFF)), 0xfff0f0f0, 0x00010101,
12 ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x4c) & 0xFF)), 0xfff0f0f0, 0x00010101,
13 ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x50) & 0xFF)), 0xfff0f0f0, 0x00010101,
14 ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x54) & 0xFF)), 0xfff0f0f0, 0x00010101,
15 ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x58) & 0xFF)), 0xfff0f0f0, 0x00010101,
16 ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x5c) & 0xFF)), 0xfff0f0f0, 0x00010101,
17 ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x68) & 0xFF)), 0x00800000, 0x0f00840f,
18 ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x6C) & 0xFF)), 0xffffff8c, 0x00000000 | (1 << 6) |(1 << 5)| (1 << 4),
19 ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x84) & 0xFF)), 0x00009c05, 0x11110020,
20 ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x88) & 0xFF)), 0xfffff0ff, 0x00000200,
21 ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((0) & 0x07) << 8) | ((0x94) & 0xFF)), 0xff000000, 0x00ff0000,
22 ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x44) & 0xFF)), 0x0000f8f8, 0x003f0000,
23 ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x4C) & 0xFF)), 0x0000f8f8, 0x00000001,
24 ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x54) & 0xFF)), 0x0000f8f8, 0x00000002,
25 ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x5C) & 0xFF)), 0x0000f8f8, 0x00000003,
26 ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x64) & 0xFF)), 0x0000f8f8, 0x00000004,
27 ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x6C) & 0xFF)), 0x0000f8f8, 0x00000005,
28 ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x74) & 0xFF)), 0x0000f8f8, 0x00000006,
29 ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x7C) & 0xFF)), 0x0000f8f8, 0x00000007,
30 ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x40) & 0xFF)), 0x0000f8fc, 0x00000003,
31 ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x48) & 0xFF)), 0x0000f8fc, 0x00400000,
32 ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x50) & 0xFF)), 0x0000f8fc, 0x00400000,
33 ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x58) & 0xFF)), 0x0000f8fc, 0x00400000,
34 ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x60) & 0xFF)), 0x0000f8fc, 0x00400000,
35 ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x68) & 0xFF)), 0x0000f8fc, 0x00400000,
36 ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x70) & 0xFF)), 0x0000f8fc, 0x00400000,
37 ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x78) & 0xFF)), 0x0000f8fc, 0x00400000,
38 ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x84) & 0xFF)), 0x00000048, 0x00e1ff00,
39 ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x8C) & 0xFF)), 0x00000048, 0x00dfff00,
40 ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x94) & 0xFF)), 0x00000048, 0x00e3ff00,
41 ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x9C) & 0xFF)), 0x00000048, 0x00000000,
42 ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xA4) & 0xFF)), 0x00000048, 0x00000000,
43 ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xAC) & 0xFF)), 0x00000048, 0x00000000,
44 ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xB4) & 0xFF)), 0x00000048, 0x00000b00,
45 ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xBC) & 0xFF)), 0x00000048, 0x00fe0b00,
46 ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x80) & 0xFF)), 0x000000f0, 0x00e00003,
47 ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x88) & 0xFF)), 0x000000f0, 0x00d80003,
48 ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x90) & 0xFF)), 0x000000f0, 0x00e20003,
49 ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0x98) & 0xFF)), 0x000000f0, 0x00000000,
50 ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xA0) & 0xFF)), 0x000000f0, 0x00000000,
51 ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xA8) & 0xFF)), 0x000000f0, 0x00000000,
52 ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xB0) & 0xFF)), 0x000000f0, 0x00000a03,
53 ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xB8) & 0xFF)), 0x000000f0, 0x00400003,
54 ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xC4) & 0xFF)), 0xFE000FC8, 0x0000d000,
55 ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xCC) & 0xFF)), 0xFE000FC8, 0x000ff000,
56 ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xD4) & 0xFF)), 0xFE000FC8, 0x00000000,
57 ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xDC) & 0xFF)), 0xFE000FC8, 0x00000000,
58 ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xC0) & 0xFF)), 0xFE000FCC, 0x0000d003,
59 ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xC8) & 0xFF)), 0xFE000FCC, 0x00001013,
60 ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xD0) & 0xFF)), 0xFE000FCC, 0x00000000,
61 ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xD8) & 0xFF)), 0xFE000FCC, 0x00000000,
62 ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xE0) & 0xFF)), 0x0000FC88, 0xff000003,
63 ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xE4) & 0xFF)), 0x0000FC88, 0x00000000,
64 ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xE8) & 0xFF)), 0x0000FC88, 0x00000000,
65 ( (((0) & 0xFF) << 16) | (((0x18) & 0x1f) << 11) | (((1) & 0x07) << 8) | ((0xEC) & 0xFF)), 0x0000FC88, 0x00000000,
67 #define PCI_ADDR(BUS, DEV, FN, WHERE) ( \
68 (((BUS) & 0xFF) << 16) | \
69 (((DEV) & 0x1f) << 11) | \
70 (((FN) & 0x07) << 8) | \
73 /* Routing Table Node i
82 * [ 0: 3] Request Route
83 * [0] Route to this node
87 * [11: 8] Response Route
88 * [0] Route to this node
92 * [19:16] Broadcast route
93 * [0] Route to this node
98 PCI_ADDR(0, 0x18, 0, 0x40), 0xfff0f0f0, 0x00010101,
99 PCI_ADDR(0, 0x18, 0, 0x44), 0xfff0f0f0, 0x00010101,
100 PCI_ADDR(0, 0x18, 0, 0x48), 0xfff0f0f0, 0x00010101,
101 PCI_ADDR(0, 0x18, 0, 0x4c), 0xfff0f0f0, 0x00010101,
102 PCI_ADDR(0, 0x18, 0, 0x50), 0xfff0f0f0, 0x00010101,
103 PCI_ADDR(0, 0x18, 0, 0x54), 0xfff0f0f0, 0x00010101,
104 PCI_ADDR(0, 0x18, 0, 0x58), 0xfff0f0f0, 0x00010101,
105 PCI_ADDR(0, 0x18, 0, 0x5c), 0xfff0f0f0, 0x00010101,
107 /* Hypetransport Transaction Control Register
109 * [ 0: 0] Disable read byte probe
111 * 1 = Probes not issued
112 * [ 1: 1] Disable Read Doubleword probe
114 * 1 = Probes not issued
115 * [ 2: 2] Disable write byte probes
117 * 1 = Probes not issued
118 * [ 3: 3] Disable Write Doubleword Probes
120 * 1 = Probes not issued.
121 * [ 4: 4] Disable Memroy Controller Target Start
122 * 0 = TgtStart packets are generated
123 * 1 = TgtStart packets are not generated.
124 * [ 5: 5] CPU1 Enable
125 * 0 = Second CPU disabled or not present
126 * 1 = Second CPU enabled.
127 * [ 6: 6] CPU Request PassPW
128 * 0 = CPU requests do not pass posted writes
129 * 1 = CPU requests pass posted writes.
130 * [ 7: 7] CPU read Respons PassPW
131 * 0 = CPU Responses do not pass posted writes
132 * 1 = CPU responses pass posted writes.
133 * [ 8: 8] Disable Probe Memory Cancel
134 * 0 = Probes may generate MemCancels
135 * 1 = Probes may not generate MemCancels
136 * [ 9: 9] Disable Remote Probe Memory Cancel.
137 * 0 = Probes hitting dirty blocks generate memory cancel packets
138 * 1 = Only probed caches on the same node as the memory controller
139 * generate cancel packets.
140 * [10:10] Disable Fill Probe
141 * 0 = Probes issued for cache fills
142 * 1 = Probes not issued for cache fills.
143 * [11:11] Response PassPw
144 * 0 = Downstream response PassPW based on original request
145 * 1 = Downstream response PassPW set to 1
146 * [12:12] Change ISOC to Ordered
147 * 0 = Bit 1 of coherent HT RdSz/WrSz command used for iosynchronous prioritization
148 * 1 = Bit 1 of coherent HT RdSz/WrSz command used for ordering.
149 * [14:13] Buffer Release Priority select
154 * [15:15] Limit Coherent HT Configuration Space Range
155 * 0 = No coherent HT configuration space restrictions
156 * 1 = Limit coherent HT configuration space based on node count
157 * [16:16] Local Interrupt Conversion Enable.
158 * 0 = ExtInt/NMI interrups unaffected.
159 * 1 = ExtInt/NMI broadcat interrupts converted to LINT0/1
160 * [17:17] APIC Extended Broadcast Enable.
161 * 0 = APIC broadcast is 0F
162 * 1 = APIC broadcast is FF
163 * [18:18] APIC Extended ID Enable
164 * 0 = APIC ID is 4 bits.
165 * 1 = APIC ID is 8 bits.
166 * [19:19] APIC Extended Spurious Vector Enable
167 * 0 = Lower 4 bits of spurious vector are read-only 1111
168 * 1 = Lower 4 bits of spurious vecotr are writeable.
169 * [20:20] Sequence ID Source Node Enable
170 * 0 = Normal operation
171 * 1 = Keep SeqID on routed packets for debugging.
172 * [22:21] Downstream non-posted request limit
178 * [25:24] Medium-Priority Bypass Count
179 * - Maximum # of times a medium priority access can pass a low
180 * priority access before Medium-Priority mode is disabled for one access.
181 * [27:26] High-Priority Bypass Count
182 * - Maximum # of times a high prioirty access can pass a medium or low
183 * priority access before High-prioirty mode is disabled for one access.
184 * [28:28] Enable High Priority CPU Reads
185 * 0 = Cpu reads are medium prioirty
186 * 1 = Cpu reads are high prioirty
187 * [29:29] Disable Low Priority Writes
188 * 0 = Non-isochronous writes are low priority
189 * 1 = Non-isochronous writes are medium prioirty
190 * [30:30] Disable High Priority Isochronous writes
191 * 0 = Isochronous writes are high priority
192 * 1 = Isochronous writes are medium priority
193 * [31:31] Disable Medium Priority Isochronous writes
194 * 0 = Isochronous writes are medium are high
195 * 1 = With bit 30 set makes Isochrouns writes low priority.
197 PCI_ADDR(0, 0x18, 0, 0x68), 0x00800000, 0x0f00840f,
198 /* HT Initialization Control Register
200 * [ 0: 0] Routing Table Disable
201 * 0 = Packets are routed according to routing tables
202 * 1 = Packets are routed according to the default link field
203 * [ 1: 1] Request Disable (BSP should clear this)
204 * 0 = Request packets may be generated
205 * 1 = Request packets may not be generated.
206 * [ 3: 2] Default Link (Read-only)
210 * 11 = CPU on same node
212 * - Scratch bit cleared by a cold reset
213 * [ 5: 5] BIOS Reset Detect
214 * - Scratch bit cleared by a cold reset
215 * [ 6: 6] INIT Detect
216 * - Scratch bit cleared by a warm or cold reset not by an INIT
219 PCI_ADDR(0, 0x18, 0, 0x6C), 0xffffff8c, 0x00000000 | (1 << 6) |(1 << 5)| (1 << 4),
220 /* LDTi Capabilities Registers
225 /* LDTi Link Control Registrs
229 * [ 1: 1] CRC Flood Enable
230 * 0 = Do not generate sync packets on CRC error
231 * 1 = Generate sync packets on CRC error
232 * [ 2: 2] CRC Start Test (Read-Only)
233 * [ 3: 3] CRC Force Frame Error
234 * 0 = Do not generate bad CRC
235 * 1 = Generate bad CRC
236 * [ 4: 4] Link Failure
237 * 0 = No link failure detected
238 * 1 = Link failure detected
239 * [ 5: 5] Initialization Complete
240 * 0 = Initialization not complete
241 * 1 = Initialization complete
242 * [ 6: 6] Receiver off
245 * [ 7: 7] Transmitter Off
247 * 1 = Transmitter off
250 * [0] = 1 Error on byte lane 0
251 * [1] = 1 Error on byte lane 1
252 * [12:12] Isochrnous Enable (Read-Only)
253 * [13:13] HT Stop Tristate Enable
254 * 0 = Driven during an LDTSTOP_L
255 * 1 = Tristated during and LDTSTOP_L
256 * [14:14] Extended CTL Time
257 * 0 = CTL is asserted for 16 bit times during link initialization
258 * 1 = CTL is asserted for 50us during link initialization
259 * [18:16] Max Link Width In (Read-Only?)
262 * [19:19] Doubleword Flow Control in (Read-Only)
263 * 0 = This link does not support doubleword flow control
264 * 1 = This link supports doubleword flow control
265 * [22:20] Max Link Width Out (Read-Only?)
268 * [23:23] Doubleworld Flow Control out (Read-Only)
269 * 0 = This link does not support doubleword flow control
270 * 1 = This link supports doubleworkd flow control
271 * [26:24] Link Width In
279 * 111 = Link physically not connected
280 * [27:27] Doubleword Flow Control In Enable
281 * 0 = Doubleword flow control disabled
282 * 1 = Doubleword flow control enabled (Not currently supported)
283 * [30:28] Link Width Out
291 * 111 = Link physically not connected
292 * [31:31] Doubleworld Flow Control Out Enable
293 * 0 = Doubleworld flow control disabled
294 * 1 = Doubleword flow control enabled (Not currently supported)
296 PCI_ADDR(0, 0x18, 0, 0x84), 0x00009c05, 0x11110020,
297 /* LDTi Frequency/Revision Registers
301 * [ 4: 0] Minor Revision
302 * Contains the HT Minor revision
303 * [ 7: 5] Major Revision
304 * Contains the HT Major revision
305 * [11: 8] Link Frequency (Takes effect the next time the link is reconnected)
322 * [15:12] Error (Not currently Implemented)
323 * [31:16] Indicates the frequency capabilities of the link
324 * [16] = 1 encoding 0000 of freq supported
325 * [17] = 1 encoding 0001 of freq supported
326 * [18] = 1 encoding 0010 of freq supported
327 * [19] = 1 encoding 0011 of freq supported
328 * [20] = 1 encoding 0100 of freq supported
329 * [21] = 1 encoding 0101 of freq supported
330 * [22] = 1 encoding 0110 of freq supported
331 * [23] = 1 encoding 0111 of freq supported
332 * [24] = 1 encoding 1000 of freq supported
333 * [25] = 1 encoding 1001 of freq supported
334 * [26] = 1 encoding 1010 of freq supported
335 * [27] = 1 encoding 1011 of freq supported
336 * [28] = 1 encoding 1100 of freq supported
337 * [29] = 1 encoding 1101 of freq supported
338 * [30] = 1 encoding 1110 of freq supported
339 * [31] = 1 encoding 1111 of freq supported
341 PCI_ADDR(0, 0x18, 0, 0x88), 0xfffff0ff, 0x00000200,
342 /* LDTi Feature Capability
347 /* LDTi Buffer Count Registers
352 /* LDTi Bus Number Registers
356 * For NonCoherent HT specifies the bus number downstream (behind the host bridge)
357 * [ 0: 7] Primary Bus Number
358 * [15: 8] Secondary Bus Number
359 * [23:15] Subordiante Bus Number
362 PCI_ADDR(0, 0x18, 0, 0x94), 0xff000000, 0x00ff0000,
363 /* LDTi Type Registers
368 /* Careful set limit registers before base registers which contain the enables */
369 /* DRAM Limit i Registers
378 * [ 2: 0] Destination Node ID
388 * [10: 8] Interleave select
389 * specifies the values of A[14:12] to use with interleave enable.
391 * [31:16] DRAM Limit Address i Bits 39-24
392 * This field defines the upper address bits of a 40 bit address
393 * that define the end of the DRAM region.
396 PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x003f0000,
399 PCI_ADDR(0, 0x18, 1, 0x44), 0x0000f8f8, 0x001f0000,
401 PCI_ADDR(0, 0x18, 1, 0x4C), 0x0000f8f8, 0x00000001,
402 PCI_ADDR(0, 0x18, 1, 0x54), 0x0000f8f8, 0x00000002,
403 PCI_ADDR(0, 0x18, 1, 0x5C), 0x0000f8f8, 0x00000003,
404 PCI_ADDR(0, 0x18, 1, 0x64), 0x0000f8f8, 0x00000004,
405 PCI_ADDR(0, 0x18, 1, 0x6C), 0x0000f8f8, 0x00000005,
406 PCI_ADDR(0, 0x18, 1, 0x74), 0x0000f8f8, 0x00000006,
407 PCI_ADDR(0, 0x18, 1, 0x7C), 0x0000f8f8, 0x00000007,
408 /* DRAM Base i Registers
417 * [ 0: 0] Read Enable
420 * [ 1: 1] Write Enable
421 * 0 = Writes Disabled
424 * [10: 8] Interleave Enable
425 * 000 = No interleave
426 * 001 = Interleave on A[12] (2 nodes)
428 * 011 = Interleave on A[12] and A[14] (4 nodes)
432 * 111 = Interleve on A[12] and A[13] and A[14] (8 nodes)
434 * [13:16] DRAM Base Address i Bits 39-24
435 * This field defines the upper address bits of a 40-bit address
436 * that define the start of the DRAM region.
438 PCI_ADDR(0, 0x18, 1, 0x40), 0x0000f8fc, 0x00000003,
440 PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00400000,
441 PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00400000,
442 PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00400000,
443 PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00400000,
444 PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00400000,
445 PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00400000,
446 PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00400000,
449 PCI_ADDR(0, 0x18, 1, 0x48), 0x0000f8fc, 0x00200000,
450 PCI_ADDR(0, 0x18, 1, 0x50), 0x0000f8fc, 0x00200000,
451 PCI_ADDR(0, 0x18, 1, 0x58), 0x0000f8fc, 0x00200000,
452 PCI_ADDR(0, 0x18, 1, 0x60), 0x0000f8fc, 0x00200000,
453 PCI_ADDR(0, 0x18, 1, 0x68), 0x0000f8fc, 0x00200000,
454 PCI_ADDR(0, 0x18, 1, 0x70), 0x0000f8fc, 0x00200000,
455 PCI_ADDR(0, 0x18, 1, 0x78), 0x0000f8fc, 0x00200000,
458 /* Memory-Mapped I/O Limit i Registers
467 * [ 2: 0] Destination Node ID
477 * [ 5: 4] Destination Link ID
484 * 0 = CPU writes may be posted
485 * 1 = CPU writes must be non-posted
486 * [31: 8] Memory-Mapped I/O Limit Address i (39-16)
487 * This field defines the upp adddress bits of a 40-bit address that
488 * defines the end of a memory-mapped I/O region n
490 PCI_ADDR(0, 0x18, 1, 0x84), 0x00000048, 0x00e1ff00,
491 PCI_ADDR(0, 0x18, 1, 0x8C), 0x00000048, 0x00dfff00,
492 PCI_ADDR(0, 0x18, 1, 0x94), 0x00000048, 0x00e3ff00,
493 PCI_ADDR(0, 0x18, 1, 0x9C), 0x00000048, 0x00000000,
494 PCI_ADDR(0, 0x18, 1, 0xA4), 0x00000048, 0x00000000,
495 PCI_ADDR(0, 0x18, 1, 0xAC), 0x00000048, 0x00000000,
496 PCI_ADDR(0, 0x18, 1, 0xB4), 0x00000048, 0x00000b00,
497 PCI_ADDR(0, 0x18, 1, 0xBC), 0x00000048, 0x00fe0b00,
499 /* Memory-Mapped I/O Base i Registers
508 * [ 0: 0] Read Enable
511 * [ 1: 1] Write Enable
512 * 0 = Writes disabled
514 * [ 2: 2] Cpu Disable
515 * 0 = Cpu can use this I/O range
516 * 1 = Cpu requests do not use this I/O range
518 * 0 = base/limit registers i are read/write
519 * 1 = base/limit registers i are read-only
521 * [31: 8] Memory-Mapped I/O Base Address i (39-16)
522 * This field defines the upper address bits of a 40bit address
523 * that defines the start of memory-mapped I/O region i
525 PCI_ADDR(0, 0x18, 1, 0x80), 0x000000f0, 0x00e00003,
526 PCI_ADDR(0, 0x18, 1, 0x88), 0x000000f0, 0x00d80003,
527 PCI_ADDR(0, 0x18, 1, 0x90), 0x000000f0, 0x00e20003,
528 PCI_ADDR(0, 0x18, 1, 0x98), 0x000000f0, 0x00000000,
529 PCI_ADDR(0, 0x18, 1, 0xA0), 0x000000f0, 0x00000000,
530 PCI_ADDR(0, 0x18, 1, 0xA8), 0x000000f0, 0x00000000,
531 PCI_ADDR(0, 0x18, 1, 0xB0), 0x000000f0, 0x00000a03,
533 PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00400003,
536 PCI_ADDR(0, 0x18, 1, 0xB8), 0x000000f0, 0x00200003,
539 /* PCI I/O Limit i Registers
544 * [ 2: 0] Destination Node ID
554 * [ 5: 4] Destination Link ID
560 * [24:12] PCI I/O Limit Address i
561 * This field defines the end of PCI I/O region n
564 PCI_ADDR(0, 0x18, 1, 0xC4), 0xFE000FC8, 0x0000d000,
565 PCI_ADDR(0, 0x18, 1, 0xCC), 0xFE000FC8, 0x000ff000,
566 PCI_ADDR(0, 0x18, 1, 0xD4), 0xFE000FC8, 0x00000000,
567 PCI_ADDR(0, 0x18, 1, 0xDC), 0xFE000FC8, 0x00000000,
569 /* PCI I/O Base i Registers
574 * [ 0: 0] Read Enable
577 * [ 1: 1] Write Enable
578 * 0 = Writes Disabled
582 * 0 = VGA matches Disabled
583 * 1 = matches all address < 64K and where A[9:0] is in the
584 * range 3B0-3BB or 3C0-3DF independen of the base & limit registers
586 * 0 = ISA matches Disabled
587 * 1 = Blocks address < 64K and in the last 768 bytes of eack 1K block
588 * from matching agains this base/limit pair
590 * [24:12] PCI I/O Base i
591 * This field defines the start of PCI I/O region n
594 PCI_ADDR(0, 0x18, 1, 0xC0), 0xFE000FCC, 0x0000d003,
595 PCI_ADDR(0, 0x18, 1, 0xC8), 0xFE000FCC, 0x00001013,
596 PCI_ADDR(0, 0x18, 1, 0xD0), 0xFE000FCC, 0x00000000,
597 PCI_ADDR(0, 0x18, 1, 0xD8), 0xFE000FCC, 0x00000000,
599 /* Config Base and Limit i Registers
604 * [ 0: 0] Read Enable
607 * [ 1: 1] Write Enable
608 * 0 = Writes Disabled
610 * [ 2: 2] Device Number Compare Enable
611 * 0 = The ranges are based on bus number
612 * 1 = The ranges are ranges of devices on bus 0
614 * [ 6: 4] Destination Node
624 * [ 9: 8] Destination Link
630 * [23:16] Bus Number Base i
631 * This field defines the lowest bus number in configuration region i
632 * [31:24] Bus Number Limit i
633 * This field defines the highest bus number in configuration regin i
635 PCI_ADDR(0, 0x18, 1, 0xE0), 0x0000FC88, 0xff000003,
636 PCI_ADDR(0, 0x18, 1, 0xE4), 0x0000FC88, 0x00000000,
637 PCI_ADDR(0, 0x18, 1, 0xE8), 0x0000FC88, 0x00000000,
638 PCI_ADDR(0, 0x18, 1, 0xEC), 0x0000FC88, 0x00000000,
643 print_debug("setting up coherent ht domain....\r\n");
644 max = sizeof(register_values)/sizeof(register_values[0]);
645 for(i = 0; i < max; i += 3) {
648 print_debug_hex32(register_values[i]);
650 print_debug_hex32(register_values[i+2]);
654 reg = pci_read_config32(register_values[i]);
655 reg &= register_values[i+1];
656 reg |= register_values[i+2] & ~register_values[i+1];
657 pci_write_config32(register_values[i], reg);
660 print_debug("done.\r\n");
663 static void main(void)
665 static const char msg[] = "hello world\r\n";
667 write(STDOUT_FILENO, msg, sizeof(msg));
670 setup_coherent_ht_domain();