2 * This file is part of msrtool.
4 * Copyright (C) 2011 Anton Kochkov <anton.kochkov@gmail.com>
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License version 2 as
8 * published by the Free Software Foundation.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
22 int intel_core2_later_probe(const struct targetdef *target) {
23 struct cpuid_t *id = cpuid();
24 return ((0x6 == id->family)&(0x17 == id->model));
27 const struct msrdef intel_core2_later_msrs[] = {
28 {0x17, MSRTYPE_RDWR, MSR2(0,0), "IA32_PLATFORM_ID Register", "Model Specific Platform ID", {
32 { 12, 5, "Maximum Qualified Ratio:", "The maximum allowed bus ratio", PRESENT_DEC, {
38 { 0x2a, MSRTYPE_RDWR, MSR2(0,0), "MSR_EBL_CR_POWERON Register", "Processor Hard Power-On Configuration", {
40 { 26, 5, "Integer Bus Frequency Ratio:", "R/O", PRESENT_DEC, {
43 { 21, 2, "Symmetric Arbitration ID:", "R/O", PRESENT_BIN, {
47 { 18, 1, "N/2:", "Non-integer bus ratio", PRESENT_DEC, {
48 { MSR1(0), "Integer ratio" },
49 { MSR1(1), "Non-integer ratio" },
52 { 17, 2, "APIC Cluster ID:", "R/O", PRESENT_HEX, {
56 { 14, 1, "1 Mbyte Power on Reset Vector", "R/O", PRESENT_DEC, {
57 { MSR1(0), "4 GBytes Power on Reset Vector" },
58 { MSR1(1), "1 Mbyte Power on Reset Vector" },
62 { 12, 1, "BINIT# Observation", "R/O", PRESENT_DEC, {
63 { MSR1(0), "BINIT# Observation disabled" },
64 { MSR1(1), "BINIT# Observation enabled" },
67 { 11, 1, "TXT", "Intel TXT Capable Chipset", PRESENT_DEC, {
68 { MSR1(0), "Intel TXT Capable Chipset not present" },
69 { MSR1(1), "Intel TXT Capable Chipset present" },
72 { 10, 1, "MCERR# Observation:", "R/O", PRESENT_DEC, {
73 { MSR1(0), "MCERR# Observation disabled" },
74 { MSR1(1), "MCERR# Observation enabled" },
77 { 9, 1, "Execute BIST", "R/O", PRESENT_DEC, {
78 { MSR1(0), "Execute BIST disabled" },
79 { MSR1(1), "Execute BIST enabled" },
82 { 8, 1, "Output Tri-state", "R/O", PRESENT_DEC, {
83 { MSR1(0), "Output Tri-state disabled" },
84 { MSR1(1), "Output Tri-state enabled" },
87 { 7, 1, "BINIT# Driver Enable", "R/W", PRESENT_DEC, {
88 { MSR1(0), "BINIT# Driver disabled" },
89 { MSR1(1), "BINIT# Driver enabled" },
93 { 4, 1, "Address parity enable", "R/W", PRESENT_DEC, {
94 { MSR1(0), "Address parity disabled" },
95 { MSR1(1), "Address parity enabled" },
98 { 3, 1, "MCERR# Driver Enable", "R/W", PRESENT_DEC, {
99 { MSR1(0), "MCERR# Driver disabled" },
100 { MSR1(1), "MCERR# Driver enabled" },
103 { 2, 1, "Response error checking enable", "R/W", PRESENT_DEC, {
104 { MSR1(0), "Response Error Checking disabled" },
105 { MSR1(1), "Response Error Checking enabled" },
108 { 1, 1, "Data error checking enable", "R/W", PRESENT_DEC, {
109 { MSR1(0), "Data error checking disabled" },
110 { MSR1(1), "Data error checking enabled" },
116 {0xcd, MSRTYPE_RDWR, MSR2(0,0), "MSR_FSB_FREQ", "", {
119 {0x11, MSRTYPE_RDWR, MSR2(0,0), "MSR_BBL_CR_CTL3", "", {
122 {0x198, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_STATUS", "", {
125 {0x1a0, MSRTYPE_RDWR, MSR2(0,0), "IA32_MISC_ENABLE", "", {
131 {0x0, MSRTYPE_RDWR, MSR2(0,0), "IA32_P5_MC_ADDR", "", {
134 {0x1, MSRTYPE_RDWR, MSR2(0,0), "IA32_P5_MC_TYPE", "", {
137 {0x6, MSRTYPE_RDWR, MSR2(0,0), "IA32_MONITOR_FILTER_SIZE", "", {
140 {0x10, MSRTYPE_RDWR, MSR2(0,0), "IA32_TIME_STEP_COUNTER", "", {
143 {0x1b, MSRTYPE_RDWR, MSR2(0,0), "IA32_APIC_BASE", "", {
146 {0x3a, MSRTYPE_RDWR, MSR2(0,0), "IA32_FEATURE_CONTROL", "", {
149 {0x40, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_0_FROM_IP", "", {
152 {0x41, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_1_FROM_IP", "", {
155 {0x42, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_2_FROM_IP", "", {
158 {0x43, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_3_FROM_IP", "", {
161 {0x60, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_0_TO_LIP", "", {
164 {0x61, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_1_TO_LIP", "", {
167 {0x62, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_2_TO_LIP", "", {
170 {0x63, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_3_TO_LIP", "", {
173 {0x79, MSRTYPE_RDWR, MSR2(0,0), "IA32_BIOS_UPDT_TRIG", "", {
176 {0x8b, MSRTYPE_RDWR, MSR2(0,0), "IA32_BIOS_SIGN_ID", "", {
179 {0xa0, MSRTYPE_RDWR, MSR2(0,0), "MSR_SMRR_PHYS_BASE", "", {
182 {0xa1, MSRTYPE_RDWR, MSR2(0,0), "MSR_SMRR_PHYS_MASK", "", {
185 {0xc1, MSRTYPE_RDWR, MSR2(0,0), "IA32_PMC0", "", {
188 {0xc2, MSRTYPE_RDWR, MSR2(0,0), "IA32_PMC1", "", {
191 {0xe7, MSRTYPE_RDWR, MSR2(0,0), "IA32_MPERF", "", {
194 {0xe8, MSRTYPE_RDWR, MSR2(0,0), "IA32_APERF", "", {
197 {0xfe, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRRCAP", "", {
200 {0x174, MSRTYPE_RDWR, MSR2(0,0), "IA32_SYSENTER_CS", "", {
203 {0x175, MSRTYPE_RDWR, MSR2(0,0), "IA32_SYSENTER_ESP", "", {
206 {0x176, MSRTYPE_RDWR, MSR2(0,0), "IA32_SYSENTER_EIP", "", {
209 {0x179, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCG_CAP", "", {
212 {0x17a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCG_STATUS", "", {
215 {0x186, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERFEVTSEL0", "", {
218 {0x187, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERFEVTSEL1", "", {
221 {0x198, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_STATUS", "", {
224 {0x199, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_CTL", "", {
227 {0x19a, MSRTYPE_RDWR, MSR2(0,0), "IA32_CLOCK_MODULATION", "", {
230 {0x19b, MSRTYPE_RDWR, MSR2(0,0), "IA32_THERM_INTERRUPT", "", {
233 {0x19c, MSRTYPE_RDWR, MSR2(0,0), "IA32_THERM_STATUS", "", {
236 {0x19d, MSRTYPE_RDWR, MSR2(0,0), "MSR_THERM2_CTL", "", {
239 {0x1a0, MSRTYPE_RDWR, MSR2(0,0), "IA32_MISC_ENABLE", "", {
242 {0x1c9, MSRTYPE_RDWR, MSR2(0,0), "MSR_LASTBRANCH_TOS", "", {
245 {0x1d9, MSRTYPE_RDWR, MSR2(0,0), "IA32_DEBUGCTL", "", {
248 {0x1dd, MSRTYPE_RDWR, MSR2(0,0), "MSR_LER_FROM_LIP", "", {
251 {0x1de, MSRTYPE_RDWR, MSR2(0,0), "MSR_LER_TO_LIP", "", {
254 {0x200, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_BASE0", "", {
257 {0x201, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_MASK0", "", {
260 {0x202, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_BASE1", "", {
263 {0x203, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_MASK1", "", {
266 {0x204, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_BASE2", "", {
269 {0x205, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_MASK2", "", {
272 {0x206, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_BASE3", "", {
275 {0x207, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_MASK3", "", {
278 {0x208, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_BASE4", "", {
281 {0x209, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_MASK4", "", {
284 {0x20a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_BASE5", "", {
287 {0x20b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_MASK5", "", {
290 {0x20c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_BASE6", "", {
293 {0x20d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_MASK6", "", {
296 {0x20e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_BASE7", "", {
299 {0x20f, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_PHYS_MASK7", "", {
302 {0x250, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX64K_00000", "", {
305 {0x258, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX16K_80000", "", {
308 {0x259, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX16K_A0000", "", {
311 {0x268, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_C0000", "", {
314 {0x269, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_C8000", "", {
317 {0x26a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_D0000", "", {
320 {0x26b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_D8000", "", {
323 {0x26c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_E0000", "", {
326 {0x26d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_E8000", "", {
329 {0x26e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_F0000", "", {
332 {0x26f, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_FIX4K_F8000", "", {
335 {0x277, MSRTYPE_RDWR, MSR2(0,0), "IA32_PAT", "", {
338 {0x2ff, MSRTYPE_RDWR, MSR2(0,0), "IA32_MTRR_DEF_TYPE", "", {
341 {0x309, MSRTYPE_RDWR, MSR2(0,0), "IA32_FIXED_CTR0", "", {
344 {0x30a, MSRTYPE_RDWR, MSR2(0,0), "IA32_FIXED_CTR1", "", {
347 {0x30b, MSRTYPE_RDWR, MSR2(0,0), "IA32_FIXED_CTR2", "", {
350 {0x345, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_CAPABILITIES", "", {
353 {0x38d, MSRTYPE_RDWR, MSR2(0,0), "IA32_FIXED_CTR_CTRL", "", {
356 {0x38e, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_GLOBAL_STATUS", "", {
359 {0x38f, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_GLOBAL_CTL", "", {
362 {0x390, MSRTYPE_RDWR, MSR2(0,0), "IA32_PERF_GLOBAL_OVF_CTL", "", {
365 {0x3f1, MSRTYPE_RDWR, MSR2(0,0), "IA32_PEBS_ENABLE", "", {
368 {0x400, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCO_CTL", "", {
371 {0x401, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCO_STATUS", "", {
374 {0x402, MSRTYPE_RDWR, MSR2(0,0), "IA32_MCO_ADDR", "", {
377 {0x403, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC0_MISC", "", {
380 {0x404, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC1_CTL", "", {
383 {0x405, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC1_STATUS", "", {
386 {0x406, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC1_ADDR", "", {
389 {0x407, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC1_MISC", "", {
392 {0x408, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC2_CTL", "", {
395 {0x409, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC2_STATUS", "", {
398 {0x40a, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC2_ADDR", "", {
401 {0x40b, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC2_MISC", "", {
404 {0x40c, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_CTL", "", {
407 {0x40d, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_STATUS", "", {
410 {0x40e, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_ADDR", "", {
413 {0x40f, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC4_MISC", "", {
416 {0x410, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_CTL", "", {
419 {0x411, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_STATUS", "", {
422 {0x412, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_ADDR", "", {
425 {0x413, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC3_MISC", "", {
428 {0x414, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC5_CTL", "", {
431 {0x415, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC5_STATUS", "", {
434 {0x416, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC5_ADDR", "", {
437 {0x417, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC5_MISC", "", {
440 {0x418, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC6_CTL", "", {
443 {0x419, MSRTYPE_RDWR, MSR2(0,0), "IA32_MC6_STATUS", "", {
446 {0x480, MSRTYPE_RDWR, MSR2(0,0), "IA32_VMX_BASIC", "", {
449 {0x481, MSRTYPE_RDWR, MSR2(0,0), "IA32_PINBASED_CTLS", "", {
452 {0x482, MSRTYPE_RDWR, MSR2(0,0), "IA32_PROCBASED_CTLS", "", {
455 {0x483, MSRTYPE_RDWR, MSR2(0,0), "IA32_VMX_EXIT_CTLS", "", {
458 {0x484, MSRTYPE_RDWR, MSR2(0,0), "IA32_VMX_ENTRY_CTLS", "", {
461 {0x485, MSRTYPE_RDWR, MSR2(0,0), "IA32_VMX_MISC", "", {
464 {0x486, MSRTYPE_RDWR, MSR2(0,0), "IA32_VMX_CR0_FIXED0", "", {
467 {0x487, MSRTYPE_RDWR, MSR2(0,0), "IA32_VMX_CR0_FIXED1", "", {
470 {0x488, MSRTYPE_RDWR, MSR2(0,0), "IA32_VMX_CR4_FIXED0", "", {
473 {0x489, MSRTYPE_RDWR, MSR2(0,0), "IA32_VMX_CR4_FIXED1", "", {
476 {0x48a, MSRTYPE_RDWR, MSR2(0,0), "IA32_VMX_VMCS_ENUM", "", {
479 {0x48b, MSRTYPE_RDWR, MSR2(0,0), "IA32_VMX_PROCBASED_CTLS2", "", {
482 {0x600, MSRTYPE_RDWR, MSR2(0,0), "IA32_DS_AREA", "", {
485 {0x107cc, MSRTYPE_RDWR, MSR2(0,0), "MSR_EMON_L3_CTR_CTL0", "", {
488 {0x107cd, MSRTYPE_RDWR, MSR2(0,0), "MSR_EMON_L3_CTR_CTL1", "", {
491 {0x107ce, MSRTYPE_RDWR, MSR2(0,0), "MSR_EMON_L3_CTR_CTL2", "", {
494 {0x107cf, MSRTYPE_RDWR, MSR2(0,0), "MSR_EMON_L3_CTR_CTL3", "", {
497 {0x107d0, MSRTYPE_RDWR, MSR2(0,0), "MSR_EMON_L3_CTR_CTL4", "", {
500 {0x107d1, MSRTYPE_RDWR, MSR2(0,0), "MSR_EMON_L3_CTR_CTL5", "", {
503 {0x107d2, MSRTYPE_RDWR, MSR2(0,0), "MSR_EMON_L3_CTR_CTL6", "", {
506 {0x107d3, MSRTYPE_RDWR, MSR2(0,0), "MSR_EMON_L3_CTR_CTL7", "", {
509 {0x107d8, MSRTYPE_RDWR, MSR2(0,0), "MSR_EMON_L3_GL_CTL", "", {
512 {0xc0000080, MSRTYPE_RDWR, MSR2(0,0), "IA32_EFER", "", {
515 {0xc0000081, MSRTYPE_RDWR, MSR2(0,0), "IA32_STAR", "", {
518 {0xc0000082, MSRTYPE_RDWR, MSR2(0,0), "IA32_LSTAR", "", {
521 {0xc0000084, MSRTYPE_RDWR, MSR2(0,0), "IA32_FMASK", "", {
524 {0xc0000100, MSRTYPE_RDWR, MSR2(0,0), "IA32_FS_BASE", "", {
527 {0xc0000101, MSRTYPE_RDWR, MSR2(0,0), "IA32_GS_BASE", "", {
530 {0xc0000102, MSRTYPE_RDWR, MSR2(0,0), "IA32_KERNEL_GS_BASE", "", {