2 * inteltool - dump all registers on an Intel CPU + chipset based system.
4 * Copyright (C) 2008 by coresystems GmbH
6 * This program is free software; you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation; version 2 of the License.
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
24 #include "inteltool.h"
27 * Egress Port Root Complex MMIO configuration space
29 int print_epbar(struct pci_dev *nb)
31 int i, size = (4 * 1024);
32 volatile uint8_t *epbar;
35 printf("\n============= EPBAR =============\n\n");
37 switch (nb->device_id) {
38 case PCI_DEVICE_ID_INTEL_82945GM:
39 case PCI_DEVICE_ID_INTEL_82945P:
40 epbar_phys = pci_read_long(nb, 0x40) & 0xfffffffe;
42 case 0x1234: // Dummy for non-existent functionality
43 printf("This northbrigde does not have EPBAR.\n");
46 printf("Error: Dumping EPBAR on this northbridge is not (yet) supported.\n");
50 epbar = mmap(0, size, PROT_WRITE | PROT_READ, MAP_SHARED,
51 fd_mem, (off_t) epbar_phys);
53 if (epbar == MAP_FAILED) {
54 perror("Error mapping EPBAR");
58 printf("EPBAR = 0x%08x (MEM)\n\n", epbar_phys);
59 for (i = 0; i < size; i += 4) {
60 if (*(uint32_t *)(epbar + i))
61 printf("0x%04x: 0x%08x\n", i, *(uint32_t *)(epbar+i));
64 munmap((void *)epbar, size);
69 * MCH-ICH Serial Interconnect Ingress Root Complex MMIO configuration space
71 int print_dmibar(struct pci_dev *nb)
73 int i, size = (4 * 1024);
74 volatile uint8_t *dmibar;
77 printf("\n============= DMIBAR ============\n\n");
79 switch (nb->device_id) {
80 case PCI_DEVICE_ID_INTEL_82945GM:
81 case PCI_DEVICE_ID_INTEL_82945P:
82 dmibar_phys = pci_read_long(nb, 0x4c) & 0xfffffffe;
84 case 0x1234: // Dummy for non-existent functionality
85 printf("This northbrigde does not have DMIBAR.\n");
88 printf("Error: Dumping DMIBAR on this northbridge is not (yet) supported.\n");
92 dmibar = mmap(0, size, PROT_WRITE | PROT_READ, MAP_SHARED,
93 fd_mem, (off_t) dmibar_phys);
95 if (dmibar == MAP_FAILED) {
96 perror("Error mapping DMIBAR");
100 printf("DMIBAR = 0x%08x (MEM)\n\n", dmibar_phys);
101 for (i = 0; i < size; i += 4) {
102 if (*(uint32_t *)(dmibar + i))
103 printf("0x%04x: 0x%08x\n", i, *(uint32_t *)(dmibar+i));
106 munmap((void *)dmibar, size);
111 * PCIe MMIO configuration space
113 int print_pciexbar(struct pci_dev *nb)
115 uint32_t pciexbar_reg;
116 uint32_t pciexbar_phys;
117 volatile uint8_t *pciexbar;
118 int max_busses, devbase, i;
121 printf("========= PCIEXBAR ========\n\n");
123 switch (nb->device_id) {
124 case PCI_DEVICE_ID_INTEL_82945GM:
125 case PCI_DEVICE_ID_INTEL_82945P:
126 pciexbar_reg = pci_read_long(nb, 0x48);
128 case 0x1234: // Dummy for non-existent functionality
129 printf("Error: This northbrigde does not have PCIEXBAR.\n");
132 printf("Error: Dumping PCIEXBAR on this northbridge is not (yet) supported.\n");
136 if (!(pciexbar_reg & (1 << 0))) {
137 printf("PCIEXBAR register is disabled.\n");
141 switch ((pciexbar_reg >> 1) & 3) {
143 pciexbar_phys = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28));
147 pciexbar_phys = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27));
151 pciexbar_phys = pciexbar_reg & ((1 << 31)|(1 << 30)|(1 << 29)|(1 << 28)|(1 << 27)|(1 << 26));
155 printf("Undefined address base. Bailing out.\n");
159 printf("PCIEXBAR: 0x%08x\n", pciexbar_phys);
161 pciexbar = mmap(0, (max_busses * 1024 * 1024), PROT_WRITE | PROT_READ,
162 MAP_SHARED, fd_mem, (off_t) pciexbar_phys);
164 if (pciexbar == MAP_FAILED) {
165 perror("Error mapping PCIEXBAR");
169 for (bus = 0; bus < max_busses; bus++) {
170 for (dev = 0; dev < 32; dev++) {
171 for (fn = 0; fn < 8; fn++) {
172 devbase = (bus * 1024 * 1024) + (dev * 32 * 1024) + (fn * 4 * 1024);
174 if (*(uint16_t *)(pciexbar + devbase) == 0xffff)
177 /* This is a heuristics. Anyone got a better check? */
178 if( (*(uint32_t *)(pciexbar + devbase + 256) == 0xffffffff) &&
179 (*(uint32_t *)(pciexbar + devbase + 512) == 0xffffffff) ) {
181 printf("Skipped non-PCIe device %02x:%02x.%01x\n", bus, dev, fn);
186 printf("\nPCIe %02x:%02x.%01x extended config space:", bus, dev, fn);
187 for (i = 0; i < 4096; i++) {
189 printf("\n%04x:", i);
190 printf(" %02x", *(pciexbar+devbase+i));
197 munmap((void *)pciexbar, (max_busses * 1024 * 1024));